+

WO1996042169A1 - Decodeur video a processeur mpeg specialise - Google Patents

Decodeur video a processeur mpeg specialise Download PDF

Info

Publication number
WO1996042169A1
WO1996042169A1 PCT/US1996/008971 US9608971W WO9642169A1 WO 1996042169 A1 WO1996042169 A1 WO 1996042169A1 US 9608971 W US9608971 W US 9608971W WO 9642169 A1 WO9642169 A1 WO 9642169A1
Authority
WO
WIPO (PCT)
Prior art keywords
frame
processor
mpeg
data
decompression
Prior art date
Application number
PCT/US1996/008971
Other languages
English (en)
Inventor
Soma Bhattacharjee
Charles C. Stearns
Original Assignee
S3, Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S3, Incorporated filed Critical S3, Incorporated
Publication of WO1996042169A1 publication Critical patent/WO1996042169A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/414—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
    • H04N21/4143—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance embedded in a Personal Computer [PC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream

Definitions

  • This invention relates to data decompression, and specifically to decompression of MPEG compressed video data in a computer system.
  • the well-known MPEG (Motion Picture Experts Group) data standard defines a compression/decompression process, conventionally called MPEG 1.
  • the MPEG 1 standard is described in the ISO publication No. ISO/IEC 11172: 1993(E), "Coding for moving pictures and associated audio ... " , incorporated by reference herein in its entirety.
  • the MPEG standard defines the format of compressed audio and video data especially adapted for e.g., motion pictures or other live video. MPEG compression is also suitable for other types of data including still pictures, text, etc.
  • the MPEG standard in brief defines the data format structure shown in Figure 1 for CD-ROM content.
  • the top required layer is the MPEG system layer having underneath it, in parallel, the video layer and audio layer.
  • the MPEG system layer contains control data describing the video and audio layers.
  • the MPEG system layer is another (optional) layer called the White book (“video CD”) or the Green book (“CDI”) that includes more information about the particular program (movie) .
  • the book layer could include Karaoke type information, high resolution still images, or other data about how the program content should appear on the screen.
  • the video layer includes sequence (video) , picture (frame) , slice (horizontal portions of a frame) , macroblock (64 pixels by 64 pixels) and block (8 pixels by 8 pixels) layers, the format of each of which is described in detail by the MPEG standard.
  • chips for MPEG decompression. Examples are those sold by C-Cube Microsystems and called the CL-450 and CL-480 products. In these products the MPEG audio and visual decompression (of all layers) is accomplished completely in dedicated circuitry in an internally programmable microcontroller. The book layer and entire MPEG system layer parsed to the last pixel of the compressed data are decompressed using the C-Cube Microsystems products. Thus these chips accomplish the entire decompression on their own, because these chips are intended for use in consumer type devices (not computers) . Thus these chips include a system memory, a CD-ROM controller and any necessary processing power to perform complete MPEG decompression.
  • the MPEG (compressed using layers) content of video data is decompressed in a computer system typically already including a microprocessor, graphics accelerator, frame buffer, peripheral bus and system memory.
  • a shared computational approach between the microprocessor (host processor) , graphics accelerator and a dedicated device makes best use of the computer system existing resources. This is a significant advantage over the prior art where the MPEG decompression is performed entirely by a dedicated processor.
  • a video decoder engine (VDE) in accordance with one embodiment of the present invention is a fast hardwired engine (processor) specifically to perform MPEG 1 video decompression.
  • the VDE does not perform the complete video stream layer decompression but handles decompression from the picture layer downwards, i.e. picture layer, slice layer, acroblock layer and block layer.
  • the VDE is programmed to decode (decompress) on a frame by frame basis and does the variable length decoding (VLD) starting at the picture layer, Inverse Zig-Zag (IZZ) , Inverse Quantization (IQ) and Inverse Discrete Cosine Transfor (IDCT) , and frame reconstruction (motion vector compensation) on a block by block basis until the end of a picture.
  • VLD variable length decoding
  • IZZ Inverse Zig-Zag
  • IQ Inverse Quantization
  • IDCT Inverse Discrete Cosine Transfor
  • frame reconstruction motion vector compensation
  • This unique partitioning method between software and hardware video decompression is well suited for audio/video synchronization, because at any state the VDE can begin to compress a new picture (frame) and abandon decompressing the current picture (frame) . Such incompletely decompressed pictures are not displayed, causing them to be dropped and may cause display of less than 30 frames per second.
  • Graceful degradation allows dropping of video frames when host processor, PCI bus or memory bandwidth is consumed, or when audio synchronization demands it. Dropping video frames to remain synchronized is acceptable perceptually; so long as one only occasionally drops video frames, the effect is hardly noticeable.
  • the VDE circuitry operates at high speed, so that frames are dropped only rarely because the VDE lacks time to decode a frame.
  • the VDE is implemented as a three stage pipeline: VLD (first stage) , IQ, IZZ, IDCT (second stage) and FR (Frame reconstruction) as the third stage. Since the circuitry to perform IQ and IDCT is similar, they are combined into one pipeline stage.
  • the inverse zigzag process is transparent; the VLD output is read from an input buffer in a zigzag manner and written to an output buffer after IQ in inverse zigzag manner.
  • the VLD is implemented without any structural memories (i.e., is RAMless and ROMless) .
  • Figure 2 shows one embodiment of the invention with partitioning of decompression including a dedicated MPEG processor with associated private memory, in a computer.
  • Figure 3 shows a second embodiment of the invention also with a dedicated MPEG processor in a computer.
  • Figure 4 shows a third embodiment of the invention with partitioning of MPEG compression in a computer system using a high performance graphics accelerator.
  • Figure 5 shows a block diagram of a chip including MPEG video and audio decompression in accordance with the invention.
  • Figure 6 shows host processor/VDE partitioning of video decompression.
  • Figure 7 shows graceful degradation of video decompression by abandoning frames.
  • Figure 8 shows in a block diagram three stage pipelining in the VDE.
  • Figure 9 shows a transparent IZZ process.
  • Figures 10A and 10F show a flowchart for a computer program for performing higher level video decompression in a host processor. Identical reference numbers in different figures refer to similar or identical structures.
  • each element in a computer system has particular strength and weaknesses.
  • the microprocessor host processor
  • the microprocessor is typically the single most capable and expensive circuit in a computer system. It is intended to execute a single instruction stream with control flow and conditional branching in minimum time. Due to its internal arithmetic units, the microprocessor has high capability for data parsing and data dependent program execution. However, the microprocessor is less capable at transferring large quantities of data, especially data originating from peripheral elements of the computer.
  • the core logic chip set of a computer interfaces the microprocessor to the peripherals, manages the memory subsystem, arbitrates usage and maintains coherency. However, it has no computational capabilities of its own.
  • the graphics subsystem manages and generates the data which is local to the frame buffer for storing video and graphics data.
  • the graphics subsystem has a capability to transfer large amounts of data but is not optimized for control flow conditional branching operation.
  • each layer has certain characteristics requiring particular hardware (circuit) properties to parse that level of information.
  • the information resembles a program data/code data stream and in fact may contain executable code (software) .
  • the information at that level is thus like a program code stream containing control flow information, variable assignments and data structures.
  • the microprocessor is suited for parsing such information.
  • parsing herein indicates the steps necessary to decompress data each layer of the type defined by the MPEG standard.
  • the video layer under the system layer, includes the compressed video content.
  • VLD variable length decoding
  • IZZ inverse zig-zagging
  • IQ inverse quantization
  • IDCT inverse discrete cosine transformation
  • MVC motion vector compensation
  • MVC motion vector compensation
  • FR frame reconstruction
  • MVC requires retrieving large quantities of data from previously decompressed frames to reconstruct new frames. This process requires transferring large amounts of video data and hence is suited for the graphics accelerator conventionally present in a computer system.
  • An example of such a graphics accelerator is the Trident TVP9512, or S3 Inc. Trio 64V.
  • the audio stream layer under the system layer includes the compressed audio content.
  • Audio decompression requires 1) variable length decoding, 2) windowing, and 3) filtering. Since audio sampling rates are lower than pixel (video) sampling rates, computational power and data bandwidth requirements for audio decompression are relatively low. Therefore, a microprocessor may be capable of accomplishing this task completely, assuming it has sufficient computational power available.
  • the MPEG decompression process is partitioned between the various hardware components in a computer system according to the computational and data bandwidth requirements of the MPEG decompression.
  • the system partitioning depends on the processing power of the microprocessor. Therefore, while the present invention is applicable to computers including various microprocessors of the types now commercially and to be available, the following description is of a computer systems having a particular class of microprocessor (the 486DX2 class microprocessors commercially available from e.g., Intel and Advanced Micro Devices.) Thus this description is illustrative and the principles disclosed herein are applicable to other types of computer systems including other microprocessors of all types.
  • microprocessor 30 (the host processor) has been found only to have computational power sufficient to decompress the MPEG book layer and system layer.
  • the graphics accelerator 40 e.g., the Trio 64V chip from S3 Inc. has insufficient computing power to accomplish the motion vector compensation (MVC) decompression. Therefore, a dedicated processor called the MPEG accelerator 46 is provided to perform the remainder of the MPEG decompression tasks.
  • the MPEG accelerator 46 may be any suitable processor or dedicated logic circuit adapted for performing the required functions.
  • the private memory 44 is e.g. one half megabyte of random access memory used to accomplish the MVC and is distinct from the frame buffer in the Figure 1 embodiment.
  • MPEG accelerator connects (see dotted lines) directly to graphics accelerator 40 for video decompression and to sound system 50 for audio decompression, not via peripheral bus 42. This version would be typical where MPEG accelerator 46 is located on the motherboard of the computer.
  • the lower layer MPEG decompression includes the functions performed by the private memory 44 and the MPEG accelerator 46.
  • the upper layer decompression is that performed by microprocessor 30.
  • the source of the MPEG program material is a CD-ROM to be played on CD-ROM player 52.
  • the program material may be provided from other means such as an external source.
  • FIG. 3 A second embodiment is shown in Figure 3. Again, here the 486 class microprocessor 30 has sufficient computational power only to decompress the book layer and the system layer. In this embodiment a more capable graphics accelerator 40A has the capability to perform the MPEG decompression motion vector compensation (MVC) . Therefore, the memory requirement for accomplishing MVC, which was accomplished by the private memory 44 in Figure 2, here takes place either in the frame buffer 38 or the system memory 36.
  • MVC MPEG decompression motion vector compensation
  • the lower layer decompression includes the functions performed by the graphics accelerator 40A, unlike the case with Figure 2.
  • the Figure 3 embodiment like that of Figure 12, has two versions as shown by the dotted lines.
  • MPEG accelerator 46 communicates via peripheral bus 42.
  • MPEG accelerator 46 is directly connected to sound system 50 for audio decompression and to graphics accelerator 40A for video decompression.
  • a third embodiment is shown in Figure 4.
  • the MPEG accelerator functionality is included in a yet more powerful graphics accelerator 4OB (a graphics controller) .
  • the memory storage requirements for motion vector compensation (MVC) are satisfied by the off-screen memory in the frame buffer 38 or a non-cacheable portion of the system memory 36.
  • MVC motion vector compensation
  • the decompression of the audio layer is performed by either the sound system 50, the graphics accelerator 40A, or the microprocessor 30.
  • the audio decompression process may be partitioned between various elements of a computer system.
  • the remainder of the decompression tasks are off-loaded to a dedicated MPEG accelerator (processor) circuit, or to a graphics accelerator already conventionally present in a computer system on a layer-by-layer basis.
  • a dedicated MPEG accelerator processor
  • a graphics accelerator already conventionally present in a computer system on a layer-by-layer basis.
  • FIG. 5 shows a high level block diagram of a chip which includes the MPEG accelerator 46 of for instance Figure 2.
  • This chip provides both video and audio decompression.
  • the video decompression is of the type disclosed herein and the audio decompression is of the type disclosed in the above-referenced copending and commonly owned patent application.
  • the chip includes a video decompression module 60 which includes a video decompression engine (VDE) , an audio decompression module which includes an audio decompression engine 64, and a synchronization module 62 for synchronizing the video and audio in their decompressed forms.
  • the VDE is a hardwired (circuitry) engine.
  • an audio display module 66 which provides the function of sending decompressed digital audio data to an external DAC.
  • An arbiter 68 arbitrates amongst the various modules for purposes of private memory access. Also provided is a conventional memory controller 70 which interfaces with the private memory 44 of Figure 2. Also provided is a peripheral master and slave bus interface 72 interfacing to the peripheral bus (PCI bus) 42.
  • PCI bus peripheral bus
  • the host processor decompresses the sequence layer and programs the quantization matrices in the VDE, and then parses the group of pictures layer and programs the VDE to start a frame decompression after it has transferred enough data into the buffer used by the VDE for the input video bit stream.
  • the registers used for programming the VDE are double buffered so that the host processor can program one set at the same time that the VDE uses another set of registers.
  • the VDE performs the rest of the variable length decoding starting from the picture layer down to block layer and does the IQ, IZZ, IDCT and FR on the 8x8 blocks generated by the VLD until the end of a picture, or until programmed to abort a picture.
  • the FR puts decompressed frames in memory. Since the display and decompression order are different, the host processor keeps track of when a frame is ready to be displayed and programs the video decompression module to burst out data to be displayed.
  • the master controller 82 in the VDE interfaces to the host processor (not shown) and controls the flow of data through the pipeline stages VLD 84, IQ/IZZ/IDCT 88 and FR 92.
  • the master controller 82 When the master controller 82 is programmed to abort a frame, it resets the main state machines in VLD 84, IQ/IZZ/IDCT 88 and FR 92 and starts a new frame decoding.
  • the VDE aborts a frame, it signals the display engine (not shown) to suppress displaying the frame.
  • the abort and suppress are usually done to B type frames to minimize the effect on quality, because if I or P type frames are aborted, all the intervening P and B type frames need to be discarded until the next I type frame.
  • the circuitry is in one embodiment overdesigned to be very fast such that this feature (to abort frames due to lack of time) is rarely needed, so that the quality of video and video/audio synchronization is good.
  • the P frame can be given longer time and the next B frame can be abandoned.
  • the VDE is implemented as a three stage pipeline with the master controller 82 controlling the interaction between three pipeline stages.
  • the first pipeline stage is the VLD 84
  • the second is the IQ/IZZ/IDCT 88
  • the third stage is the frame reconstruction (FR) 92.
  • Stages 84, 88, 92 are chosen such that the circuitry associated with each stage is unique. For example, since IQ and IDCT both need a multiplier they are in the same stage to avoid duplicating the multiplier.
  • Another advantage of three stages is that operation is pipelined and all three stages can operate simultaneously, reducing the overall time to decode with minimal circuitry.
  • temporary buffer BUFFER A 96 is placed between first and second stages and two buffers BUFFER B, BUFFER C 100, 102 between the second and third stages, so that IQ/IZZ/IDLT 88 and FR 92 work on different buffers.
  • the master controller 82 controls and enables the flow of information from the VLD 84 to IQ/IZZ/IDCT 88 and FR 92. Master controller 82 makes sure that the VLD 84 is two blocks ahead of FR 92 and IQ/IZZ/IDCT 88 is one block ahead of FR 92 during normal operation. In case of skipped macroblocks or in case of a warning caused by a bad variable length code detected by VLD 84, the master controller 82 stalls the VLD 84 and IQ/IZZ/IDCT 88 stages until the FR 92 has finished reconstructing the skipped macroblocks (or the error blocks in case of the warning) .
  • the IQ step according to the MPEG 1 specification involves two multiplications, two additions and one saturation operation.
  • two adders and one multiplier are provided to complete the IQ in an optimal number of cycles with minimum circuitry.
  • the IDCT calculations involve 11 multiplications and 29 additions per row/ column.
  • one multiplier and two adders are used to obtain optimal balance between circuitry and cycles to complete the IDCT.
  • IDCT reads rows of data from a buffer and writes back the result after ID-IDCT into the same buffer.
  • IDCT then reads columns of data from the same buffer and does ID-IDCT and writes them back as columns. Because of this, IDCT avoids doing a transpose operation after the ID-IDCT on the 8 rows and avoids using a transpose RAM (saving cycles and circuitry respectively) .
  • the shuffle operation (part of a well-known algorithm) is a transparent operation going directly to the second stage 88 and reading from the correct locations. In the above example using (1) and (2) this becomes:
  • IZZ is performed transparently during IQ.
  • the DCT coefficients are read in zigzag order from the
  • VLD output buffer go through IQ and are written to the
  • IQ/IZZ/IDCT buffers 100, 102 in raster scan order as shown in Figure 9.
  • IQ matrix 104 stores the quantization coefficients. These are multiplied by the DCT coefficients and the quantization scale factors
  • the VLD module is in one embodiment purely synthesized logic with no structured memories, i.e. no ROM, RAM or PLA. All the look-up tables are implemented with logic. This advantageously eliminates any need for read only memory.
  • MVC motion vector calculation requires different circuitry (adder and combinational logic) compared to the rest of the VLD. This speeds up the VLD because the motion vector calculation does not stall the rest of the VLD. Also in this case the same circuitry is used for all four motion vector calculations-motion horizontal forward, motion horizontal backward, motion vertical forward and motion vertical backward-thereby reducing needed circuitry.
  • FIG. 10A shows the MPEG driver modules.
  • This MPEG driver includes code for video decompression, audio decompression and synchronization therebetween.
  • the right hand side of Figure 10A shows the video decompression, i.e. VDE code, modules. This includes six modules which respectively represent VDE initialization, open, add packet, decode, close and exit. Detail of each of these modules is shown in Figures 10B through 10F on a step by step basis.
  • This flow chart is self explanatory to one of ordinary skill in the art, and therefore its content is not repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

L'invention se rapporte à la décompression de données vidéo comprimées selon les normes du Groupe d'experts en images animées (MPEG) dans un système informatique. Cette décompression comprend un partage des tâches de calcul inhérentes à la décompression entre le microprocesseur central du système, l'accélérateur graphique et un processeur MPEG spécialisé (moteur de décodage vidéo) afin de tirer le meilleur parti des ressources du système informatique. De la sorte, le processeur MPEG spécialisé est doté d'une capacité minimum et offre l'avantage d'un coût minimum. Le microprocesseur central accomplit la décompression des couches de données supérieures MPEG. Plus le microprocesseur central est puissant, plus le nombre de couches de données supérieures dont il effectue la décompression est important. Le reste des opérations de décompression (couches de données inférieures) incombent au processeur MPEG spécialisé et/ou à l'accélérateur graphique. Le moteur de décodage vidéo est un processeur cablé rapide. Sa capacité de dégradation souple permet les pertes occasionnelles d'images vidéo sans affichage d'une partie quelconque d'une image vidéo perdue. Le moteur de décodage vidéo a une structure en pipeline en trois étages, ce qui permet de réduire au minimum les circuits et d'accélérer le fonctionnement.
PCT/US1996/008971 1995-06-12 1996-06-12 Decodeur video a processeur mpeg specialise WO1996042169A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/490,322 US5818967A (en) 1995-06-12 1995-06-12 Video decoder engine
US490,322 1995-06-12

Publications (1)

Publication Number Publication Date
WO1996042169A1 true WO1996042169A1 (fr) 1996-12-27

Family

ID=23947555

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/008971 WO1996042169A1 (fr) 1995-06-12 1996-06-12 Decodeur video a processeur mpeg specialise

Country Status (2)

Country Link
US (1) US5818967A (fr)
WO (1) WO1996042169A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0859322A2 (fr) 1997-02-17 1998-08-19 Sony Corporation Détermination de sous-fonctions de dispositifs dans un environnement P1394
WO1999012126A1 (fr) * 1997-09-04 1999-03-11 Electronics And Telecommunications Research Institute Procede informatique de degradation progressive utilisant des informations prioritaires dans une situation d'objets multiples
EP0847204A3 (fr) * 1996-12-03 2000-03-01 STMicroelectronics, Inc. Décompresseur vidéo multistandard

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9501736D0 (en) * 1995-01-30 1995-03-22 Snell & Wilcox Ltd Video signal processing
JP3053781B2 (ja) * 1997-03-18 2000-06-19 沖電気工業株式会社 動画像圧縮符号の復号方法及び復号装置
US5986714A (en) * 1997-06-10 1999-11-16 International Business Machines Corporation Method, apparatus and computer program product for selectively reducing bandwidth of real-time video data
US6304297B1 (en) * 1998-07-21 2001-10-16 Ati Technologies, Inc. Method and apparatus for manipulating display of update rate
JP3324556B2 (ja) * 1999-04-13 2002-09-17 日本電気株式会社 映像記録方式
WO2002015591A1 (fr) * 2000-08-16 2002-02-21 Koninklijke Philips Electronics N.V. Procede pour reproduire des donnees multimedias
CN1265645C (zh) * 2000-08-29 2006-07-19 皇家菲利浦电子有限公司 运行一种算法的方法以及一种可伸缩编程的处理设备
US6618445B1 (en) * 2000-11-09 2003-09-09 Koninklijke Philips Electronics N.V. Scalable MPEG-2 video decoder
US20040071216A1 (en) * 2000-12-21 2004-04-15 Richardson John William Delivering video over an ATM/DSL network using a multi-layered video coding system
CN1245839C (zh) * 2001-07-04 2006-03-15 矽统科技股份有限公司 分散式视频数据流解码方法
US7079692B2 (en) * 2001-07-24 2006-07-18 Koninklijke Philips Electronics N.V. Reduced complexity video decoding by reducing the IDCT computation in B-frames
US8284844B2 (en) 2002-04-01 2012-10-09 Broadcom Corporation Video decoding system supporting multiple standards
FR2854263A1 (fr) * 2003-04-24 2004-10-29 St Microelectronics Sa Procede d'execution de taches concurrentes par un sous-systeme gere par un processeur central
US7983342B2 (en) * 2004-07-29 2011-07-19 Stmicroelectronics Pvt. Ltd. Macro-block level parallel video decoder
US7191086B1 (en) 2005-01-04 2007-03-13 Advanced Micro Devices, Inc. System for verifying media video decoding capability of a software model
KR20060105890A (ko) * 2005-03-31 2006-10-12 삼성전자주식회사 디지털 방송 수신 장치 및 그 장치에서의 동기화 처리 방법
JP5063866B2 (ja) * 2005-04-14 2012-10-31 オリンパスメディカルシステムズ株式会社 画像表示装置
US7801224B1 (en) * 2005-10-17 2010-09-21 Advanced Micro Devices, Inc. Optimizing decoders on a hardware platform that supports video acceleration
US8238415B2 (en) * 2006-02-14 2012-08-07 Broadcom Corporation Method and system for programmable breakpoints in an integrated embedded image and video accelerator
JP4876969B2 (ja) * 2007-02-26 2012-02-15 ソニー株式会社 画像処理システム、情報処理装置、画像処理方法、及びプログラム
JP5105191B2 (ja) * 2008-10-08 2012-12-19 株式会社メガチップス 画像処理装置
US9532059B2 (en) 2010-10-05 2016-12-27 Google Technology Holdings LLC Method and apparatus for spatial scalability for video coding
US8989256B2 (en) 2011-05-25 2015-03-24 Google Inc. Method and apparatus for using segmentation-based coding of prediction information
US9247257B1 (en) 2011-11-30 2016-01-26 Google Inc. Segmentation based entropy encoding and decoding
US9094681B1 (en) 2012-02-28 2015-07-28 Google Inc. Adaptive segmentation
US9332276B1 (en) 2012-08-09 2016-05-03 Google Inc. Variable-sized super block based direct prediction mode
US9380298B1 (en) 2012-08-10 2016-06-28 Google Inc. Object-based intra-prediction
TWI681362B (zh) * 2018-03-01 2020-01-01 瑞昱半導體股份有限公司 有限記憶體頻寬系統及其動態限制圖形處理器的記憶體頻寬的方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0376469A (ja) * 1989-08-18 1991-04-02 Fujitsu Ltd 可変長符号の復号回路
EP0498544A2 (fr) * 1991-02-04 1992-08-12 International Business Machines Corporation Unité d'expansion de multimédia
EP0545323A1 (fr) * 1991-11-30 1993-06-09 Sony Corporation Système de décodage d'images animées
EP0572766A2 (fr) * 1992-06-04 1993-12-08 International Business Machines Corporation Architecture à tâche pipe-line pour le traitement d'image vidéo
EP0591944A2 (fr) * 1992-10-07 1994-04-13 Nec Corporation Système pour la compression et la reconstruction synchrone
US5329318A (en) * 1993-05-13 1994-07-12 Intel Corporation Method for optimizing image motion estimation
WO1996020567A1 (fr) * 1994-12-23 1996-07-04 Cirrus Logic, Inc. Unite de commande de memoire pour decoder et afficher une image video compressee

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2062200A1 (fr) * 1991-03-15 1992-09-16 Stephen C. Purcell Processeur de decompression pour applications video
US5212742A (en) * 1991-05-24 1993-05-18 Apple Computer, Inc. Method and apparatus for encoding/decoding image data
US5335321A (en) * 1992-06-19 1994-08-02 Intel Corporation Scalable multimedia platform architecture
US5394534A (en) * 1992-09-11 1995-02-28 International Business Machines Corporation Data compression/decompression and storage of compressed and uncompressed data on a same removable data storage medium
US5493339A (en) * 1993-01-21 1996-02-20 Scientific-Atlanta, Inc. System and method for transmitting a plurality of digital services including compressed imaging services and associated ancillary data services
US5452466A (en) * 1993-05-11 1995-09-19 Teknekron Communications Systems, Inc. Method and apparatus for preforming DCT and IDCT transforms on data signals with a preprocessor, a post-processor, and a controllable shuffle-exchange unit connected between the pre-processor and post-processor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0376469A (ja) * 1989-08-18 1991-04-02 Fujitsu Ltd 可変長符号の復号回路
EP0498544A2 (fr) * 1991-02-04 1992-08-12 International Business Machines Corporation Unité d'expansion de multimédia
EP0545323A1 (fr) * 1991-11-30 1993-06-09 Sony Corporation Système de décodage d'images animées
EP0572766A2 (fr) * 1992-06-04 1993-12-08 International Business Machines Corporation Architecture à tâche pipe-line pour le traitement d'image vidéo
EP0591944A2 (fr) * 1992-10-07 1994-04-13 Nec Corporation Système pour la compression et la reconstruction synchrone
US5329318A (en) * 1993-05-13 1994-07-12 Intel Corporation Method for optimizing image motion estimation
WO1996020567A1 (fr) * 1994-12-23 1996-07-04 Cirrus Logic, Inc. Unite de commande de memoire pour decoder et afficher une image video compressee

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
FANDRIANTO ET AL.: "A Programmable Solution for Standard Video Compression", COMPCON '92, 24 February 1992 (1992-02-24), SAN FRANCISCO, US, pages 47 - 50, XP000340716 *
NORTHCUTT ET AL.: "A High Resolution Video Workstation", SIGNAL PROCESSING: IMAGE COMMUNICATION, vol. 4, 1992, ELSEVIER, NL, pages 445 - 455, XP000293760 *
PATENT ABSTRACTS OF JAPAN vol. 15, no. 246 (E - 1081) 24 June 1991 (1991-06-24) *
STOJANCIC ET AL.: "Architecture and VLSI Implementation of the MPEG-2:MP@ML Video Decoding Process", SMPTE JOURNAL, vol. 104, no. 2, February 1995 (1995-02-01), WHITE PLAINS, NY, US, pages 62 - 72, XP000496038 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847204A3 (fr) * 1996-12-03 2000-03-01 STMicroelectronics, Inc. Décompresseur vidéo multistandard
EP0859322A2 (fr) 1997-02-17 1998-08-19 Sony Corporation Détermination de sous-fonctions de dispositifs dans un environnement P1394
WO1999012126A1 (fr) * 1997-09-04 1999-03-11 Electronics And Telecommunications Research Institute Procede informatique de degradation progressive utilisant des informations prioritaires dans une situation d'objets multiples
US7062097B2 (en) 1997-09-04 2006-06-13 Electronics And Telecommunications Research Institute Computational graceful degradation method using priority information in multiple objects case
US7362906B2 (en) 1997-09-04 2008-04-22 Electronics And Telecommunications Research Institute Computational graceful degradation method using priority information in multiple objects case

Also Published As

Publication number Publication date
US5818967A (en) 1998-10-06

Similar Documents

Publication Publication Date Title
US5818967A (en) Video decoder engine
US5778096A (en) Decompression of MPEG compressed data in a computer system
KR100298533B1 (ko) Mpeg비디오압축해제용방법및장치
USRE48845E1 (en) Video decoding system supporting multiple standards
US5812791A (en) Multiple sequence MPEG decoder
US5557538A (en) MPEG decoder
US5774206A (en) Process for controlling an MPEG decoder
US6275239B1 (en) Media coprocessor with graphics video and audio tasks partitioned by time division multiplexing
EP1446953B1 (fr) Systeme et procede de transcodage video de canaux multiples
US8005147B2 (en) Method of operating a video decoding system
US6141721A (en) Method of asynchronous memory access
KR100562116B1 (ko) 처리 효율을 높인 영상음성 처리장치
US6959348B1 (en) Method and system for accessing data
US5774676A (en) Method and apparatus for decompression of MPEG compressed data in a computer system
JPH0759084A (ja) 画像処理システム
JPH06326996A (ja) 圧縮されたビデオデータをデコードする方法及び装置
US6002441A (en) Audio/video subprocessor method and structure
KR100440715B1 (ko) 비디오 디코딩 방법 및 장치
US7675972B1 (en) System and method for multiple channel video transcoding
WO1996036178A1 (fr) Decodeur mpeg a sequence multiple et processus de commande
EP1351513A2 (fr) Procédé de fonctionnement d'un système de décodage vidéo
WO1996042072A1 (fr) Decodeur video de type mpeg
CA2323508A1 (fr) Dispositif et methode permettant d'utiliser de maniere efficace une memoire dans un decodeur video
Lee Architectures and algorithms for MPEG video coding
JPH1141607A (ja) 動画像処理装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载