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WO1996041379A1 - Systemes de circuits integres grandeur plaquette et leur procede de fabrication - Google Patents

Systemes de circuits integres grandeur plaquette et leur procede de fabrication Download PDF

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Publication number
WO1996041379A1
WO1996041379A1 PCT/US1996/010005 US9610005W WO9641379A1 WO 1996041379 A1 WO1996041379 A1 WO 1996041379A1 US 9610005 W US9610005 W US 9610005W WO 9641379 A1 WO9641379 A1 WO 9641379A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated
circuit unit
wafer
circuit
memory
Prior art date
Application number
PCT/US1996/010005
Other languages
English (en)
Inventor
Christophe R. Tretz
Robert C. White
Original Assignee
The Trustees Of Columbia University In The City Of New York
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Trustees Of Columbia University In The City Of New York filed Critical The Trustees Of Columbia University In The City Of New York
Publication of WO1996041379A1 publication Critical patent/WO1996041379A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Definitions

  • the present invention relates generally to semi ⁇ conductor wafer-scale integrated circuits and, more particularly, to a wafer-scale integrated circuit design and layout technique. 5
  • the following published items are representative of proposed wafer-scale integration (WSI) for memory systems:
  • Tazunoki discloses forming a plurality of circuits on a single wafer and describes a technique for interconnecting the circuits.
  • the patent discloses a wafer-scale memory
  • the multiplexer can be configured to form a linear array of cells that achieves a fixed known delay time from function logic to function logic of the cells.
  • U.S. Patent No. 5,214,657 issued May 25, 1993 to Farnworth et al. discloses a semiconductor wafer having a plurality of integrated circuit memory sections which are separated from one another by areas called "street areas". Error detection and correction circuitry is provided within the street areas to detect and correct circuit errors generated within the discrete memory sections.
  • U.S. Patent No. 5,126,828 issued June 30, 1992 to Hatta et al. discloses making cut-outs centrally and/or peripherally to a wafer to allow for an increase in the number of bonding pads for interconnections along the periphery of the wafer. The increase in bonding facilitates communication between circuitry on the wafer and external outside circuitry.
  • U.S. Patent No. 4,038,648 issued July 26, 1977 to Chesley discloses a self-configurable circuit structure for achieving wafer-scale integration. Additionally, a circuit structure is disclosed which accomplishes wafer-scale integration by using dynamic circuit intercoupling capable of subsequent reconfiguration of the intercoupling structure when malfunctions are detected.
  • Preferred integrated-circuit design and layout in a WSI-system or -assembly is such that an integrated- 35 circuit portion having greater yield sensitivity, e.g., the central processor unit (CPU) of a single-chip microcomputer, is disposed in a central region of the semiconductor wafer substrate. Less yield-sensitive units or blocks, e.g., memory arrays are disposed in a peripheral region complementary to the central region. In this fashion, favorable yield can be achieved in the manufacture of high-performance WSI-systems.
  • an integrated- 35 circuit portion having greater yield sensitivity e.g., the central processor unit (CPU) of a single-chip microcomputer
  • Fig. l is a top-view schematic of a single-chip computer in accordance with a preferred embodiment of the invention.
  • the single-chip computer of Fig. 1 has a mostly random-logic CPU 11, several RAM arrays 12 coupled to the microprocessor 11, and several I/O drivers 13 connected to the RAM arrays 12 or/and to the CPU 11, all on a common semiconductor wafer substrate 10.
  • Other or further functional components may be included, such as fuses, for example.
  • the substrate wafer has a size or diameter in a range from 2 to 5 inches.
  • integrated-circuit feature size or design rule is in a range from 0.8 to 2 micrometers approxi- mately.
  • satisfactory yield may be realized with design rules down to approximately 0.35 micrometer.
  • Resulting integrated-circuit assemblies can operate with a power supply in a range from 3 to 5 volts. In operation, such assemblies have desirably low heat dissipation.
  • the microprocessor 11 is disposed centrally on the wafer substrate, occupying an area of approximately 4 cm 2 .
  • the memory arrays 12 are disposed surrounding the microprocessor 11. Each memory array occupies an area of approximately 4 cm 2 and may have up to 64 Mbits of storage capacity. Thus, with 8 memory arrays, the wafer assembly may have a total capacity of 512 Mbits.
  • the I/O drivers 13 are also disposed peripherally, surrounding the memory arrays 12 as shown.
  • VLSI very large scale integrated
  • CMOS complementary metal oxide semiconductor
  • the invention is predicated on the observation that most defects, and especially those affecting pattern processing, tend to be near the periphery of the wafer substrate.
  • most defects, and especially those affecting pattern processing tend to be near the periphery of the wafer substrate.
  • the amount of on-chip fast memory may be so large so as to reduce the amount of cache or external extended memory that is needed.
  • overall execution speed and throughput are enhanced as most or all system/operating software can be held in local memory.
  • Yield sensitivity of an integrated-circuit unit in a system may be understood as directly related to the likelihood of operational failure of the unit due to material defects, and indirectly related to the number of similar units which can substitute in performing its function in the system.
  • a CPU is more yield sensitive than a memory array, and especially so if the CPU is coupled to several memory arrays.
  • memory arrays are less critical also in view of their lesser complexity.
  • a memory array may include redundant cells which, upon suitable address remapping, can be used as substitutes for defective cells, thereby compensating for defects.
  • Testing of a CPU and of surrounding memory units may involve physical contacting with external probes, of contact pads included for this purpose. Since surface area is not at a premium in a wafer-scale assembly, inclusion of a large number of such pads is practicable. More typically, a number of approximately 20 to 30 pads may be sufficient per assembly.
  • Testing may also involve the use of software loaded into the assembly via its input pads. Such software may be designed for testing of the CPU, as well as of memory units connected to the CPU. Test results may be read out at the output pads of the assembly, for example.
  • Reconfiguring may involve physically breaking connections to deficient portions of a memory unit or to a deficient memory unit in its entirety. This typically involves the use of a laser pulse for severing a metallic connection, e.g., in a fuse unit.
  • reconfiguring typically involves software modifications, e.g., for customary logical memory addresses to be translated into appropriate physical addresses of usable memory units and memory cells. Such translation may then be carried out for each store/fetch memory operation in device use.
  • wafer-scale integrated-circuit systems promise to find use, e.g., in high-speed, low-power multimedia processing and communications systems.

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Etant donné que la densité de défauts qui entachent l'efficacité d'un dispositif décroît du centre d'une tranche (10) de semi-conducteur vers sa périphérie, il est possible d'obtenir une meilleure efficacité dans la fabrication de circuits intégrés grandeur plaquette (WSI) lorsqu'on place une unité fonctionnelle plus sensible au rendement au centre de la tranche (10). Par exemple, dans un ordinateur monopuce, on préférera intégrer un processeur central (11) au centre des éléments de mémoires (12).
PCT/US1996/010005 1995-06-07 1996-06-07 Systemes de circuits integres grandeur plaquette et leur procede de fabrication WO1996041379A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47895795A 1995-06-07 1995-06-07
US08/478,957 1995-06-07

Publications (1)

Publication Number Publication Date
WO1996041379A1 true WO1996041379A1 (fr) 1996-12-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/010005 WO1996041379A1 (fr) 1995-06-07 1996-06-07 Systemes de circuits integres grandeur plaquette et leur procede de fabrication

Country Status (1)

Country Link
WO (1) WO1996041379A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1094467A2 (fr) * 1999-10-19 2001-04-25 Motorola, Inc. Unité de traitement avec MRAMS intégrés ayant chacun deux ports de lecture
US6956763B2 (en) 2003-06-27 2005-10-18 Freescale Semiconductor, Inc. MRAM element and methods for writing the MRAM element
US6967366B2 (en) 2003-08-25 2005-11-22 Freescale Semiconductor, Inc. Magnetoresistive random access memory with reduced switching field variation
US7129098B2 (en) 2004-11-24 2006-10-31 Freescale Semiconductor, Inc. Reduced power magnetoresistive random access memory elements
US7184300B2 (en) 2001-10-16 2007-02-27 Freescale Semiconductor, Inc. Magneto resistance random access memory element

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04130656A (ja) * 1990-09-20 1992-05-01 Mitsubishi Electric Corp 半導体集積回路
US5300796A (en) * 1988-06-29 1994-04-05 Hitachi, Ltd. Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells
US5386129A (en) * 1991-09-13 1995-01-31 Nec Corporation Power supply system of semiconductor chip for optimizing impedances of power supply sub-systems associated with outside and inside function blocks
US5410161A (en) * 1991-07-12 1995-04-25 Nec Corporation Semiconductor device equipped with characteristic checking element

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300796A (en) * 1988-06-29 1994-04-05 Hitachi, Ltd. Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells
JPH04130656A (ja) * 1990-09-20 1992-05-01 Mitsubishi Electric Corp 半導体集積回路
US5410161A (en) * 1991-07-12 1995-04-25 Nec Corporation Semiconductor device equipped with characteristic checking element
US5386129A (en) * 1991-09-13 1995-01-31 Nec Corporation Power supply system of semiconductor chip for optimizing impedances of power supply sub-systems associated with outside and inside function blocks

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
W.R. RUNYAN and K.E. BEAN, "Semiconductor Integrated Circuit Processing Technology", ADDISON WESLEY, 1990, page 593 and page 637. *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1094467A2 (fr) * 1999-10-19 2001-04-25 Motorola, Inc. Unité de traitement avec MRAMS intégrés ayant chacun deux ports de lecture
EP1094467A3 (fr) * 1999-10-19 2001-05-30 Motorola, Inc. Unité de traitement avec MRAMS intégrés ayant chacun deux ports de lecture
JP2001175641A (ja) * 1999-10-19 2001-06-29 Motorola Inc デュアル・リード・ポートを含む埋め込みｍｒａｍ
SG90176A1 (en) * 1999-10-19 2002-07-23 Motorola Inc Embedded mrams including dual read ports
US6609174B1 (en) 1999-10-19 2003-08-19 Motorola, Inc. Embedded MRAMs including dual read ports
KR100751841B1 (ko) * 1999-10-19 2007-08-24 모토로라 인코포레이티드 내장된 ｍｒａｍ을 갖는 처리 장비와 데이터 처리 장비를 제조하는 방법
US7184300B2 (en) 2001-10-16 2007-02-27 Freescale Semiconductor, Inc. Magneto resistance random access memory element
US6956763B2 (en) 2003-06-27 2005-10-18 Freescale Semiconductor, Inc. MRAM element and methods for writing the MRAM element
US6967366B2 (en) 2003-08-25 2005-11-22 Freescale Semiconductor, Inc. Magnetoresistive random access memory with reduced switching field variation
US7129098B2 (en) 2004-11-24 2006-10-31 Freescale Semiconductor, Inc. Reduced power magnetoresistive random access memory elements

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