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WO1995028668A2 - Dispositif d'affichage d'image et attaqueur de selection et circuit d'attaqueur integre utilisables dans ledit dispositif d'affichage d'image - Google Patents

Dispositif d'affichage d'image et attaqueur de selection et circuit d'attaqueur integre utilisables dans ledit dispositif d'affichage d'image Download PDF

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Publication number
WO1995028668A2
WO1995028668A2 PCT/IB1995/000246 IB9500246W WO9528668A2 WO 1995028668 A2 WO1995028668 A2 WO 1995028668A2 IB 9500246 W IB9500246 W IB 9500246W WO 9528668 A2 WO9528668 A2 WO 9528668A2
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WO
WIPO (PCT)
Prior art keywords
selection
pulse
display device
picture display
electrode
Prior art date
Application number
PCT/IB1995/000246
Other languages
English (en)
Other versions
WO1995028668A3 (fr
Inventor
Terence Doyle
Robert Jan Fronen
Peter Johan Heijnen
Karel Elbert Kuijk
James Joseph Anthony Mccormack
Original Assignee
Philips Electronics N.V.
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics N.V., Philips Norden Ab filed Critical Philips Electronics N.V.
Publication of WO1995028668A2 publication Critical patent/WO1995028668A2/fr
Publication of WO1995028668A3 publication Critical patent/WO1995028668A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J31/00—Cathode ray tubes; Electron beam tubes
    • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
    • H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
    • H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
    • H01J31/123—Flat display tubes
    • H01J31/124—Flat display tubes using electron beam scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/20—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using multi-beam tubes

Definitions

  • Picture display device and selection driver and integrated driver circuit for use in such a picture display device are Picture display device and selection driver and integrated driver circuit for use in such a picture display device.
  • the invention relates to a picture display device having a selection structure for controlling the passage of electrons via extraction locations which communicate row by row with electron transport ducts fed by electron sources and with selection electrodes associated with the extraction locations and coupled to a selection driver for applying selection pulses to the selection electrodes.
  • a picture display device of this type is described in European Patent Application no. 92204007.6 (PHN 13.963) and may comprise a display unit of the flat-panel type as disclosed in European Patent Applications EP-A 0 400 750 and EP-A 0 436 997.
  • Display units of the flat-panel type are constructions having a transparent face plate and, arranged at a small distance therefrom, a rear plate, which plates are interconnected by means of partitions and in which the inner side of the face plate is provided with pixels in the form of a phosphor pattern, one side of which is provided with an electrically conducting coating (the combination also being referred to as luminescent screen). If (video information- controlled) electrons impinge upon the luminescent screen, a visual image is formed which is visible via the front side of the face plate.
  • the face plate may be flat, or if desired, curved (for example, spherical or cylindrical).
  • the display unit described in European Patent Applications EP-A 0 400 750 and EP-A 0 436 997 comprises a plurality of juxtaposed sources for emitting electrons, local electron transport ducts cooperating with the sources and each having walls of high- ohmic, electrically substantially insulating material having a secondary emission coefficient suitable for transporting emitted electrons in the form of electron currents and a selection structure comprising selectively energizable electrodes (selection electrodes) for extracting each electron current from its transport duct at predetermined extraction locations facing the luminescent screen, while further means are provided for directing extracted electrons towards pixels of the luminescent screen for producing a picture composed of pixels.
  • this known display unit is based on the recognition that electron transport is possible when electrons impinge on an inner wall of an elongate evacuated cavity (referred to as "compartment") defined by walls of a high-ohmic, electrically substantially insulating material (for example, glass or synthetic material), if an electric field of sufficient power is generated in the longitudinal direction of the "compartment” (by applying an electric potential difference across the ends of the "compartment”).
  • the impinging electrons then generate secondary electrons by wall interaction, which electrons are attracted to a further wall section and in their turn generate secondary electrons again by wall interaction.
  • a flat-panel picture display unit can be realised by providing each one of a plurality of juxtaposed "compartments", which constitute transport ducts, with a column of extraction apertures at a side which is to face a display screen. It will then be practical to arrange the extraction apertures of adjacent transport ducts along parallel lines extending transversely to the transport ducts.
  • selection electrodes arranged in rows with the arrangement of apertures which selection electrodes are energizable by means of a first (positive) electric voltage (pulse) for extracting electron currents from the "compartments” via the apertures of a row, or which convey a second (lower) electric voltage if no electrons are to be locally extracted from the "compartments”
  • an addressing means is provided with which electrons extracted from the "compartments” can be directed towards the screen for producing an image composed of pixels by activating the pixels.
  • this transport voltage may be approximately 100 V/cm so that a total transport voltage of 3 kV is required for a flat-panel display unit having a height of, for example 30 cm (with one cathode at one side of the panel).
  • the active selection period of a selection pulse covers the time when the electron currents in the electron transport ducts are modulated with video information and these modulated electron currents are extracted from the transport ducts by the selection electrode to which the selection pulse is applied.
  • the invention is based on a dual recognition.
  • the voltage at a selection electrode may be "high" without any problem during the active selection period of an adjacent selection electrode, if this adjacent selection electrode is located in the direction of the electron sources (thus upstream of the electron current in the electron transport ducts) because this adjacent selection electrode will then extract (substantially) all electrons from the electron transport ducts so that the selection pulse can no longer extract (substantially) any electrons from the election transport ducts at the first-mentioned (downstream) selection electrode.
  • the described overlapping of the selection pulses considerably reduces the peak currents to be supplied by the selection driver. This will be elucidated with reference to the Figures.
  • an edge of the selection pulse for said one selection electrode may have a capacitive crosstalk to the active selection period of the pulse for said adjacent selection electrode.
  • the picture display device according to the invention may be further characterized in that the selection pulse for said one selection electrode overlaps at least the entire active selection period of the selection pulse for said adjacent selection electrode to such an extent that no edge of the selection pulse for said one selection electrode occurs during this active selection period.
  • Such a picture display device in which the selection pulses have a first edge and a second edge adjoining the active selection period of the relevant pulse, is preferably characterized in that the second edge of the selection pulse for said one selection electrode coincides with the first edge of the selection pulse for a non-adjacent selection electrode located further in the direction of the electron sources.
  • the above-mentioned selection pulse can be realised in a simple manner because the selection driver comprises output stages which are controlled by charge and discharge bits supplied via a cascade of delay stages, with each delay stage having a delay which is equal to the selection pulse repetition time, while at least two charge bits followed by a multiple of discharge bits are supplied via the cascade of delay stages.
  • the picture display device is characterized in that the selection pulses have a steep and a less steep edge and in that the less steep edge of a selection pulse at least partially overlaps the active selection period of the selection pulse for a selection electrode located in the direction of the electron sources.
  • the selection driver comprises output stages each having charge means and discharge means for charging and discharging the selection electrode connected to the output stage, and in that the dimensions of the discharge means differ essentially from the dimensions of the charge means.
  • the invention also relates to a selection driver for use in a picture display device according to the invention and to an integrated driver circuit for use in such a picture display device.
  • Fig. 1A is a diagrammatic perspective elevational view, partly broken away, of a display unit as can be used in a display device according to the invention
  • Fig. IB is a cross-section through a display unit of Fig. 1 A
  • Fig. 2A is a diagrammatic perspective elevational view, partly broken away, of a display unit as can also be used in a picture display device, which display unit has a preselection and a fine selection
  • Fig. 2B is a cross-section through a display unit of Fig. 2A
  • Fig. 3 shows block-diagrammatically an embodiment of a picture display device in which the invention can be used
  • Figs. 4A, B and C show a detailed circuit of a selection driver already proposed for selection electrodes
  • Fig. 5 shows waveforms of customary selection pulses
  • Figs. 6, 7 and 8 show waveforms of selection pulses in a picture display device according to the invention.
  • Figs. 1 A and IB show a flat-panel display unit 1 of a picture display device according to the invention, having a display panel (window) 3 comprising a transparent face plate and a luminescent screen and a rear wall 4 located opposite said panel.
  • a luminescent screen 7 having a repetitive pattern (rows or dots) of, for example triplets of red (R), green (G) and blue (B) luminescing phosphor elements (or monochrome elements) is arranged on the inner surface of window 3.
  • the luminescent screen 7 is either arranged on a transparent, electrically conducting layer (for example, indium-tin oxide) or is provided with an electrically conducting layer (for example, Al backing).
  • the (dot-shaped) phosphor elements of a triplet are located at the vertices of a substantial isosceles/equilateral triangle.
  • An electron source arrangement 5 for example a line cathode which by means of drive electrodes provides a large number (for example, several hundred) of electron emitters or a similar number of separate emitters, is arranged proximate to a bottom plate 2 which interconnects display panel 3 and rear wall 4. Each of these emitters is to provide a relatively small current so that many types of cathodes (cold or hot cathodes) are suitable as emitters. They may have a constant emission (at pulse width modulation) or a controllable emission (at amplitude modulation).
  • the electron source arrangement 5 is arranged opposite entrance apertures of a row of electron transport ducts extending substantially parallel to the screen, which ducts are constituted by compartments 6, 6', 6", ... etc.
  • each compartment for each electron source has cavities 11, 11', 11", ... defined by the rear wall 4 and partitions 12, 12', 12", ...
  • At least one wall (preferably the rear wall) of each compartment is made of a material which has a suitable high electrical resistance in the longitudinal direction of the compartments for the purpose of the invention (for example, ceramic material, glass, synthetic material - coated or uncoated -) and which have a secondary emission coefficient ⁇ > I over a given range of primary electron energies. It is alternatively possible to construct (for example, the rear wall) from "isles” insulated from each other (in the longitudinal direction of the compartments) so as to obtain the desired high electrical resistance in the transport direction.
  • the electrical resistance of the wall material has such a value in the transport direction that a minimum possible total amount of current (preferably less than, for example, 10 mA) will flow in the walls at a field strength in the axial direction in the compartments of the order of one hundred to several hundred volts per cm required for the electron transport.
  • a voltage Vt which generates the field strength required for the transport is present in operation between an upper rim 200 and a lower rim 201 of the rear wall 4.
  • the electrons are accelerated by said field strength, whereafter they impinge upon the walls in the compartments and generate secondary electrons.
  • the electrons can be extracted, for example row by row from the compartments via apertures 8, 8', ... in a selection plate 10 energized by means of electrodes 9, 9', ... (see Fig. 1A), and accelerated towards the luminescent screen 7 by means of an acceleration voltage applied in operation between the selection plate and the luminescent screen.
  • Horizontal partitions 112, 112', 112", ... are arranged between the display panel 3 and the selection plate 10. Instead of the partitions shown, it is alternatively possible to use apertured plates.
  • the display unit utilizes the aspect disclosed in European Patent Applications EP-A 0 400 750 and EP-A 0 436 997 that vacuum electron transport by means of secondary emission (hopping) within compartments having walls of electrically insulating material is possible if an electric field (E y ) of sufficient power is applied in the longitudinal direction of the compartment.
  • European Patent Applications EP-A 0 400 750 and EP-A 0 436 997 are herein incorporated by reference.
  • Figs. 1A and IB show the principle of a display unit operating with single selection (as described hereinbefore).
  • Figs. 2A and 2B show the principle of stepped selection. Stepped selection is herein understood to mean that the selection from the compartments 6, 6', 6", ... to the luminescent screen 7 is realised in at least two steps.
  • the space between the compartments and the luminescent screen 7, which is arranged on the inner wall of the display panel 3, accommodates an active colour selection system 100 which comprises an (active) preselection plate 10a, a spacer plate 10b and an (active) (fine- )selection plate 10c.
  • Structure 100 is separated from the luminescent screen 7 by a flu-spacer structure 101, for example an apertured electrically insulating plate.
  • Fig. 2B shows in a diagrammatical cross-section a part of the picture display device of Fig. 2A in greater detail, particularly the active colour selection plate structure 100 which comprises a preselection plate 10a with extraction apertures 8, 8', 8", ... and a fine-selection plate 10c with groups of apertures R, G, B.
  • the apertures R, G, B are generally positioned in a triangle, but for the sake of clarity all three of them have been shown in the cross-section in Fig. 2B.
  • Each extraction aperture 8, 8', etc. is associated with three fine-selection apertures R, G, B in this case.
  • Other numbers are alternatively possible, for example 6 fine-selection apertures for each preselection aperture, etc.
  • An intermediate spacer structure 10b is arranged between the preselection plate 10a and the fine-selection plate 10c.
  • This structure accommodates communication ducts 30, 30', 30", ... having a cross-section which is chosen to suit the shape of the phosphor colour pixels (for example, circular or triangular triplets).
  • the electron transport ducts 6, 6', 6", ... are formed between the structure 100 and the rear wall 4. To be able to extract the electrons from the transport ducts 6, 6', 6", ... via the apertures 8, 8', 8", ..., pierced metal preselection electrodes 9, 9', 9", ... are arranged on the screen-sided surface of the plate 10a.
  • the walls of the apertures 8, 8', ... are preferably metallized completely or partly, but there is preferably no or little electrode metal on the surface of plate 10a on 8 the side where the electrons land. This is done to ensure that no electrons remain on a selection electrode during addressing (i.e. the electrode must draw a minimal current).
  • Another solution to the problem of drawing current is to ensure that there is electrode metal on the selection surface where the elections land, but this metal should be given such a large secondary emission coefficient that the preselection electrodes do not draw any net current.
  • the screen-sided surface of the apertured fine- selection plate 10c is provided with (fine-)selection electrodes 13, 13', ... for realising, for example colour selection.
  • the apertures are preferably metallized completely or partly.
  • the possibility of electrically interconnecting fine-selection electrodes is important in this respect. In fact, a preselection for each pixel has already taken place and, in principle, electrons cannot land at the wrong location (on the wrong pixel in this example). This means that, in principle, only one group or a small number of groups of three separate fine- selection electrodes is required for this form of fine selection.
  • the drive is effected as follows, but there are also other possibilities.
  • the preselection electrodes are brought to a potential substantially linearly increasing with the distance to the electron source arrangement 5, for example, by means of a suitable resistance ladder.
  • One or more picture lines are selected by applying a positive voltage pulse of, for example 250 V to the desired preselection electrodes used for selecting these picture lines.
  • Colour pixels are addressed by applying shorter pulses having an amplitude of, for example 350 V to the fine-selection electrodes.
  • the fine-selection electrodes preferably have such an electrical resistance, or are connected to external resistors in such a way that they safeguard the electronic circuits (controlling the drive) against breakdown from the luminescent screen.
  • Fig. 3 shows a picture display device W according to the invention.
  • the display device receives an input video signal Vin at an input 61.
  • the input video signal Vin is applied to a video signal processing circuit 65.
  • the display device receives a synchronizing signal sync at an input 62.
  • the input 62 is connected to a synchronization processing circuit 63.
  • This synchronization processing circuit supplies synchronizing signals to a clock generator 613 and defines the television standard of the incoming video signal.
  • the incoming video signal may comprise, for example, Y, U, V signals (or R,G,B signals). If the incoming video signal comprises Y, U, V signals, a conversion to R, G, B signals will have to take place in the video signal processing circuit 65 so that ultimately the different phosphors (red, green and blue) can be driven on the display panel 3. This conversion of Y, 9
  • U, V signals to R, G, B signals may be effected by means of a matrix circuit. It is possible to carry out this conversion before the video signal is written into the memory MEM, or when the video signal is read from the memory MEM.
  • the video signal is stored, for example, line-sequentially in the video signal processing circuit 65 under the control of a write clock which is generated, for example, by the clock generator 613.
  • the video signal is supplied line by line (for example, for each colour line (R, G, B) when a colour display screen is used) at an output of the video signal processing circuit under the control of a read clock which is generated by a clock generator 614 and is applied to the video drive circuit 34.
  • the video information of, for example a (colour) line is written under the control of the clock generator 614 and subsequently applied in parallel to the Gl (or G2) electrodes which are arranged at the inputs of the compartments 6, 6', 6", ... (see Fig. 1) of the display unit 1, after which the video information is displayed on the display panel 3.
  • the lines are selected by means of a selection controller 611.
  • This controller is controlled by a clock signal from the clock generator 614.
  • the selection driver Dl applies new drive voltages to the selection electrodes 9, 9', 9", ... (see also Fig. 1A) under the control of the selection controller 611.
  • the selection controller 611 also drives a driver for the fine selection D2.
  • This fine-selection driver D2 is then coupled to the fine-selection electrodes 13, 13', 13", ... If the picture display device comprises dummy electrodes 14, 14', 14", ... (to enhance the contrast), the selection controller 611 will also drive a dummy electrode driver D3. This dummy electrode driver drives the dummy electrodes 14, 14', 14", ... The selection controller receives the information about the drive voltages, for example from a look-up table or from an EPROM.
  • the display unit 1 has a structure as described hereinbefore (see Fig. 1, 1A).
  • the synchronization processing circuit 63 defines the line frequency and the field frequency with reference to the incoming video signal and, if the display device is suitable for displaying video signals of different TV standards and/or different aspect ratios, for example also the TV standard and the aspect ratio.
  • the selection electrodes 9, 9', 9", ... must be driven by means of suitable voltages. These voltages may be subdivided into a bias voltage and a selection pulse.
  • the bias voltage is used for transporting the electrons in the transport ducts along the non- selected selection electrodes. Successive selection electrodes may have a bias voltage which increases with their position across the length of the transport ducts.
  • the selection pulse is a pulse of, for example 300 Volt pulse height which is superimposed on the bias voltage for the selection electrode whose turn it is to extract electrons from the transport ducts.
  • Fig. 4A shows a part of a customary selection driver for the selection electrodes 9.
  • the selection driver comprises an integrated circuit I having a plurality of output stages O ⁇ , O n , ... and, for their control, a shift register in the form of a cascade of delay stages D n _ ! , D n , ...
  • the control input of an output stage is connected to each connection between two consecutive delay stages.
  • the control signals are shifted in the form of charge bits and discharge bits via the cascade of delay stages.
  • a charge bit for example a 1-bit appears at the output of the delay stage D n _ !
  • the output stage O n-1 connected thereto starts a selection pulse at the selection electrode 9 n _ 1 .
  • a discharge bit for example a 0-bit appears at the output of the delay stage D, ⁇ , so that the selection pulse of the output stage O ⁇ is ended, while the delayed charge bit appears at the output of the delay stage D n , so that the output stage O n starts supplying a selection pulse, and so forth.
  • the charge bit is applied to the upper one of the delay stages (not shown).
  • the upper delay stage is fed with discharge bits which then move up behind the charge bits.
  • the horizontal rows of extraction apertures 8 in the display unit are thus activated from top to bottom; the display panel is scanned in the downward direction.
  • the display panel may alternatively be scanned in the upward direction and in that case the bits are applied to the lower one of the delay stages, while these control signals should then move from bottom to top through the cascade of delay stages.
  • the selection pulses are applied to the selection electrodes 9 ⁇ . ! , 9 n , ... via coupling capacitors CC n-1 , CC n , ... and via protection resistors RP ⁇ , RP n ,
  • the required bias (transport) voltage is supplied by a series circuit of ladder resistors RL ⁇ , RL,,, ... whose branches are connected to the connections between the coupling capacitors and the protection resistors via separating resistors RS n . ⁇ , RS n , ....
  • a direct current flows through the series circuit of ladder resistors so that the bias voltage for the selection electrodes 9 n .,; 9 n , ... decreases or increases by a given value, for example 6 volts per electrode.
  • the bias voltage will also increase from bottom to top (i.e. with a descending ordinal number), and if on the other hand the electron transport in the electron transport ducts 6 proceeds from top to bottom, the bias voltage will decrease from bottom to top (i.e. with an ascending ordinal number).
  • the separating resistors RS prevent too much voltage of the selection pulses from getting lost via the ladder resistors RL and the protection resistors RP prevent damage of the output stages O at flashes on the selection electrodes.
  • Fig. 4 A shows the most important parasitic capacitances of the selection electrodes, viz. capacitances CE.,. 1 , CE emphasize, ... between adjacent selection electrodes and capacitances CD,,. ! , CD consult, .... between the selection electrodes and the rest of their ambience.
  • Customary values for the elements of Fig. 4A for a 26" (4:3) or a 32" (16:9) display panel may be, for example:
  • CD 38 pF It appears from these values that the parasitic capacitances and particularly the mutual capacitances CE between adjacent selection electrodes are large. This is a result of the large length of the selection electrodes and of the fact that the selection electrodes are located very close together (spaced apart by approximately 0.1 to 0.2 mm).
  • FIGs. 4B and 4C show only those elements of Fig. 4A which are of essential importance for understanding the invention.
  • Each output stage O is shown diagrammatically with charge means, for example a PMOS field effect transistor TC ⁇ , TC complicat, ... and an NMOS field effect transistor TD n- j, TD n , ....
  • the PMOS transistor TC n . ! , TC n , ... is arranged between a high power supply voltage VH ⁇ , VH Trigger, ... and the selection electrode 9 consumer- ⁇ , 9 service, ....
  • the NMOS transistor TD consume.,, TD drain, ... is arranged between a low power supply voltage VL n , ... and the selection electrode.
  • the voltages VL for adjacent selection electrodes may be different or equal.
  • the high voltage VH is always higher by a given value, the pulse height voltage, than the low voltage VL of the same output stage.
  • the coupling capacitors CC and the resistors RL, RS and RP are omitted because they are not of primary importance for the present invention and the invention can therefore also be used in picture display devices as described in European Patent Application (PHN 14.787) in which no coupling capacitors and no resistance ladder are used.
  • Fig. 4B shows the route of the charge currents during the leading edge of a selection pulse at the selection electrode 9 n .
  • the gate electrodes of the transistors TC and TD are controlled by means of the above-described charge and discharge bits in such a way that all transistors TD, except TD n are turned on and all transistors TC, except T , are turned off.
  • a charge current IC fresh flows from the power supply voltage VH companion through the PMOS transistor TC complicate.
  • the current IC n is split up into a current IC" n which charges the capacitance CD remind and two equal currents IC'voicing which charge the equal capacitances CE confuse and CE o+1 .
  • the currents IC' n are depleted via the transistors TD, ⁇ and TD n+1 which are turned on.
  • the voltage at the electrode 9 is charged from VL Bin to VEL, the voltages at the electrodes 9 cable. ⁇ and 9 n+ ⁇ remain low at the values VL n .j and VL-, +1 , respectively.
  • the currents IC'ont are larger than the current IC" formulation because the capacitances CE*, and CE n+1 are larger than the capacitance CD n .
  • Curves V preference. ⁇ to V n+2 in Fig. 5 show the time diagrams of four selection pulses at the consecutive selection electrodes 9 n-1 to 9 n+2 and curves to L ⁇ show the time diagrams of the associated charge and discharge currents.
  • the references T n-2 to T n+2 in this Figure also show the active selection periods of the selection electrodes 9 n . 2 to 9 n+2 .
  • the active selection period of a selection electrode is the period during which video information- controlled electrons are extracted from the electron transport ducts 8 by the relevant selection electrode. This Figure shows that the leading edge of the selection pulse for a given selection electrode coincides with the trailing edge of the directly preceding selection pulse.
  • the curve I Tin shows that the charge current I flows during the leading edge of the selection pulse V n .
  • the trailing edge of the directly preceding selection pulse V n . produces a current ID' n-1 in the selection electrode 9 n
  • the sum of the two currents IC n and of the PMOS transistor TC salt flows to the selection electrode 9 cosmetic.
  • the current to be supplied by the transistor TC neg which also applies to all other PMOS transistors TC, is thus raised by more than 40% (in the above dimensioning example) due to the fact that the leading edge of the selection pulse at the relevant selection electrode coincides with the trailing edge of the directly preceding selection pulse at the adjacent higher selection electrode.
  • the transistors TC should be specially designed for this larger current, which can only be realised in practice by rendering these transistors larger, hence on a larger IC surface area.
  • the transistor TD filing conveys the discharge current ID n during the trailing edge of the selection pulse V render, but due to the fact that this trailing edge coincides with the leading edge of the selection pulse V n+1 at the adjacent lower selection electrode 9 n+1 , the transistor TD filing should also convey the charge current IC' n+1 which thus raises the current through this transistor by approximately 40% again.
  • a method of obviating this current increase in the transistors TC and TD is to render the selection pulses so much shorter that the trailing edge of a selection pulse is ended before the leading edge of the directly succeeding selection pulse starts.
  • Fig. 6 shows a better solution for decreasing the peak currents through the transistors TC and TD.
  • the selection pulses are extended in such a way that the trailing edge of each selection pulse does not start until the leading edge of the next selection pulse has ended. This means that a selection pulse overlaps a part of the active selection period of the next selection pulse.
  • the trailing edge of the selection pulse now falls within the active selection period T n of the selection electrode 9 pharmaceutical and the trailing edge of Vute falls within the active selection period T n+ ⁇ of the selection electrode 9 n+1 , and so forth.
  • the curve shows that the current pulse ID', ⁇ is now shifted with respect to the current pulse IC n and the current pulse ID diary is shifted with respect to the current pulse IC' n+1 .
  • the maximum charge current is not larger than IC n and the maximum discharge current is not larger than ID n . It should be noted that it is assumed in the solution shown in Fig. 6 that the electrons flow from bottom to top in the electron transport ducts while the selection electrodes are scanned from top to bottom. In fact, the extension of the selection pulse V n _ ! then does not result in an (unwanted) extraction of electrons from the electron transport ducts during the period T n because the selection pulse V n has already extracted the electrons coming from the bottom.
  • the selection pulses should therefore be extended in such a way that it at least partially overlaps the active selection period of the selection pulse for the selection electrode which is located in the direction of the electron sources 5 (i.e. upstream of the electron current in the transport ducts).
  • the pulse extension shown in Fig. 6 has the drawback that the trailing edge of a selection pulse, which coincides with the active selection period of the next selection pulse, may have a capacitive crosstalk to this next selection pulse and thus causes a disturbance of the contrast of the displayed image.
  • This capacitive crosstalk results from the fact that the discharge current ID' n . ⁇ at the adjacent selection electrode 9 n causes a voltage change (not shown in Fig. 6) of the selection pulse V n , because the conducting PMOS transistor TC n for the active selection electrode is not sufficiently low-ohmic to keep the voltage at this electrode constant.
  • This crosstalk is even re-inforced by the presence of the protection resistor RP.
  • the selection pulse is preferably extended to such an extent that the trailing edge of this selection pulse does not occur until the active selection period of the next selection pulse has ended, for example during the active selection period of the next pulse.
  • the unwanted crosstalk is prevented by advancing the leading edge of a selection pulse to such an extent that it has already ended before the active selection period of the next selection pulse has started.
  • the selection pulse for a selection electrode is extended to such an extent that no edge thereof coincides with the active selection period of the selection pulse for the adjacent selection electrode located in the direction of the electron sources.
  • the crosstalk may be further reduced if the trailing edge of each selection pulse coincides with the leading edge of a selection pulse subsequent to the next selection pulse because said leading edge then falls outside each active selection period T so that also capacitive crosstalk at selection electrodes which are located at a further distance is avoided.
  • a preferred embodiment thereof is shown in Fig. 7 in which the trailing edge of an arbitrary selection pulse (VJ coincides with the leading edge of the next selection pulse (V n+2 ) but one.
  • this pulse shape has the additional advantage that in each selection electrode (9 two of the unwanted edge currents (ID i and IC' n+1 ) coming from the two adjacent selection electrodes coincide and thus cancel each other out so that they do not flow via the PMOS transistor TC cum of the relevant electrode (9J.
  • the pulse shape as shown in Fig. 7 can be realised in a very simple manner by supplying two charge bits directly after each other instead of a single charge bit to the cascade of delay stages D n- j, D administrat, ... shown in Fig. 4A.
  • the delay times of the stages D n . ! , D n , ... then remain equal to the selection pulse repetition time.
  • the leading edge of the selection pulse V n . ⁇ at the selection electrode 9 ride. ⁇ starts.
  • the selection pulse V201 When the second charge bit appears at the output of the stage D ⁇ , the selection pulse V201., remains high and the leading edge of the pulse V n starts because the first charge bit appears simultaneously at the output of the stage D n .
  • V render When subsequently the second charge bit appears at the output of the stage D curat, V render remains high, the trailing edge of the pulse V n-1 starts because a discharge bit now appears at the output of the stage D n ., and the leading edge of the pulse V n+ , starts because the first charge bit now appears at the output of the stage D n+1 , and so forth. If the trailing edge of a selection pulse (for example V n-1 ) is to coincide with the leading edge of the next selection pulse (V n+2 ) but two, three charge bits will be consecutively passed through the cascade of delay stages, and so forth.
  • Fig. 8 shows a selection pulse shape by which a further reduction of the peak currents through the NMOS transistors TD, ⁇ , TD lake, ... is obtained.
  • the steepness of the trailing edge of the selection pulses is reduced with respect to the steepness of the leading edge. Consequently, the trailing edge covers a longer time and thus at least partially overlaps the active selection period of a subsequent selection pulse. As already described hereinbefore, this does not have any detrimental consequences because the electrons coming from the bottom have already been extracted from the transport ducts by a lower selection electrode.
  • the smaller edge steepness of the trailing edge can be realised in a simple and advantageous manner by rendering the saturation current of the NMOS transistors TD administrat. ! , TD n , ... smaller than that of the PMOS transistors. This may be preferably realised by rendering the NMOS transistors smaller than the PMOS transistors so that they occupy a smaller IC surface area.
  • the trailing edge of the selection pulse cannot of course be extended, but instead the leading edge can be extended so that the charge peak currents are reduced and hence smaller PMOS transistors are obtained.

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  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)

Abstract

Ce dispositif d'affichage d'image comprend plusieurs conduits de transport d'électrons, qui servent à transporter des électrons sous la forme de courants d'électrons, et des électrodes de sélection qui servent à extraire chaque courant d'électrons de son conduit de transport en des points prédéterminés et qui servent à diriger ce courant vers un écran luminescent. Les électrodes de sélection sont excitées par des impulsions de sélection, lesquelles se prolongent de façon à chevaucher au moins partiellement la période de sélection active de l'électrode de sélection adjacente disposée dans la direction des sources d'électrons.
PCT/IB1995/000246 1994-04-15 1995-04-07 Dispositif d'affichage d'image et attaqueur de selection et circuit d'attaqueur integre utilisables dans ledit dispositif d'affichage d'image WO1995028668A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP94201031 1994-04-15
EP94201031.5 1994-04-15

Publications (2)

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WO1995028668A2 true WO1995028668A2 (fr) 1995-10-26
WO1995028668A3 WO1995028668A3 (fr) 1995-11-23

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PCT/IB1995/000246 WO1995028668A2 (fr) 1994-04-15 1995-04-07 Dispositif d'affichage d'image et attaqueur de selection et circuit d'attaqueur integre utilisables dans ledit dispositif d'affichage d'image

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WO (1) WO1995028668A2 (fr)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0550104A2 (fr) * 1992-01-03 1993-07-07 Koninklijke Philips Electronics N.V. Dispositif de reproduction d'images muni d'une unité de reproduction de type à panneau plat

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WO1995028668A3 (fr) 1995-11-23

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