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WO1995011522A1 - Procede de fabrication de transistors a l'aide de dispositifs en silicium cristallin sur du verre - Google Patents

Procede de fabrication de transistors a l'aide de dispositifs en silicium cristallin sur du verre Download PDF

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Publication number
WO1995011522A1
WO1995011522A1 PCT/US1994/011641 US9411641W WO9511522A1 WO 1995011522 A1 WO1995011522 A1 WO 1995011522A1 US 9411641 W US9411641 W US 9411641W WO 9511522 A1 WO9511522 A1 WO 9511522A1
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Prior art keywords
layer
silicon
oxide
metal
doped
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PCT/US1994/011641
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English (en)
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Anthony M. Mccarthy
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The Regents Of The University Of California
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Publication of WO1995011522A1 publication Critical patent/WO1995011522A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/041—Manufacture or treatment of thin-film BJTs 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/311—Thin-film BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

Definitions

  • the present invention relates to fabricating single-crystal silicon devices, particularly to the fabrication of devices on an insulator substrate, and more particularly to a method for producing transistors in a silicon-on-glass substrate, wherein device components are formed on a silicon substrate, transferred to a glass substrate, and whereafter additional transistors may be formed.
  • Silicon-on-insulator (SOI) technologies have advanced dramatically in recent years towards the goal of producing thin single- crystal silicon films on insulated substrates.
  • Components such as metal- oxide-semiconductor (MOS) transistors, fabricated in SOI films have the potential for increased mobility, reduced parasitic capacitance and leakage current as well as improved radiation hardness due to reduced junction sidewall area and elimination of bottom junction area.
  • MOS metal- oxide-semiconductor
  • silicon-on-glass substrate processing Due to the high temperature processing requirements of silicon (greater than 800 C), silicon-on-glass substrate processing has not been possible except on the so-called "high- temperature” glass, such as Corning 1729 glass, capable of withstanding greater than 800°C temperatures. Other glasses used in commercial applications, such as lap-top displays, cannot withstand temperature exposures greater than 600°C, such as the Corning 7059 or other "low- temperature” glasses. Due to the high temperatures of silicon processing conventional silicon-on-glass techniques have relied on amorphous (a- Si) and polycrystalline (p-Si) materials which can be doped and treated at temperatures that the glass can withstand, but whose performance is decidedly inferior to single-crystal films.
  • a- Si amorphous
  • p-Si polycrystalline
  • the present invention satisfies this need by providing a process in which a low-temperature glass substrate may be used in a silicon-on-insulator device. Basically, this is accomplished by first forming the microelectronic device components on a silicon substrate and then transferring them to a glass substrate.
  • single- crystal silicon films can be utilized, instead of the previously used amorphous and polycrystalline silicon films, in SOI devices on glass.
  • a further object of the invention is to overcome problems associated with electrical damage to device components during anodic bonding of silicon to glass.
  • Another object of the invention is to provide a method for forming a gate-all-around device using the single-crystal silicon-on-glass technology.
  • Another object of the invention is to enable the use of less expensive, lower temperature glass substrates in the manufacture of components, such as transistors, nevertheless using conventional high temperature silicon processing.
  • Another object of the invention is to provide a technique for manufacturing single-crystal-silicon (SCS) metal-oxide- semiconductors (MOS) transistors and bipolar transistors on glass.
  • SCS single-crystal-silicon
  • MOS metal-oxide- semiconductors
  • Another object of the invention is to provide a process of fabricating single-crystal-silicon (SCS) devices on glass which require metal on at least one face of the device.
  • SCS single-crystal-silicon
  • this invention constitutes an improvement over the device fabrication method described and claimed in above-referenced U.S. Application Serial No. 08/137,411.
  • This invention both overcomes the electrical damage that may be caused to a device during the high voltage bonding of the silicon to the glass substrate, via the provision of a metal layer, which may be incorporated as part of the component.
  • Multilayers are formed on a silicon substrate which may include epitaxial layers of boron doped silicon, (or -lead or -tin) silicon-germanium alloy layers, and silicon, whereafter regions are implanted and thermally activated in the top or device-quality silicon layer.
  • An oxide layer is then thermally grown or deposited, followed by a layer of metal, such as aluminum, and an amorphous layer of silicon, silicon nitride, or silicon dioxide. Patterning of the oxide layer allows the metal layer to physically and electrically contact the silicon.
  • the multilayer structure is anodically bonded to a glass substrate, and due to the metal layer contacting the silicon, the current passes through areas which have not been employed to form device components, thus eliminating problems associated with electrical damage during the bonding operation.
  • the silicon substrate and the extra epitaxial layers are removed leaving the device quality top silicon layer with embedded components on the glass.
  • devices are functionally present on the glass and only a few steps such as device isolation, passivation, contact hole formation and an optional final metalization need to be performed. Further refinements of the circuitry on the glass may be performed, using the implanted and activated areas to form, for example, single gate or a gate- all-around device.
  • Figures 1 illustrates an example of multilayers deposited on a silicon substrate.
  • Figure 2 illustrates an example of deposited silicon substrate bonding of the multi-layer structures of Figure 1 to a glass substrate.
  • Figures 3 and 4 illustrate the process of removing the silicon substrate and the extra epitaxial layers following bonding to the glass substrate.
  • Figure 5 illustrates an embodiment of a single gate metal- oxide-semiconductor device formed on the glass substrate.
  • Figure 6 illustrates an embodiment of a gate-all-around metal-oxide-semiconductor device formed on the glass substrate.
  • Figures 7-10 illustrate the fabrication process of an alternative embodiment of a gate-all-around metal-oxide-semiconductor device formed on the glass substrate.
  • FIGS 11-12 illustrate an embodiment of a bipolar junction transistor made in accordance with the invention.
  • Figure 13 illustrates an embodiment using a trench arrangement to provide current bypassing during anodic bonding of the silicon to the glass substrate.
  • the invention is directed to the fabrication of components, such as transistors on glass using single-crystal silicon on glass.
  • the invention overcomes problems relating to transistor damage due to high voltages used in anodic bonding of the silicon to the glass. This is accomplished by use of a patterned oxide layer and a metal layer, whereby the current passes through areas not occupied by the transistor components.
  • the method of this invention is initially carried out as in the above-referenced copending application S.N. 08/(TL-9133), but with the addition of a patterned oxide layer, and a metal (aluminum or titanium) layer, and an outer dielectric layer prior to bonding to the glass substrate.
  • Figures 1-4 illustrate the forming of a silicon-on-glass device, with Figures 5 and 6 illustrating various components formed on the silicon on glass device of Figure 4.
  • the method for carrying out the invention is exemplified by the following operational sequence with reference to the drawings:
  • a silicon wafer 10 having a (100) orientation is used as the starting substrate.
  • a first etch stop layer 11 is formed on the silicon wafer 10.
  • Typical means of forming this layer are implantation, epitaxy or liquid source doping in a furnace at temperatures in excess of 750°C with a boron level exceeding about Iel9cm3.
  • the thickness of the layer is determined by the selectivity of the etching technique subsequently used to remove the silicon wafer, and may, for example, be 500 ⁇ m.
  • a liquid source doped boron layer about 3 microns thickness of which exceeded the required doping level, was used.
  • An alternative etch stop approach is to use a layer of SiGe:B (see W. P. Maszara, "Strain compensated Epitaxial Etchstop for BESOI", Proceedings of the 1992 IEEE International SOI Conference, p6).
  • An intermediate silicon layer 12 is epitaxially grown on the surface of layer 11.
  • the thickness of layer 12 was 1.5 microns.
  • a suitable thickness of layer 12 exceeds 0.5 microns.
  • the intermediate layer 12 was undoped.
  • a second etch stop layer 13 may be an epitaxially grown boron doped silicon layer or a silicon-germanium layer. If a boron doped layer 13 is used the thickness required will exceed about 500A and the doping density will exceed about 5el9/cm ⁇ . In the event a silicon- germanium (SiGe) epitaxial layer 13 is used, it should have a thickness of about 100-1500A. Doping may be used in the SiGe layer but is not necessary to achieve adequate etch stop properties. The SiGe layer may have between 1 and 50% Ge. An undoped thickness of about 500A is usually sufficient. In this example, 10-25% SiGe layers were used. Also, epitaxially grown silicon-lead or silicon-tin may be used in layer 13, and may be boron doped.
  • An epitaxial layer 14 of device quality silicon, thickness of 0.01-l ⁇ m, is epitaxially deposited on the etch stop layer 13 (see Figure
  • the silicon layer 14 is pattern-implanted with the desired dopant species to form the source/drain regions 15 and 16, and then activated at a temperature over 600°C (see Figure 1).
  • a low doping concentration in the range Iel4/cm3-5el6/cm3 layer is suitable for MOS devices.
  • the etch stop material (SiGe) will normally sustain short anneals in the temperature range of 600°C-800°C without adverse effects.
  • An oxide layer 17 having a thickness of 0.01-0.5 ⁇ m is formed by thermal oxidation or low-temperature deposition on the silicon layer 14.
  • the oxide layer 17 may be composed of silicon dioxide, for example.
  • This layer is patterned and etched to form contact holes for the subsequent metal deposition. This contact between the metal and the silicon outside the device areas permits current flowing during anodic bonding to flow around the devices without damage to the devices themselves.
  • An alternative arrangement is not to have any contacts between the metal and the silicon wafer but to undersize the glass substrate with respect to the silicon wafer so that electrical contact can be made to the metal layer during bonding.
  • Other metals, such as titanium, or conductive materials, such as polysilicon, may be used in layer 18.
  • a layer (or sequence of layers) 19 of amorphous material such as a-Si, a-SiN, a-SiON, or a-SiO, having a thickness of 0.01-1. O ⁇ m, for example, is deposited on the metal layer 18 by plasma enhanced chemical vapor deposition, as set forth in above-referenced copending application Serial No. 08/137,411.
  • a glass wafer or substrate 20 is selected and cleaned.
  • the silicon wafer 10 is bonded to the clean glass wafer or substrate 20, see Figure 2, by anodic bonding at a temperature of 300- 700°C and 0.5-5000 volts, using standard anodic bonding techniques.
  • the power supply is indicated at 21. Due to the oxide layer 17 and the metal layer 18, voltage and current flow around areas 15 and 16, thus eliminating possible damage thereto.
  • the silicon wafer substrate 10 is removed leaving the etch stop layer 11 exposed, as shown in Figure 3. This can be accomplished by polishing and/or wet/dry etching techniques. Polishing, using a diamond containing slurry, is used to grind down the silicon wafer 10 to a thickness of 100-200 ⁇ m followed by a wet or dry etch to complete removal of the silicon wafer. A wet etch of a 3:1 H2O/KOH was used at 80°C, although typical H2O/KOH compositions consist of 1:1- 5:1. The time period of wet etching in this example was 8 hours.
  • Isopropanol may be added to the H2O/KOH solution in excess of solubility and temperature may be reduced to provide a very sensitive etch stop.
  • ISO Isopropanol
  • a solution of 2:6:1 KOH:H2 ⁇ :ISO at 60°C may be used.
  • the etch rate of lightly doped silicon in this solution is about 250 ⁇ A/minute whereas the etch rate of heavily boron doped silicon and SiGe is about 3 ⁇ A/minute.
  • the etch stop layer 11 is removed by wet or dry etching, as shown in Figure 4.
  • the layer 11 is etched by plasma etching in a SF6/C2CIF5 environment using a power density of about 0.25 Watts /cm 2 for about 25 minutes.
  • the intermediate layer 12 is removed using the same selective etch of 3:1 KOH with Isoproponal added above liquid solubility as mentioned in paragraph 10.
  • the second etch stop 13 is SiGe is removed with a 5:1:1 H2 ⁇ :H2 ⁇ 2:NH ⁇ H as described in the above- referenced Godbey et al. patent, and if it is a boron doped silicon layer it is removed with plasma etching optionally followed by laser or by wet silicon etching using for example, 2:1 H2 ⁇ :NH4 ⁇ H.
  • Layer 14 is patterned and etched, to form a silicon island between components 15 and 16, shown in Figure 5.
  • Layers 18 and 19 are patterned and etched, to form light shield regions under the silicon islands as shown in Figure 5.
  • a low temperature oxide 22 layer is deposited over the exposed layers, with the layer 22 being composed of silicon dioxide, for example.
  • a metal layer generally indicated at 24, is deposited over this oxide layer 22 after the formation of contact holes 23 in layer 22 to the implanted and activated regions 15 and 16 using conventional microelectronic lithographic technology.
  • the metal layer 24 may be composed of aluminum or other conductive metal or materials.
  • Metal regions 24A and 24B are patterned from the metal layer 24, see Figure 5, forming the source (24A) and the drain (24B), respectively, of a conventional metal oxide semiconductor (MOSFET) transistor, with the metal layer 18 acting as the gate of this transistor.
  • MOSFET metal oxide semiconductor
  • a gate-all-around MOSFET may be formed from the single-gate MOSFET of Figure 5, as shown in Figure 6, by patterning the metal layer 24 to define metal regions 24A, 24B, and 24C, as shown in Figure 6, to form a second gate 24C thereby providing a gate-all-around embodiment.
  • Metal layers 18 and 24C act as gates, with region 24A acting as the source, and region 24B acting as the drain, of the Figure 6 gate-all- around transistor.
  • the active interfaces are those between layers 17 and 14 and layers 22 and 14 bounded by the source and drain.
  • An alternative embodiment of the single gate device has contacts to the source and drain made on the silicon wafer prior to bonding as shown in Figure 7 where patterned holes made in layer 17 include contacts 25 and 26 to the source and drain regions 15 and 16 on the top of the glass wafer.
  • Layer 17 may be either a thermal oxide or a low temperature oxide, composed of silicon dioxide, for example.
  • the source drain and gate metalizations must be patterned prior to bonding to allow access to the three terminal device.
  • Spaces 27 and 28 are formed in the patterned metal layer, indicated at 29, 30, and 31 as seen in Figure 7. The identical process development through Figures 3-6 is followed and is reproduced in Figures 7-10.
  • Figure 8 shows a single gate device where the active interface is again that between layers 17 and 14 bounded by the source 15 and drain 16 but in this case contacts 25 and 26 to the source and drain are made under the device as seen from the top in Figure 8.
  • Figure 9 shows the device contacted from both the top and the bottom with metal layers 24A and 24B from the top and layers 29, 30, and 31 via contacts 25 and 26 from the bottom.
  • Figure 10 shows a gate-all-around device implemented in this scheme with gates 24C and 30 and the drain and source contacted on both sides.
  • FIG. 11-12 An alternative embodiment of this technology is shown in Figures 11-12 where a bipolar transistor is bonded to glass.
  • the silicon wafer 41 is prepared with an initial etch stop layer 42 similar to those described in paragraph 2 above.
  • the subsequent layer deposition to achieve a bipolar configuration is variable but one example is shown here.
  • Layer 43, called the buried collector is a layer of conductivity type 1, usually doped in the range Iel9-le21/cm3. Examples of conductivity types are p-type silicon achieved by doping silicon with boron or other Column V elements, and n-type silicon achieved by doping silicon with phosphorus or other Column HI elements.
  • Layer 44 called the intrinsic collector has the same conductivity type 1 as layer 43 and its doping range lies approximately in the range Iel5-lel7/cm3.
  • Layer 45 called the base, has conductivity type 2 and its doping range lies approximately in the range 5el7-5el8/cm3.
  • Layer 46 called the emitter, has conductivity type 1 and its doping range lies approximately in the range 5el8-le21/cm3. Electrical contact to the base 45 is established by a high dose implant of conductivity type 2 shown as 55.
  • Layer 47 is a deposited or thermally grown oxide. Electrical contact to the emitter 46 is established by an opening or contact hole 48 in oxide layer 47 through which a contact 52 of a metal layer 51 deposited over oxide layer 47 extends.
  • Electrode to the base 45 is established by opening or contact hole 48' in oxide layer 47 through which a contact 52' of a metal layer 49 extends.
  • Metal layers 51 and 49 are separated by a gap or opening 50 so as to separate the base metal 49 from the emitter metal 51.
  • a dielectric layer 53, of amorphous nitride is deposited over the metal layers 49 and 51 and gap or opening 50.
  • the silicon wafer 41 with the attached layers 42-53 is bonded to a glass substrate 60 via layer 53.
  • the metal layers 49 and 51 may be contacted from the front of the wafer by undersizing the glass 60.
  • a third contact hole type may be opened at specific locations as shown in Figure 13 where a trench 59 may be patterned, creating opening 58, and plasma etched followed by metal deposition to provide contact from the metal layer 51 to the substrate allowing the bypassing of current during anodic bonding.
  • the silicon wafer is removed according to the etching schedule described in paragraph 10.
  • the substrate with the remaining thin film of silicon is patterned and etched to remove unwanted areas of silicon and to isolate the transistors.
  • the etching may be performed as in paragraphs 11.
  • a low temperature oxide layer 54 is deposited over the exposed layers (see Figure 12).
  • a contact opening 57 may be made on the silicon island in this oxide layer to allow contact with the extrinsic P+/N+ collector from a deposited metal 56, such as aluminum or aluminum/1% Si. Openings in the oxide layer 54 may also be made to permit contact to the two other electrodes, the base 49 and the emitter 51.
  • the present invention provides a method for forming microelectronic devices, such as single and gate- all-around transistors, on a silicon-on-glass substrate, thus advancing the state of this art. Also, the method provides for anodic bonding of a layer of silicon to a glass substrate without adverse effects on the implanted and activated regions formed in the silicon layer.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Procédé de fabrication de transistors faisant appel à des dispositifs en silicium monocristallin sur verre. Ce procédé permet d'éviter les dommages éventuels qui pourraient être causés au dispositif lors de la liaison sous haute tension (21) et fait appel à une couche de métal (18) pouvant être incorporée pour faire partie intégrante du transistor. Selon l'invention, lors de la liaison de la pastille ou du substrat de silicium sur le substrat de verre (20), la tension et le courant traversent des zones où aucun transistor ne sera fabriqué. Après retrait du substrat de silicium, il est possible de déposer à nouveau du métal, de manière à former des contacts électriques ou à ajouter une fonctionnalité aux dispositifs. Ce procédé permet de réaliser aussi bien des dispositifs à grille simple que des dispositifs à grille périphérique.
PCT/US1994/011641 1993-10-18 1994-10-14 Procede de fabrication de transistors a l'aide de dispositifs en silicium cristallin sur du verre WO1995011522A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/137,402 1993-10-18
US08/137,402 US5414276A (en) 1993-10-18 1993-10-18 Transistors using crystalline silicon devices on glass

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WO1995011522A1 true WO1995011522A1 (fr) 1995-04-27

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