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WO1995008188A1 - Puces a bosses dans des boitiers electroniques metalliques - Google Patents

Puces a bosses dans des boitiers electroniques metalliques Download PDF

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Publication number
WO1995008188A1
WO1995008188A1 PCT/US1994/009612 US9409612W WO9508188A1 WO 1995008188 A1 WO1995008188 A1 WO 1995008188A1 US 9409612 W US9409612 W US 9409612W WO 9508188 A1 WO9508188 A1 WO 9508188A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic package
metallic base
integrated circuit
base component
substrate
Prior art date
Application number
PCT/US1994/009612
Other languages
English (en)
Inventor
Jeffrey S. Braden
Deepak Mahulikar
Original Assignee
Olin Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olin Corporation filed Critical Olin Corporation
Priority to AU76044/94A priority Critical patent/AU7604494A/en
Priority to JP7509197A priority patent/JPH09502837A/ja
Priority to KR1019960701241A priority patent/KR960705359A/ko
Priority to EP94926028A priority patent/EP0719453A4/fr
Publication of WO1995008188A1 publication Critical patent/WO1995008188A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/22—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device liquid at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Definitions

  • the invention is subject to a wide range of applications, it is particularly suited for metal packages to house an electronic device. More particularly, the invention relates to a metal electronic package in which one or more integrated circuit devices are flip chip bonded to a supporting substrate.
  • Adhesively sealed metal packages for housing electronic devices are disclosed in U.S. Patent Nos. 4,105,861 to Hascoe; 4,461,924 to Butt and 4,939,316 to Mahulikar et al.
  • the packages have a metallic base and cover.
  • a leadframe is disposed between the base and cover and adhesively bonded to both.
  • the leadframe may include a centrally positioned die attach paddle with the integrated circuit device bonded thereto. Bond wires electrically interconnect the device to the leadframe.
  • QFP's quad flat packs
  • CERDIP's ceramic dual in line packages
  • Metal packages remove heat generated during operation of the device more efficiently than plastic or ceramic packages.
  • the improved thermal dissipation is due to both improved thermal conduction of the metallic components and the ability of the components to disperse heat laterally along all surfaces of the package.
  • the improved thermal dissipation permits encapsulation of more complex and higher powered integrated circuit devices than is possible with plastic or ceramic packages.
  • Improved thermal dissipation also facilitates the encapsulation of a plurality of integrated circuit devices within a single package. As the integrated circuit devices become more complex, more electrical interconnections with external circuitry are required.
  • the leadframe which electrically interconnects the device to external circuitry, is usually manufactured from a copper base alloy having a thickness of from about 0.13 mm to about 0.51 mm (5-20 mils).
  • the minimum width of each lead, as well as the spacing between leads, is about equal to the thickness of the leadframe.
  • the number of leads which may approach the integrated circuit device.
  • One way to increase the number of leads is to increase the distance between the leadframe and the integrated circuit device.
  • the distance over which effective wire bonds are made is limited to about 5.1 mm (200 mils).
  • One method which has been used to electrically interconnect integrated circuit device with a leadframe which does not require the use of thin bond wires is known as controlled collapse chip connection (C4) or flip chip bonding.
  • flip chip bonding As generally described in Section 6.3 of Microelectrocic Packaging Handbook edited by Tummala et al, input/output pads on the electrically active face of a semiconductor device are directly soldered to metallized pads on a substrate. Electrically conductive circuit traces interconnect the input/output pads with terminal pins to electrically interconnect the semiconductor device to external circuitry. While flip chip bonding has been applied to ceramic and plastic pin grid array packages, it has not been applied to metal electronic packages. Accordingly, it is an object of the invention to provide a metal electronic package having one or more flip chip bonded semiconductor integrated circuits housed therein. It is a feature of the invention that the integrated circuit devices are supported on and electrically interconnected to a substrate by a first array of bond pads.
  • the inner leads of a leadframe are electrically interconnected to a second array of bond pads on the same substrate.
  • the substrate may be formed from any rigid material having a coefficient of thermal expansion approximately equal to that of the semiconductor device.
  • an electronic package has a metallic base component and a cover component.
  • the metallic base component and the cover component define a cavity.
  • a leadframe which has inner and outer lead ends is disposed between the metallic base component and the cover component and bonded to both. The inner lead ends are positioned within the cavity.
  • a substrate is disposed within the cavity. This substrate contains a first metallization array and a second metallization array. The first metallization array aligns with the input/output pad configuration of a desired integrated circuit device.
  • the second metallization array is electrically interconnected to the leadframe.
  • Figure 1 shows in cross-sectional representation a metallic electronic package having a flip chip bonded integrated circuit in accordance with the invention.
  • Figure 2 shows in top planar view, a substrate for the flip chip bonding of an integrated circuit device in accordance with the present invention.
  • Figure 3 shows in cross-sectional representation, a first embodiment of the substrate of Figure 2.
  • Figure 4 shows in cross-sectional representation, a second embodiment of the substrate of Figure 2.
  • Figures 5-7 show in cross-sectional representation a method for the assembly of the electronic package of the invention.
  • Figure 8 shows in cross-sectional representation the metal electronic package of the invention incorporating a heat spreader.
  • Figure 9 shows in cross-sectional representation a ball grid array electronic package in accordance with the invention.
  • Figure 10 shows in cross-sectional representation a housing for encapsulating an integrated circuit device flip chip bonded to a printed circuit board.
  • Figure 1 shows in cross-sectional representation an electronic package 10 for encapsulating one or more integrated circuit devices 12 in accordance with the present invention.
  • the electronic package 10 has a metallic base component 14 and a cover component 16.
  • the metallic base component 14 and the cover component 16 define a cavity 18. While the spatial orientation of the metallic base component 14 and cover component 16 depends whether the electronic package 10 is a cavity up or a cavity down configuration, throughout this application the "base component" is that component adjacent the back side 19 of the integrated circuit device 12.
  • the metallic base component 14 may be formed from any suitable metal, metal alloy or metal compound. To maximize thermal conductivity, the metallic base component 14 is preferably formed from copper, aluminum or alloys thereof. In a most preferred embodiment, the metallic base component 14 is formed from an aluminum alloy and anodized prior to package assembly. Anodization provides corrosion resistance and also electrically insulates the metallic base component. To achieve a uniform gray to black color, useful for infrared soldering, the metallic base component 14 is an aluminum alloy containing manganese and silicon. Preferred aluminum alloys are designated by the ASM (American Society for Metals) as 3xxx and 6xxx series. Alloys of the 3xxx series contain up to about 1.5% by weight manganese along with other alloying elements.
  • ASM American Society for Metals
  • Alloys of the 6xxx series contain magnesium and silicon in an approximate proportion to form Mg 2 Si.
  • One preferred aluminum alloy is aluminum alloy 3003 which has the nominal composition of about 0.12% by weight copper, about 1.2% by weight manganese and the balance aluminum.
  • the light black to black color is achieved by integral color anodization.
  • the metallic base component 14 is immersed in any suitable electrolyte such as a mixture of sulfuric and sulfosalicylic acids in a concentration range of from about 1 to 4 gm/1 H 2 S0 4 and from about 50 to about 120 gm/1 C ⁇ OgS.
  • the cover component 16 is formed from any suitable material. To prevent distortion of the electronic package 10 due to coefficient of thermal expansion mismatch, the cover component 16 preferably has a coefficient of thermal expansion approximately equal to that of the metallic base component 14. Any suitable polymer, ceramic or metal may be utilized. A ceramic cover component 16 has the advantage of rigidity and light weight. A metal cover component 16 has the advantage of ease • of formability and with aluminum based materials, light weight as well. Preferably, the cover component 16 is formed from the same metal, metal alloy or metal compound as the metallic base component 14, such as an anodized aluminum alloy. A leadframe 20 having inner lead ends 22 and outer lead ends 24 is disposed between the metallic base component 14 and the cover component 16 and bonded to both.
  • the bond 26 may be any suitable dielectric material such as a low temperature sealing glass or a polymer adhesive.
  • the bond 26 is a polymer adhesive such as a ther osetting epoxy resin.
  • Leadframe 20 is positioned such that the inner lead ends 22 are within the cavity 18.
  • a substrate 28 is disposed within the cavity 18.
  • the substrate 28 contains a first metallization array 30 and a second metallization array 32.
  • the first metallization array 30 aligns with the input/output pad configuration on the electrically active face 34 of the integrated circuit device 12.
  • the second metallization array 32 is electrically interconnected to the inner leads 22 of the leadframe 20.
  • Vent hole 36 which can be formed either in the metallic base component 14 or, as illustrated in Figure 1, in the cover component 16, facilitates the removal of polymer cure reaction by-products from the package cavity 18 during assembly.
  • the vent hole 36 is subsequently sealed with either a metal plug or a polymer.
  • the substrate 28 is illustrated in top planar view in Figure 2.
  • the substrate 28 contains a support layer 38 which is preferably rigid or semi-rigid to maintain the integrity of the bonds to the integrated circuit.
  • the support layer 38 may be formed from any suitable metal, ceramic, metal alloy, metal compound or composite.
  • the support layer 38 preferably has a coefficient of thermal expansion approximately equal to that of the integrated circuit device 12 to prevent stress on the bond between an integrated circuit and the substrate during assembly or operation. Generally, the coefficient of thermal expansion of the support layer 38 is within about 10% of the coefficient of thermal expansion of the integrated circuit device.
  • Formed on a surface of the support layer 38 is a first metallic array 30 and a second metallic array 32 of any electrically conductive material which may be accurately patterned.
  • Patterning may be by screen printing, photolithography, direct writing or any other means known in the art.
  • Typical materials for the first metallization array 30 and second metallization array 32 are copper, tungsten, palladium/nickel alloys and chromium/copper/chromium laminar structures.
  • Conductive polymers such as a silver filled epoxy can also be used.
  • the first metallization array 30 is configured to align with the pattern of input/output pads formed on the electrically active face of an integrated circuit device.
  • the second metallization array 32 is configured to align with the inner lead ends of a leadframe. Electrically conductive circuit traces 40 interconnect the first metallization array 30 and the second metallization array 32.
  • Figure 3 illustrates in cross-sectional representation a substrate 28 in accordance with an embodiment of the invention.
  • the support layer 38 is formed from a rigid or semi-rigid material having a coefficient of thermal expansion about equal to that of an integrated circuit device.
  • the support layer 38 may be electrically conductive or electrically nonconductive.
  • Typical materials include iron alloys, iron-nickel alloys and iron-nickel-cobalt alloys, as well as ceramic materials such as alumina, aluminum nitride and boron nitride.
  • the thickness is that effective to maintain a rigid to semi-rigid backing layer, typically on the order of from about 0.13mm to about 0.38mm (0.005-0.015 inch).
  • An adhesive layer 42 bonds the support layer 38 to a circuit structure 44.
  • the circuit structure 44 may be a copper foil layer laminated directly to adhesive 42 or, as illustrated in Figure 3, a composite circuit layer. Particularly suitable is a composite flexible circuit.
  • the composite flexible circuit includes a dielectric substrate 46, such as polyimide, laminated to a conductive layer, typically copper or a copper alloy.
  • the conductive layer is patterned, typically by photolithography, to a desired circuit pattern 30, 32, 40.
  • multiple circuit layers 44 may be laminated one to the other to form a multilayer structure supported by support layer 38.
  • FIG. 4 illustrates in cross-sectional representation, a substrate 28' in accordance with a second embodiment of the invention.
  • the support layer 38 is formed from an electrically insulating material such as alumina, aluminum nitride or boron nitride.
  • a desired circuit pattern 30, 32, 40 is formed on the support layer 38.
  • the circuit pattern can be formed by thick film technology such as screen printing or direct writing; by thin film technology such as sputtering or vapor deposition followed by selective etching; or by tape automated bonding (TAB) technology such as the selective etching of a laminated copper layer.
  • the circuit pattern 30, 32 and 40 is deposited as a palladium/nickel alloy paste which is converted to a metallic layer by heating to an elevated temperature in a reducing atmosphere.
  • the metallization layer is then built to a desired thickness by the deposition of an overlying copper layer by electroless or electrolytic means.
  • the substrate 28 is bonded to a leadframe 20 electrically interconnecting the inner lead ends 22 with the second metallization array 32.
  • the interconnection 48 may be by any suitable material such as solder, conductive epoxy or a weld. Typical solders include lead-tin and silver-tin alloys, as well as low melting temperature gold alloys such as gold-tin. More preferred, are electrically conductive polymer adhesives such as silver filled thermosetting epoxy.
  • the integrated circuit device 12 has a back side 19 which is usually devoid of any electrically active components and is generally a flat plane of silicon dioxide or gold metallized silicon or silicon dioxide.
  • the opposing face 34 of the integrated circuit device 12 contains electrically active features as known from conventional integrated circuit technology. Among these electrically active features are an array 50 of input/output pads arranged in a specific configuration.
  • the first metallization array 30 of the substrate 28 is configured to align with the configuration of the input/output pads 50.
  • Other electronic features 52 may include transistors, resistors, and storage regions.
  • An interconnect 54 bonds the integrated circuit device 12 to the substrate 28.
  • the interconnect 54 electrically interconnects the input/output pads 50 with the first metallization array 30.
  • the interconnect 54 is any suitable electrically conductive material including low melting temperature solders such as tin-lead, tin-silver, gold-tin or gold-silicon alloys.
  • an electrically conductive adhesive such as a silver filled thermosetting epoxy may be used.
  • the assembly 56 is then assembled into an electronic package housing as illustrated in Figure 7.
  • the assembly 56 is supported by a fixture having a fixture base 58 and a fixture cover 60.
  • the fixture base 58 and fixture cover 60 may be formed from any suitable material which can withstand the assembly temperature of approximately 250°C. Preferred materials include stainless steel and aluminum.
  • Supported on the fixture base 58 is the metallic base component 14.
  • a bond material 26 either stamped as a preform in a window frame shape from a thin sheet of adhesive or deposited in a window frame shape by screen printing or direct writing in the form of an adhesive or sealing glass is deposited on the periphery of the metallic base component 14.
  • a thermally conductive chip attach material 62 is deposited on a central region of the metallic base component 14.
  • the thermally conductive chip attach material 62 may be any suitable material such as a silver filled thermosetting epoxy.
  • the assembly 56 is then deposited onto the base component 14 with a central portion of the leadframe 20 contacting the bond 26 and the back side 19 of the integrated circuit device 12 contacting the thermally conductive chip attach material 62.
  • the cover component 16 is aligned on the opposing side of the leadframe 20 with a bond material 26 disposed therebetween.
  • the fixture cover 60 is then positioned on the fixture base 58 and provides a desired amount of pressure on bond 26 and thermally conductive chip attach material 62. When heated, an integral bond is formed between the metallic base component 14 and both the leadframe 20 and back side 19 of the integrated circuit device 12. The vent hole 36 is then sealed, completing assembly of the electronic package.
  • FIG 8 shows in cross-sectional representation an embodiment in which a heat spreader 64 is disposed between the back side 19 of the integrated circuit device 12 and the metallic base component 14.
  • the heat spreader 64 is any thermally conductive material such as copper, aluminum or alloys thereof. Anodized aluminum is particularly suited for multichip applications when it is desirable to electrically isolate the individual integrated circuit devices.
  • the heat spreader 64 laterally diffuses heat away from the integrated circuit device 12.
  • the heat spreader 64 has a cross-sectional area larger than the integrated circuit device 12 to both better dissipate heat and to disperse the thermally conductive chip attach material 62 into a thinner, less thermally resistant, layer and also prevents the chip attach material from running up the sides of the integrated circuit device. While the invention has been described in terms of a leaded electronic package having a single encapsulated integrated circuit device, the invention is equally applicable to leaded packages having a plurality of encapsulated integrated circuit devices, as well as leadless electronic packages.
  • FIG. 9 shows in cross-sectional representation one such leadless electronic package.
  • the ball grid array package 70 has a metallic base component 14 sealed to a cover component 16.
  • the cover component is either electrically nonconductive or, if electrically conductive, coated with a nonconductive layer.
  • Suitable cover materials include ceramics such as alumina or aluminum nitride as well as polymers.
  • One suitable electrically conductive cover is an aluminum alloy coated with an anodization layer.
  • a first metallization array 30 is formed on an electrically nonconductive surface of the cover component 16.
  • An interconnection 54 electrically interconnects the first metallization array 30 to the electrically active face 34 of an integrated circuit device 12.
  • a second metallization array 72 is formed on an opposing electrically nonconductive surface of the cover component 16.
  • Conductive vias 74 electrically interconnect the first 30 and second 72 metallization arrays.
  • the second metallization array 72 is electrically interconnected to a third metallization array 78 formed on the substrate 80 of a printed circuit board or other circuit assembly.
  • An interconnect 82 such as a low melting temperature solder or conductive adhesive provides the electrical interconnection.
  • FIG 10 illustrates in cross-sectional representation an electronic package 90 in which the integrated circuit device 12 is directly bonded to the substrate 80 of a printed circuit board.
  • This package is an improvement over conventional flip chip bonded integrated circuits which are coated with silicone glob top.
  • the package 90 has a metallic base component 14 bonded to the back side of the integrated circuit device 12 to conduct heat from the device.
  • the metallic base component 14 is manufactured from a metal such as copper, aluminum, or alloys thereof or a metal compound or metal composite.
  • the thermally conductive chip attach material 62 and the bond material 26 may be any suitable material such as a thermally or ultra violet curable adhesive.
  • a first metallization array 30 is formed on the substrate 80 an electrically interconnects to the integrated circuit device 12 by interconnects 54.
  • Circuit traces 92 such as patterned copper foil laminated to the substrate 80 electrically interconnect the integrated circuit device to external circuitry 94.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un boîtier électronique (10) permettant d'encapsuler un dispositif (12) à circuit intégré soudé par des puces à bosses. Une base métallique (14) et un couvercle (16) définissent une cavité (18) où est disposé un substrat (28) qui présente deux réseaux (30, 32) de métallisation. Les plots (50) d'entrée/sortie du dispositif (12) à circuit intégré sont soudées au premier réseau (30) de métallisation et les conducteurs (22) internes d'un cadre de montage (20) sont soudés au deuxième réseau (32) de métallisation. Quand on soude (26) la base métallique (14) et le couvercle (16) en intercalant entre eux un cadre de montage (20), le substrat (28), les conducteurs (22) internes et le dispositif (12) à circuit intégré sont encapsulés dans la cavité (18).
PCT/US1994/009612 1993-09-13 1994-08-29 Puces a bosses dans des boitiers electroniques metalliques WO1995008188A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU76044/94A AU7604494A (en) 1993-09-13 1994-08-29 Flip chip in metal electronic packages
JP7509197A JPH09502837A (ja) 1993-09-13 1994-08-29 金属製電子パッケージに入れたフリップチップ
KR1019960701241A KR960705359A (ko) 1993-09-13 1994-08-29 금속 전자 패키지에서의 플립칩(Flip chip in metal electronic packages)
EP94926028A EP0719453A4 (fr) 1993-09-13 1994-08-29 Puces a bosses dans des boitiers electroniques metalliques

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12060993A 1993-09-13 1993-09-13
US120,609 1993-09-13

Publications (1)

Publication Number Publication Date
WO1995008188A1 true WO1995008188A1 (fr) 1995-03-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1994/009612 WO1995008188A1 (fr) 1993-09-13 1994-08-29 Puces a bosses dans des boitiers electroniques metalliques

Country Status (5)

Country Link
EP (1) EP0719453A4 (fr)
JP (1) JPH09502837A (fr)
KR (1) KR960705359A (fr)
AU (1) AU7604494A (fr)
WO (1) WO1995008188A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7592694B2 (en) 2006-12-18 2009-09-22 Chipmos Technologies Inc. Chip package and method of manufacturing the same

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US4939316A (en) * 1988-10-05 1990-07-03 Olin Corporation Aluminum alloy semiconductor packages
US5311402A (en) * 1992-02-14 1994-05-10 Nec Corporation Semiconductor device package having locating mechanism for properly positioning semiconductor device within package

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Also Published As

Publication number Publication date
JPH09502837A (ja) 1997-03-18
AU7604494A (en) 1995-04-03
EP0719453A4 (fr) 1998-08-19
EP0719453A1 (fr) 1996-07-03
KR960705359A (ko) 1996-10-09

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