+

WO1993023810A1 - Coprocesseur modulable - Google Patents

Coprocesseur modulable Download PDF

Info

Publication number
WO1993023810A1
WO1993023810A1 PCT/JP1993/000617 JP9300617W WO9323810A1 WO 1993023810 A1 WO1993023810 A1 WO 1993023810A1 JP 9300617 W JP9300617 W JP 9300617W WO 9323810 A1 WO9323810 A1 WO 9323810A1
Authority
WO
WIPO (PCT)
Prior art keywords
coprocessor
computer system
coupled
actual
bus
Prior art date
Application number
PCT/JP1993/000617
Other languages
English (en)
Inventor
Sameer Kanagala
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to JP5520052A priority Critical patent/JPH06509896A/ja
Publication of WO1993023810A1 publication Critical patent/WO1993023810A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA

Definitions

  • This invention pertains to the field of computing systems, and in particular to techniques for improving the communications between central processing units and system resources such as input/output controllers and memory.
  • Figure 1 illustrates the conventional method by which central processing units (CPUs) communicate with system resources 2.
  • the computer system comprises a set of m system resources 2, which can include memory and input/output controllers that are in turn coupled to input/output devices.
  • the system comprises at least one CPU 1 for performing computational tasks, running stored programs, and communicating with system resources 2.
  • Figure 1 illustrates a set of n CPUs If all of which are coupled to each other via a system bus 4, typically comprising a set of parallel data lines and a set of parallel address lines.
  • System bus 4 for example, might have 32 parallel data lines and 32 parallel address lines. Using binary arithmetic, this is enough to address 4 Gigabytes of data at random.
  • a bus master 34 is coupled to bus 4 and regulates access thereto.
  • a DMA controller 3 is associated with each system resource 2. All of the DMA controllers 3 are coupled to system
  • Bus arbiter 5 is a set of logic that is duplicated on all of the other DMA controllers 3. Bus arbiter 5 5 stores priority information associated with that system resource 2 and indicates to bus master 34 that one of the CPUs 1 wishes to activate the associated system resource 2. Bus master 34 then determines which of the DMA controllers 3 will be given authorization to become operational. Only one DMA
  • ⁇ JO controller 3 can be operational at any one time.
  • the way that a CPU 1 communicates with a system resource 2 is for CPU 1 to place, typically, three pieces of information into the associated DMA controller 3 : the source address (the address where the data that are the subject of the
  • source address pointer 6 15 communication are to be found
  • address pointer 7 the address of the destination (location where the data are to be sent) is stored in address pointer 7; and the number of bytes desired to be moved is stored in byte counter 8.
  • byte counter 8 decrements
  • CPU 1 wishes to perform operations such as arithmetic, logic, or shift operations on the data in addition to simply moving them, this
  • the present invention is a computer system comprising at least one central processing unit (CPU) (1) capable of performing operations on data stored within a set of system resources (2) .
  • a scalable coprocessor (9) is coupled to the CPUs (1) and the system resources (2) via a system bus (4) .
  • Within the scalable coprocessor (9) and coupled to the CPUs (1) is a single register file (10) that is compartmentalized into at least two bins, each bin corresponding to a virtual coprocessor channel.
  • Coupled to the register file (10) is a single actual coprocessor (6, 7, 8, 13, 33) for performing operations on the system resources (2) .
  • Coupled to the register file (10) is a means (11) for apportioning the operational cycles of the actual coprocessor among the set of virtual coprocessor channels.
  • the number of virtual channels can be increased (scaled) without the need to increase the number of actual channel hardware elements (such as items 5, 6, 7 and 8 of the prior art) , since there is but one scalable coprocessor (9) -
  • FIG. 1 is a block diagram of the conventional prior art technique of communicating among CPUs 1 and system resources 2;
  • FIG. 2 is a block diagram of scalable coprocessor 9 of the present invention.
  • FIG. 3 is a block diagram of state machines 11 of scalable coprocessor 9 of the present invention.
  • Figure 4 is a sketch of amplitude versus time for gas pedal signal 15 of the present invention
  • Figure 5 is a block diagram of a fly-by DMA controller
  • FIG. 6 is a block diagram of a RAID coprocessor 29 embodiment of the present invention.
  • FIG 2 is a block diagram of a general embodiment of scalable coprocessor 9 of the present invention.
  • the environment is a computer system which comprises at least one central processing unit (CPU) 1.
  • CPU central processing unit
  • Each CPU 1 can be any active processing element capable of performing an operation on a set of system resources 2.
  • n CPUs 1 are illustrated in Figure 2.
  • CPUs 1 are all coupled together via the same system bus 4.
  • system bus 4 may have 32 parallel data lines and 32 parallel address lines. This is enough to address four Gigabytes of data at random.
  • each CPU 1 can submit multiple I/O requests simultaneously.
  • a CPU 1 can be a file server that asks for hundreds of files simultaneously.
  • System resources 2 are likewise coupled together via the same system bus 4. Only one operation can be performed on system bus 4 at any given time.
  • System resources 2 comprise, typically, memory and input/output controllers that are in turn
  • inpu /output devices such as disk drives, tape drives, CD ROMs, Bernoulli boxes, etc.
  • Coprocessor 9 communicates with system resources 2 at speeds approaching memory bandwidth, e.g., 66 MBps in embodiments that have been built, rather than at slower CPU 1 bandwidths.
  • Scalable coprocessor 9 is coupled to CPUs 1 via system bus 4 and comprises register file 10 , a set of state machines 11, and an actual coprocessor comprising at least one address pointer (e.g., source address pointer 6 and destination address pointer 7) , byte counter 8, buffer 13, and (optionally) logic unit 33.
  • Pointers 6 and 7 are storage devices such as registers or programmable counters.
  • Register file 10 is a storage device such as a random access memory (RAM) that has been preselectedly compartmentalized into an arbitrary number of p+1 storage areas or bins corresponding to the number of virtual coprocessor channels that the user of coprocessor 9 has decided to set up in advance.
  • p+1 may correspond to the number of blocks of data that are known to be present in the computer system.
  • Each bin or channel stores at least three pieces of information: the beginning address of the data that are to be used as the source for an operation, the beginning address of the desired destination for the data after the operation has been performed, and the size of the data that are the subject
  • information can be stored in the channel indicating the type of arithmetic, logic, or shift operation desired to be performed on the data.
  • the set of state machines 11 determines which channels are allowed to become operational in which order and for how long, based upon a programmable arbitration scheme stored within state machines 11.
  • a given channel is allowed to become operational, the stored source address from that channel is placed into source address pointer 6 via pointer bus 12, the destination address is placed into destination address pointer 7 via pointer bus 12, and the byte count is placed into byte counter 8 via pointer bus 12.
  • the stored arithmetic, logic, or shift instructions, if any, are placed into optional logic unit 33 over pointer bus 12.
  • coprocessor 9 is clocked through its normal operational cycles by a conventional clock (not shown), e.g., at the rate of 66 Megahertz, the desired operations are performed.
  • the source data are addressed by means of source address pointer 6 placing the source address over system bus 4.
  • the destination address is similarly accessed by pointer 7, again using system bus 4. If it is desired to perform an arithmetic, logic, or shift operation on the data and not just simply move them, logic unit 33 is invoked. Finally, byte counter 8 is decremented once per cycle.
  • state machines 11 allow each channel to perform a finite number of operations (corresponding to a given finite number of clock cycles) per operational authorization. 128 cycles is a typical number. This may or may not be enough
  • buffer 13 is needed because one of the CPUs . 1 may be trying to initialize another channel within register file 10 at the same time that the updated information is being sent back to register file 10 over update bus 14. Thus, buffer 13 prevents collisions of inbound and outbound in ormation.
  • FIG. 3 illustrates in more detail the set of state machines 11.
  • the first state machine is a programmable arbiter 20, which may comprise random access memory plus associated logic devices.
  • Arbiter 20 stores the programmable scheme for arbitrating which channels are given operational access and for how long.
  • the programming scheme may entail the use of gate arrays, EEPROMs, fuses/anti-fuses, etc.
  • the arbitration scheme may be any one of a number of techniques such as round robin (cycling through the channels in order and then repeating at the zeroeth channel) , priority (giving authorization only to channels which are flagged with certain priority bytes or giving flagged channels a greater number of operational cycles than channels not flagged) , etc.
  • a set of channel lines CH is input into programmable arbiter 20. These lines can originate from register file 10
  • arbiter 20 is a line conveying the number of the channel which is being granted operational access at any given time. This signal is fed to channel initialize and update module 21.
  • One of the outputs of module 21 is a register file address index, which informs register file 10 which channel is being given operational authorization. The length of this index is variable, depending upon the number of channels. For example, if there are eight channels, this index requires three bits.
  • the other output of module 21 is a channel ready signal.
  • This signal is fed to gas pedal module 22.
  • the composite output of gas pedal 22 is a square wave 15, whose amplitude versus time is illustrated in Figure 4.
  • gas pedal signal 15 When gas pedal signal 15 is high, this indicates the presence of a throttle (operational) period 18, i.e., one in which operations on the data are being performed by actual coprocessor 6, 7, 8, 33.
  • gas pedal signal 15 is low, this indicates the presence of an idle period 19 during which no virtual channel is allowed to be operational, but rather CPUs 1 rather than coprocessor 9 are given access to system bus 4.
  • the durations of the throttle and idle periods 18, 19 are variable and programmable in advance.
  • FIG. 5 illustrates a specific embodiment of the present invention: a fly-by DMA controller 23.
  • This embodiment of scalable coprocessor 9 is used in conjunction with non-addressable devices such as input/output controllers 25. Since these devices are non-addressable, one. of the pointers 6 r 7 r from the general embodiment can be eliminated.
  • a single input/output address pointer 24 is used to indicate where in memory 26 data to be read from or written to I/O controller 25 are stored. Pointer 24 points to the beginning location in memory 26 where the data are to be read from or written to.
  • a separate request line 28 and acknowledge line 27 connects pointer 24 with each I/O controller 25.
  • a signal is sent by I/O controller 25 over request line 28 to address pointer 24, asking DMA controller 23 to start each byte transfer. Similarly, a signal is sent from pointer 24 over acknowledge line 27 to I/O controller 25 for each byte that is transferred, signaling that system bus 4 is available to perform the read or write operation.
  • Byte counter 8 decrements
  • FIG. 6 A second embodiment of the present invention is illustrated in Figure 6: a RAID (redundant array of inexpensive disks) coprocessor 29.
  • a RAID (redundant array of inexpensive disks) coprocessor 29 there are m-1 equally sized blocks of memory 26, where m-1 is at least 2.
  • the output is a set of m equally sized blocks of data that are written to a set of disk controllers 2.
  • the mth. block is a byte-by-byte parity check on the first m-1 blocks. This permits fault tolerant processing: if any one block fails, including the parity block, all of the data can be reconstructed from the remaining blocks.
  • register file 10 contains but a single destination pointer, because the writing onto the m disk controllers 2 is automatically partitioned equally among the m controllers 2.
  • Exclusive OR (XOR) pipeline 30 is a special case of logic unit 33. Every time a source block of data is read in from a memory 26, an exclusive OR (XOR) is performed byte by byte, e.g., 8 bits by 8 bits even when the words are 32 bits long. After all of the m-1 blocks of data have been read " in, XOR pipeline 30 contains the parity block. This is written to the destination controller 2 (m) along with the other m-1 blocks of data, which are written to the first m-1 controllers
  • Pipeline 30 communicates with the memories 26 and disk controllers 2 over the data lines subset 31 of system bus 4.
  • address pointer 24 communicates with memories 26 and disk controllers 2 over the address lines subset 32 of system bus 4.
  • the byte count stored in register file 10 is the same for each source 26, because each block of input data has the same number of bytes.
  • State machines 11 give operational authority to the m-1 sources 26 sequentially.
  • a third embodiment of the present invention is a striping coprocessor.
  • the striping coprocessor 23 takes as inputs the m blocks of data that have been written onto the disk controllers 2 by the RAID coprocessor 29 and notionally (via software) stripes these blocks of data onto m I/O controllers 25.
  • Striping is an . intentional scatter, i.e. the data are fragmented into m equally sized blocks. The number of stripes and their widths are based upon hardware considerations.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Advance Control (AREA)
  • Bus Control (AREA)

Abstract

Coprocesseur modulable (9) permettant de renforcer les communications entre une serie d'unités centrales de traitement (CPU) (1) et une série de ressources de système (2), dans un système informatique. Le coprocesseur modulable (9) comprend un fichier unique à registre (10) compartimenté en au moins deux casiers, chaque casier correspondant à une voie virtuelle de coprocesseur. Couplé au fichier à registre (10), un coprocesseur unique effectif (6, 7, 8, 13, 33) effectue des opérations sur les ressources du système (2). Le nombre de voies virtuelles peut être accru à volonté sans qu'il soit nécessaire d'accroître également le nombre d'éléments de voie. Une série d'automates finis programmables (11) accorde l'autorité opérationnelle aux voies virtuelles dans l'ordre et pour la durée souhaitée. Les divers modes de réalisation de la présente invention recouvrent un régisseur d'accès direct à la mémoire (23), un coprocesseur RAID (29) et un coprocesseur d'entrelacement (23).
PCT/JP1993/000617 1992-05-12 1993-05-11 Coprocesseur modulable WO1993023810A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5520052A JPH06509896A (ja) 1992-05-12 1993-05-11 スケーラブル・コプロセッサ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88129992A 1992-05-12 1992-05-12
US07/881,299 1992-05-12

Publications (1)

Publication Number Publication Date
WO1993023810A1 true WO1993023810A1 (fr) 1993-11-25

Family

ID=25378191

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1993/000617 WO1993023810A1 (fr) 1992-05-12 1993-05-11 Coprocesseur modulable

Country Status (2)

Country Link
JP (1) JPH06509896A (fr)
WO (1) WO1993023810A1 (fr)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2714747A1 (fr) * 1993-11-01 1995-07-07 Ericsson Ge Mobile Communicat Dispositif de commande de l'accès partagé à une mémoire de données dans un système multiprocesseur.
EP0772131A3 (fr) * 1995-11-03 1998-02-04 Sun Microsystems, Inc. Méthode et dispositif destiné au support de canaux virtuels pour transmission des données
WO2002015470A3 (fr) * 2000-08-17 2003-02-27 Advanced Micro Devices Inc Systeme et procede de mise en oeuvre d'un canal virtuel separe pour demandes postees dans un systeme informatique multiprocesseur
EP1141843A4 (fr) * 1998-10-19 2005-02-23 Intel Corp Segmentation des donnees d'un reseau redondant de disques independants au moyen de canaux virtuels multiples
US6888843B2 (en) 1999-09-17 2005-05-03 Advanced Micro Devices, Inc. Response virtual channel for handling all responses
US6938094B1 (en) 1999-09-17 2005-08-30 Advanced Micro Devices, Inc. Virtual channels and corresponding buffer allocations for deadlock-free computer system operation
US6950438B1 (en) 1999-09-17 2005-09-27 Advanced Micro Devices, Inc. System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system
US7089344B1 (en) * 2000-06-09 2006-08-08 Motorola, Inc. Integrated processor platform supporting wireless handheld multi-media devices
GB2433611A (en) * 2005-12-21 2007-06-27 Advanced Risc Mach Ltd DMA controller with virtual channels
EP2324430A4 (fr) * 2008-08-06 2012-07-25 Aspen Acquisition Corp Moteur d'accès direct à la mémoire (dma) pouvant être arrêté et redémarré

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000250847A (ja) * 1999-02-26 2000-09-14 Nec Corp データ転送方式
JP4499008B2 (ja) 2005-09-15 2010-07-07 富士通マイクロエレクトロニクス株式会社 Ｄｍａ転送システム
KR102259970B1 (ko) 2017-10-13 2021-06-02 주식회사 엘지에너지솔루션 데이터 입력 스케쥴링 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2211325A (en) * 1987-10-16 1989-06-28 Ziitt DMA controller
EP0365116A2 (fr) * 1988-10-18 1990-04-25 Hewlett-Packard Limited Dispositif mémoire tampon
WO1991011767A1 (fr) * 1990-02-02 1991-08-08 Auspex Systems, Inc. Controleur d'acces direct a une memoire pour le transfert flexible en continu a haute vitesse de donnees d'une source a une destination
EP0482819A2 (fr) * 1990-10-23 1992-04-29 Emc Corporation Reconstruction en ligne d'un système à réseau redondant défaillant

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2211325A (en) * 1987-10-16 1989-06-28 Ziitt DMA controller
EP0365116A2 (fr) * 1988-10-18 1990-04-25 Hewlett-Packard Limited Dispositif mémoire tampon
WO1991011767A1 (fr) * 1990-02-02 1991-08-08 Auspex Systems, Inc. Controleur d'acces direct a une memoire pour le transfert flexible en continu a haute vitesse de donnees d'une source a une destination
EP0482819A2 (fr) * 1990-10-23 1992-04-29 Emc Corporation Reconstruction en ligne d'un système à réseau redondant défaillant

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2714747A1 (fr) * 1993-11-01 1995-07-07 Ericsson Ge Mobile Communicat Dispositif de commande de l'accès partagé à une mémoire de données dans un système multiprocesseur.
US5598575A (en) * 1993-11-01 1997-01-28 Ericsson Inc. Multiprocessor data memory sharing system in which access to the data memory is determined by the control processor's access to the program memory
EP0772131A3 (fr) * 1995-11-03 1998-02-04 Sun Microsystems, Inc. Méthode et dispositif destiné au support de canaux virtuels pour transmission des données
US5875352A (en) * 1995-11-03 1999-02-23 Sun Microsystems, Inc. Method and apparatus for multiple channel direct memory access control
KR100680633B1 (ko) * 1998-10-19 2007-02-09 인텔 코포레이션 다중 가상 채널을 이용하는 ｒａｉｄ 스트라이핑
EP1141843A4 (fr) * 1998-10-19 2005-02-23 Intel Corp Segmentation des donnees d'un reseau redondant de disques independants au moyen de canaux virtuels multiples
US6888843B2 (en) 1999-09-17 2005-05-03 Advanced Micro Devices, Inc. Response virtual channel for handling all responses
US6938094B1 (en) 1999-09-17 2005-08-30 Advanced Micro Devices, Inc. Virtual channels and corresponding buffer allocations for deadlock-free computer system operation
US6950438B1 (en) 1999-09-17 2005-09-27 Advanced Micro Devices, Inc. System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system
US7089344B1 (en) * 2000-06-09 2006-08-08 Motorola, Inc. Integrated processor platform supporting wireless handheld multi-media devices
WO2002015470A3 (fr) * 2000-08-17 2003-02-27 Advanced Micro Devices Inc Systeme et procede de mise en oeuvre d'un canal virtuel separe pour demandes postees dans un systeme informatique multiprocesseur
GB2433611A (en) * 2005-12-21 2007-06-27 Advanced Risc Mach Ltd DMA controller with virtual channels
EP2324430A4 (fr) * 2008-08-06 2012-07-25 Aspen Acquisition Corp Moteur d'accès direct à la mémoire (dma) pouvant être arrêté et redémarré
US8732382B2 (en) 2008-08-06 2014-05-20 Qualcomm Incorporated Haltable and restartable DMA engine

Also Published As

Publication number Publication date
JPH06509896A (ja) 1994-11-02

Similar Documents

Publication Publication Date Title
US5333305A (en) Method for improving partial stripe write performance in disk array subsystems
US7925847B2 (en) Method and apparatus for adjusting timing signal between media controller and storage media
US4872125A (en) Multiple processor accelerator for logic simulation
US5909691A (en) Method for developing physical disk drive specific commands from logical disk access commands for use in a disk array
US5206943A (en) Disk array controller with parity capabilities
EP0768607B1 (fr) Dispositif de commande d'un réseau de disques pour effectuer des operations OU-exclusifs
EP0550164B1 (fr) Méthode et dispositif d'entrelacement d'opérations d'accès direct en mémoire en canaux-multiples
US5185876A (en) Buffering system for dynamically providing data to multiple storage elements
US5553307A (en) Method and device for transferring noncontiguous blocks in one transfer start by creating bit-map indicating which block is to be transferred
CA1150846A (fr) Microprocesseur de traitement de signaux par un nombre fini d'operations
US5522065A (en) Method for performing write operations in a parity fault tolerant disk array
US4916647A (en) Hardwired pipeline processor for logic simulation
CA2029199A1 (fr) Protocole de commande pour bus maitre
WO1993023810A1 (fr) Coprocesseur modulable
KR910017296A (ko) 멀티-마스터 버스 파이프라이닝 실행방법 및 장치
US4873656A (en) Multiple processor accelerator for logic simulation
JP3247075B2 (ja) パリティブロックの生成装置
US5127088A (en) Disk control apparatus
JP2539058B2 (ja) デ―タプロセッサ
US5649209A (en) Bus coupling information processing system for multiple access to system bus
JPH0728758A (ja) ダイナミックタイムループ調停及び装置
EP0619896A1 (fr) Procede permettant d'effectuer des operations sur des ensembles de disques en utilisant un systeme de topographie a taille de bande non uniforme
CN1061153C (zh) 输入/输出设备和处理设备之间的总线仲裁
US5875458A (en) Disk storage device
WO1991001021A1 (fr) Procede et circuit de selection de sequences d'elements programmables

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载