WO1993023845A1 - Liquid crystal display and electronic equipment using the liquid crystal display - Google Patents
Liquid crystal display and electronic equipment using the liquid crystal display Download PDFInfo
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- WO1993023845A1 WO1993023845A1 PCT/JP1993/000639 JP9300639W WO9323845A1 WO 1993023845 A1 WO1993023845 A1 WO 1993023845A1 JP 9300639 W JP9300639 W JP 9300639W WO 9323845 A1 WO9323845 A1 WO 9323845A1
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 308
- 239000003990 capacitor Substances 0.000 claims abstract description 43
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3622—Control of matrices with row and column drivers using a passive matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3622—Control of matrices with row and column drivers using a passive matrix
- G09G3/3625—Control of matrices with row and column drivers using a passive matrix using active addressing
Definitions
- the present invention uses a simple matrix method to display characters, graphics, etc. on a liquid crystal panel.
- the present invention relates to a liquid crystal display device and an electronic device using the same.
- a driving method generally called a voltage averaging method is conventionally used. Also, among the voltage averaging methods, a six-level driving method is widely used.
- Japanese Patent Application Laid-Open No. 2-89 discloses an outline of a six-level driving method.
- the six-level driving method will be described with reference to FIGS.
- FIG. 23 is a diagram showing the structure and display contents of the liquid crystal panel.
- the liquid crystal panel 300 is composed of a liquid crystal layer (not shown) and a pair of substrates 302 and 304 sandwiching the liquid crystal layer.
- S-plate 302 scanning electrodes # 1 to # 6 are formed in the # direction.
- signal electrodes XI to ⁇ 6 are formed on the other substrate 304.
- the intersection between the fixed electrodes ⁇ 1 to ⁇ 6 and the symbol electrodes X1 to ⁇ 6 is the display dot.
- the hatched display dots indicate the lighting state, and the other display dots indicate the non-lighting state.
- liquid crystal panel 3 ⁇ 0 shown in FIG. 23 has a 6 ⁇ 6 dot configuration, but this is for the sake of simplicity, and the actual number of dots of the liquid crystal panel is usually Much more.
- a selection voltage or a non-selection voltage is sequentially applied to each of the scan electrodes # 1 to # 6.
- the period required for sequentially applying the selection voltage to all the scanning electrodes # 1 to # 6 is called one frame.
- a selection voltage or a non-selection voltage is sequentially applied to each of the scanning electrodes ⁇ 1 to -6-6
- a lighting voltage or a non-lighting voltage is simultaneously applied to each of the symbol electrodes X1 to ⁇ 6. Is done. That is, when the display electrode at the intersection of a certain scanning electrode and a certain signal electrode is turned on, a lighting voltage is applied to the symbol electrode when the scanning electrode is selected. When not lighting, non-lighting voltage is applied. It is.
- FIGS. 24A to 24C and FIGS. 25A to 25C are diagrams illustrating examples of actual driving waveforms (applied voltage waveforms).
- FIG. 24A shows the signal voltage waveform applied to the signal electrode X5 shown in FIG. 23 described above
- FIG. 24B shows the scan voltage waveform applied to the scan electrode Y3
- FIG. 24C shows the signal electrode X5 and the scan electrode Y3 shown in FIG. The voltage waveform applied to the display dot (lighting state) at the intersection with is shown.
- Fig. 25A shows the signal voltage waveform applied to the signal electrode X5
- Fig. 25B shows the scanning voltage waveform applied to the scanning electrode Y4
- Fig. 25C shows the display dot at the intersection of the signal electrode X5 and the scanning electrode Y4. The waveforms of the voltages applied to each of the power supplies (non-lighting state) are shown.
- F 1 and F 2 are frame periods.
- V0 -V5 k ⁇ V (k is a positive number)
- AC driving is performed by changing the polarity in the frame periods F1 and F2.
- Japanese Patent Application Laid-Open No. Sho 62-31825 discloses a six-level driving method in which the polarity is periodically switched at intervals other than the frame periods Fl and F2.
- Another driving method other than the 6-level driving method is the so-called IHAT method.
- This driving method was proposed by TNRuckmongathan, (1988 International Display Research Conference) 0
- the scanning electrode Y1 When the scanning electrode Y1 is not selected in the frame period F1, the non-selection voltage V4 is applied to the scanning electrode Y1. At this time, when the scanning electrode to which the selection voltage is applied (hereinafter referred to as “selected scanning electrode”) shifts from Y2 to Y6, the signal electrodes XI to X4.X6 are turned off with the lighting voltage V5. The voltage V3 is applied alternately and repeatedly. Therefore, during the period when the scan electrode Y1 is not selected, each display dot formed as an intersection of the scan electrode Y1 and the signal electrode XI-X4.X6 alternately has a voltage of 1 V and + V. Is applied.
- the scanning electrodes Y1 to Y6 and the signal electrodes XI to # 4, # 6 are each formed to have a certain width, and the liquid crystal layer functions as a dielectric, so that each display dot becomes a capacitor equivalent to electric. Therefore, the AC voltage described above is applied to this capacitor, and power is consumed in the power supply circuit that applies the drive voltage to the liquid crystal panel 30 °.
- the power consumption increases not only when the display dot for each scan electrode alternates between lighting and non-lighting alternately within a certain frame period, but also when the polarity is changed halfway. Is the same.
- display unevenness may occur depending on a pattern of characters, figures, and the like displayed on the liquid crystal panel. there were.
- the occurrence of display unevenness has been improved by using the I HAT method. It was impossible to completely eliminate display irregularities.
- the display dot has a capacitance determined by its area, the thickness of the liquid crystal layer, and the dielectric constant of the liquid crystal material.
- both the scanning electrode and the signal electrode are generally made of a transparent conductive film having a sheet resistance of about several tens of ohms, and of course have a certain electrical resistance. Is raised.
- the present invention has been made in view of such problems of the related art, and a liquid crystal panel driving method, a liquid crystal display device, and a liquid crystal display device that reduce power consumption and suppress display unevenness. To provide electronic devices.
- a liquid crystal panel having a liquid crystal layer sandwiched between a plurality of scanning electrodes and a plurality of signal electrodes;
- First voltage applying means for applying a scanning voltage consisting of a selection voltage and a non-selection voltage to a plurality of scanning electrodes of the liquid crystal panel;
- Second voltage applying means for applying a signal voltage comprising a lighting voltage and a non-lighting voltage to a plurality of signal electrodes of the liquid crystal panel;
- the scanning electrode and the signal are connected to the first voltage applying unit and the second voltage applying unit, and are connected to the display dots of the liquid crystal panel in accordance with a lighting state of each display dot.
- liquid crystal panel is AC-driven.
- the polarity of the drive voltage is inverted according to the lighting state of each display dot of the liquid crystal panel, thereby increasing power consumption and display unevenness that may be caused by a display pattern. It can be reduced.
- the polarity inversion control means is configured such that when the scan electrode to which the selection voltage is applied by the first voltage application means is switched, the polarity of the drive voltage is not inverted with respect to a field base in which the polarity is inverted.
- the polarity inversion control means is configured to control the number of the signal electrodes whose lighting state of a display dot changes when the scanning electrodes to which the selection voltage is applied by the first voltage application means are switched. And determining the amount of the electric charge by comparing the obtained number of signal electrodes with a predetermined number.
- the predetermined number is approximately one half of the total number of the symbol electrodes.
- the predetermined number is a half of the total number of the signal electrodes.
- the feature is that the value is larger. .
- the amount of charge movement when the polarity of the driving voltage is inverted and the amount of charge movement when the polarity is not inverted are not exactly compared under the same conditions.
- the size can be reduced, and the configuration of the liquid crystal display device can be simplified.
- the predetermined number is set such that, when the scanning electrode to which the selection voltage is applied by the first voltage applying means is switched, the scanning is performed by a display dot on the scanning electrode.
- the setting is made in consideration of the capacitance of a capacitor formed between an electrode and the signal electrode.
- the capacitance of the capacitor formed on the selected scanning electrode is taken into consideration, and the power consumption can be reliably reduced by accurately controlling the polarity inversion.
- the predetermined number is set in consideration of a capacitance of a capacitor included in a power supply circuit that generates the scanning voltage and the signal voltage.
- the polarity inversion control means includes a case where the polarity of the driving voltage is not inverted when the scanning electrode to which the selection voltage is applied by the first voltage application means is switched.
- the inverted field base the sum of the voltage change of the signal electrode with respect to the non-selection voltage is obtained, and the polarity of the drive voltage is inverted only when the polarity is inverted when the sum of the voltage changes is smaller. It is characterized in that it performs control to make it.
- the total change in the voltage of the signal electrode can be reduced, so that the occurrence of display unevenness due to the voltage change can be reduced.
- the polarity inversion control means controls the inversion of the polarity of the drive voltage according to the lighting state of each display dot of the liquid crystal panel, and the lighting state of each display dot of the liquid crystal panel. Regardless of the above, a combination with control for inverting the polarity of the drive voltage at a predetermined cycle is a special feature.
- the polarity inversion control means limits the number of times of the polarity inversion. Further, the polarity inversion control means changes the frequency of the polarity inversion in accordance with the number of times that the condition for inverting the polarity is satisfied within a predetermined period. As a result, it is possible to prevent the driving frequency of the liquid crystal panel from becoming abnormally high, and to reduce the occurrence of display unevenness.
- a liquid crystal panel having a liquid crystal layer sandwiched between a plurality of scanning electrodes and a plurality of signal electrodes;
- First voltage applying means for applying a scanning voltage consisting of a selection voltage and a non-selection voltage to a plurality of scanning electrodes of the liquid crystal panel;
- Second voltage applying means for applying a signal voltage comprising a lighting voltage and a non-lighting voltage to a plurality of signal electrodes of the liquid crystal panel;
- a driving device that is connected to the first voltage applying unit and the second voltage applying unit, and that is a potential difference between the scanning electrode and the signal electrode according to a lighting state of each display dot of the liquid crystal panel.
- a polarity inversion means for performing control for inverting the polarity of the voltage
- the polarity inversion control means includes a case where the polarity of the drive voltage is inverted when the scan electrode to which the selection voltage is applied is switched by the first voltage application means, and a case where the polarity is inverted. If not, determine the amount of charge transfer through the capacitor created by the display dot, and perform control to invert the polarity of the drive voltage when the polarity is inverted when the amount of charge transfer is small. It is characterized by.
- the polarity inversion control means includes a base that does not invert the polarity of the dynamic voltage when the scan electrode to which the selection voltage is applied by the first voltage application means is switched.
- the inverted field base For the inverted field base, the sum of the voltage changes of the signal electrodes with respect to the non-selection voltage is calculated, and the polarity is inverted when the voltage is inverted. Only when the sum of the pressure changes is small, the control for inverting the polarity of the drive voltage is performed.
- the polarity of the drive voltage is appropriately inverted according to the display pattern on the liquid crystal panel, so that power consumption can be reduced and display unevenness can be suppressed.
- FIG. 1 is a diagram showing a configuration of a liquid crystal display device of a first embodiment to which the present invention is applied
- FIG. 2 is a diagram showing a configuration of a liquid crystal panel used in the first embodiment
- FIGS. 3A and 3B are diagrams showing an example of a detailed configuration of the level shifter circuit ⁇
- FIG. 4 is a diagram showing a detailed configuration of the polarity inversion circuit of the first embodiment
- FIG. 5 is a diagram showing the operation timing of the liquid crystal display device of the first embodiment
- 6A to 6G are diagrams showing voltage waveforms applied to each signal electrode and scanning electrode when driving a liquid crystal cell and a channel by performing polarity inversion by the polarity inversion control circuit of the first embodiment.
- FIG. 7 is a diagram showing the configuration of the liquid crystal display device of the second embodiment
- FIG. 8 is a diagram showing the structure of the liquid crystal display device of the fourth embodiment.
- FIG. 9 is a diagram showing the detailed configuration of the power supply circuit
- FIG. 10 is a diagram showing a configuration of a liquid crystal display device of a fifth embodiment
- FIG. 11 is a diagram showing a configuration of a liquid crystal display device of a seventh embodiment
- FIG. 12 is a diagram showing an example of a lighting state of each display dot in the liquid crystal panel of the seventh embodiment.
- FIGS. 13A to 13H are diagrams showing voltage waveforms applied to the respective electrodes when the pattern shown in FIG. 12 is displayed on the liquid crystal panel shown in FIG. 11, and FIG. 14 is a diagram showing the liquid crystal panel.
- FIG. 15 is a diagram showing another example of the lighting state of each display dot in FIG. 15,
- FIG. 15 is a diagram showing the configuration of a liquid crystal display device of an eighth embodiment to which a forcible polar end is added,
- FIG. 16 is a diagram showing a configuration of a liquid crystal display device of a ninth embodiment in which polarity inversion is restricted
- FIG. 17 shows a liquid crystal display device of a tenth embodiment in which the frequency of polarity reversal is changed stepwise. Diagram showing the configuration of the device,
- FIG. 19 is a diagram showing a configuration of the liquid crystal display device of the first embodiment
- FIG. 20 is a diagram showing an example of a lighting state of each display dot of the liquid crystal panel in the first embodiment.
- Fig. 22 is a diagram showing the operation timing of the liquid crystal display device of the first embodiment
- Fig. 23 is a conventional liquid crystal display. Diagram showing the structure and display contents of the panel
- FIGS. 24A to 24C are diagrams showing an example of a conventional drive waveform.
- FIGS. 25A to 25C are diagrams showing an example of a conventional drive waveform.
- the liquid crystal display device of the first embodiment is characterized in that the polarity of the drive voltage applied to the liquid crystal panel is inverted according to the pattern of characters, graphics, etc. displayed on the liquid crystal panel. By performing such polarity inversion, the power consumption of the liquid crystal display device can be reduced.
- the liquid crystal display device of the present embodiment uses a six-level driving method, and six different voltages V 0 to V 5 are defined as follows.
- Lighting voltage V5
- Second voltage group (corresponding to frame period F2 in conventional 6-level drive method)
- V0-V5 k »V (k is a positive number)
- FIG. 1 is a diagram showing a configuration of a liquid crystal display device of a first embodiment to which the present invention is applied.
- This liquid crystal display device has a polarity inversion control circuit 32, which inverts the polarity of the drive voltage applied to the liquid crystal panel 10 according to the pattern of characters, figures, etc. displayed on the liquid crystal panel 10. It is characterized by AC drive.
- the power inversion of the power supply circuit 30 that supplies the drive voltage to the liquid crystal panel 10 can be reduced by this polarity inversion.
- the liquid crystal display device shown in FIG. 1 includes a liquid crystal panel 10 having a predetermined number of scanning electrodes and signal electrodes, an X driver 16 for applying a lighting voltage or a non-lighting voltage to the signal electrodes, and a selection of the scanning electrodes.
- a Y driver 24 for applying a voltage or a non-selection voltage
- a power supply circuit 30 for applying a predetermined voltage to the X driver 16 and the Y driver 24, and applying the liquid crystal panel 10 from the X driver 16 and the Y driver 24.
- a polarity inversion control circuit 32 for appropriately inverting the polarity of the lighting voltage and the like.
- the first voltage applying means corresponds to the X driver 16 and the power supply circuit 30.
- the second voltage applying means corresponds to the Y driver 24 and the power supply circuit 3 °.
- FIG. 2 is a diagram illustrating a configuration of the liquid crystal panel 10 described above.
- the liquid crystal panel 10 includes a pair of substrates 12 and 14 sandwiching a liquid crystal layer (not shown).
- the substrate 12 six signal electrodes X1 to X6 are formed.
- the substrate 14 six scanning electrodes Y1 to Y6 are formed. Each of the scanning electrodes Y1 to # 6 and each of the signal electrodes X1 to X6 intersect to form a display dot, thereby forming a screen.
- the hatched display dots indicate that they are lit.
- the X driver 16 shown in FIG. 1 applies a lighting voltage or a non-lighting voltage to each of the signal electrodes X1 to X6 of the liquid crystal panel 1 °.
- the X driver 16 includes a shift register circuit 18, a latch circuit 20, and a level shifter circuit 22.
- the shift register circuit 18 converts the sequentially input six 1-bit data into 6-bit parallel data and outputs it.
- the latch circuit 20 temporarily holds the 6-bit parallel data output from the shift register circuit 18, and has the same 6-bit capacity as the parallel data.
- the level shifter circuit '22 sets a voltage level corresponding to each bit of the 6-bit data output from the latch circuit 20, and applies the set voltage to each signal electrode of the liquid crystal panel 1 °. Is applied as a lighting voltage or a non-lighting voltage.
- FIG. 3A and 3B are diagrams illustrating an example of a detailed configuration of the level shifter circuit 22.
- FIG. FIG. 3A shows an example in which the level shifter circuit 22 is configured by a 4-input / 1-output multiplexer 22a.
- the level shifter circuits 22 are provided with the multiplexers 22a as many as the number of signal electrodes.
- the multiplexer 22 a has four input terminals to which voltages V 2, V 0, V 3, and V 5 are applied, and any one of them based on the output of the latch circuit 20 and the polarity inversion signal FRI. The switching operation is performed so that the voltage applied to the input terminal appears at the output terminal.
- the logic of the polarity inversion signal FRI is "1"
- the first signal voltage is selected, and the lighting voltage V5 or the non-lighting voltage V3 is selected according to the output of the latch circuit 20.
- the logic of the polarity inversion signal FRI is "0”
- the second signal voltage is selected, and the lighting voltage V ⁇ or the non-lighting voltage V2 is selected according to the output of the latch circuit 2 •.
- FIG. 3B shows an example in which the level shifter circuit 22 is composed of three multiplexers 2 2 b, 22 c and 22 d having two inputs and one output.
- Level shifter circuit 2 2 are provided with these multiplexers 22b, 22c, and 22d by the number of i-th electrodes.
- the multiplexer 22b has two input terminals to which the lighting voltage V5 and the non-lighting voltage V3, which are the first signal voltages, are applied, and outputs one of the voltages according to the output of the latch circuit 20. select.
- the multiplexer 22c has two input terminals to which a second signal voltage, a lighting voltage V0 and a non-lighting voltage V2, is applied, and selects one of the voltages according to the output of the latch circuit 20. I do.
- the multiplexer 22d has two input terminals to which the two voltages selected by the multiplexers 22b and 22c are applied.
- the logic of the polarity inversion signal FRI is "1”
- the first signal voltage applied through the multiplexer 22c is selected.
- the logic of the polarity inversion signal FRI is "0”
- the first signal voltage applied through the multiplexer 22d is selected.
- a second signal voltage to be applied is selected.
- the Y driver 24 applies a selection voltage or a non-selection voltage to each of the scanning electrodes Y1 to Y6 of the liquid crystal panel 1 °.
- the driver 24 includes a shift register circuit 26 and a level shifter circuit 28.
- the shift register circuit 26 shifts the data-in signal DI, which is input once per frame, in synchronization with the latch pulse L ⁇ , and if any one bit is “1” and the other bits are “0”, It outputs 6-bit parallel data that is ".
- the latch pulse LP is input at the timing of switching the selected scan electrode, and is input as many as the number of scan electrodes within one frame.
- the level shifter circuit 28 sets a voltage level corresponding to each bit of the 6-bit parallel data output from the shift register 26, and applies the set voltage to each scanning electrode of the liquid crystal panel 1 ⁇ . Applied as a scanning electrode or non-lighting voltage.
- the detailed configuration of the level shifter circuit 28 is basically the same as that of the level shifter circuit 22 of the X driver 16 and the configuration of FIG. 3A or 3B can be applied as it is.
- the first and second signal voltages V5, V3, V0, and V2 applied to the input terminals of the multiplexers 22a, 22b, and 22c are the first and second signal voltages. It is necessary to place them at the second scanning voltage V0, V4, V5, V1.
- the power supply circuit 3 ⁇ generates six different voltages V0 to V5 at the terminals T0 to T5, and applies these voltages to the X driver 16 and the ⁇ driver 24. Specifically, the power supply circuit 3 ⁇ applies the first and second signal voltages V5, V3, V0, and V2 to the level shifter circuit 22 in the X driver 16, and performs the first and second scans. The voltages VO, V4, V5, and V1 are supplied to the level shifter circuit 28 in the driver 24.
- the polarity inversion control circuit 32 responds to the pattern of characters, figures, and the like displayed on the liquid crystal panel 1, and specifically, displays dots of the currently selected scan electrode and the next selected scan electrode.
- the polarity of the signal voltage applied to the liquid crystal panel 10 and the polarity of the scanning voltage are switched according to the pattern of the data.
- the polarity inversion control circuit 32 includes an address generation circuit 34, a storage element 36, a mismatch detection circuit 38, a counting circuit 40, a size comparison circuit 42, and a polarity inversion circuit 44.
- the address generation circuit 34 is a circuit that generates a storage address of the storage element 36.
- the address generating circuit 34 is constituted by, for example, a counter, reset when a latch pulse L # is input, performs a count operation in synchronization with a clock signal C # input thereafter, and counts the count value. Is output as an address.
- the storage element 36 is constituted by a RAM, and has a capacity to store data DT for six display dots corresponding to one scanning electrode of the liquid crystal panel 10.
- the storage element 36 stores the data D T input in synchronization with the clock signal CK in an area specified by the address output from the end address generation circuit 34.
- the storage element 36 outputs the data DT stored in the area specified by the address output from the address generation circuit 34. I do. Therefore, the data D T of the immediately preceding scan electrode is output from the storage element 36, and the data D T of the currently input scan electrode is sequentially stored in the storage element 36.
- the mismatch detecting circuit 38 detects whether the data DT corresponding to the immediately preceding scan electrode output from the storage element 36 is different from the data DT of the currently input scan electrode. That is, the mismatch detection circuit 38 The lighting states of the display dots on the same symbol electrode are compared for the electrodes.
- the counting circuit 40 counts the specific nests by the inconsistency detection circuit 38, and is constituted by, for example, a counter.
- the comparison result of the mismatch detection circuit 38 is input to the enable terminal of the counter constituting the counting circuit 40, and this counter counts up in synchronization with the clock signal C # only when the comparison result indicates a mismatch. .
- the count is reset when the latch pulse L # is input.
- the magnitude comparing circuit 42 compares the magnitude of a predetermined value (here, 3 which is half the number of signal electrodes of the liquid crystal panel 10) with the count value of the counting circuit 40.
- the polarity inversion circuit 44 inverts the polarity inversion signal FRI in synchronization with the latch pulse L P when the count fit by the counting circuit 4 ° is larger than a predetermined value based on the comparison result by the magnitude comparison circuit 42. For example, the polarity inversion circuit 44 inverts the polarity inversion signal FRI from “0" to "1” or from “1” to "0” when the count value of the counting circuit 40 is larger than a predetermined value. Output.
- the polarity inversion signal FRI is input to the level shifter circuit 22 of the X driver 16 and the level shifter circuit 28 of the Y driver 24.
- FIG. 4 is a diagram showing a detailed configuration of the polarity inversion circuit 32.
- the polarity inversion circuit 44 is composed of exclusive OR gates EX-OR) 46 and D-type flip-flop (D-FF) 48.
- the result of comparison by the magnitude comparison circuit 42 is input to one input terminal of EX-0R46, and the polarity inversion signal FR I output from the output terminal Q of D-FF48 is input to the other input terminal. ing.
- the output of this EX-0R46 is input to the input terminal D of D-FF48.
- the latch pulse LP is input to the clock terminal of D-FF48 in negative logic.
- the following numbers Na.Nb.Nc.Nd are defined, and whether to invert the polarity is determined based on these numbers and the total number S of the number of signal electrodes.
- Na be the number of signal electrodes for which the display dots formed between the scanning electrodes ⁇ + 1 are not lit during this period.
- a display dot formed between the signal electrode Xn and the scan electrode Yn is not lit, and is formed between the signal electrode Xn and the scan electrode Yn + i during a period in which the scan electrode Yn + i is selected. 3 ⁇ 4 of the signal electrode whose display dot is lit is Nb.
- the display dot formed between the signal electrode Xn and the scan electrode Yn is turned on, and the display dot formed between the signal electrode Xn and the scan electrode Yn + i during the period in which the scan electrode Yn + 1 is selected.
- Nc be the number of signal electrodes where the light is on.
- the product of the capacitance V of the capacitor between the scan electrodes other than the two scan electrodes Yn and Yn + i and each signal electrode, and the difference V between the non-selection voltage and the lighting voltage (or the non-lighting voltage). Is Q. If the capacitance of this capacitor is c, then Q 398xc xV.
- the calculation was performed with the number of scanning electrodes being 400.
- each of the scanning electrode Y and the signal electrode X is formed with a certain width, and since the liquid crystal layer functions as a dielectric, each display dot becomes a capacitor in an electrically equivalent manner.
- the width of each electrode of the scanning electrode and the signal electrode of the liquid crystal panel 10 is 0.33 mm.
- the distance between the scanning electrode and the signal electrode is 5 m, and the relative permittivity of the liquid crystal is 5 (exactly depending on driving conditions. However, it is fixed here for the sake of simplicity).
- the capacitance c of the capacitor created by each display dot is
- the voltage selected based on the polarity reversal signal FRI switches from the second voltage group to the first voltage group.
- the electric charge of 2Ne Q moves from terminal TO of power supply circuit 30 to ⁇ 1
- the electric charge of 2Nd Q moves from terminal T1 to terminal T2. Therefore, the average current consumption is (Nc + Nd) x 39.8 amps.
- the voltage selected based on the polarity inversion signal FRI switches from the first voltage group to the second voltage group.
- the average current consumption is (Nc + Nd) x 39.8 amps.
- the voltage selected based on the polarity inversion signal FRI When the voltage changes from the first voltage group to the second voltage group and when the voltage changes from the second voltage group to the first voltage group (when the polarity is reversed), the current consumption increases as Ne + Nd increases. However, when the polarity does not reverse, the current consumption increases as N a + N b increases.
- FIG. 5 is a diagram showing the operation timing of the liquid crystal display device of the present embodiment.
- data DT synchronized with the clock signal CK is input to the liquid crystal display device in bit units.
- the shift register circuit 18 in the X driver 16 captures the input data DT in synchronization with the fall of the clock signal CK.
- the fetched data DT is shifted bit by bit.
- the shift register circuit 18 receives data of the same number of bits as the number of signal electrodes 6 of the liquid crystal panel 1 °, the latch circuit 20 that operates in synchronization with the latch pulse signal LP is connected to the shift register circuit 18. It takes in and stores 6-bit data corresponding to each stored signal electrode.
- the level shifter circuit 22 determines which of the first signal voltage and the second signal voltage depends on the data held in the latch circuit 20 and the logic state of the polarity inversion signal FRI input from the polarity inversion control circuit 32 at this time. Is applied to each signal electrode of the liquid crystal panel.
- the shift register circuit 26 of the Y driver 24 receives a data-in signal DI synchronized with the latch pulse LP.
- the shift register circuit 26 receives the data inputted at a rate of once for every six pitch pulses LP.
- One tine signal DI is shifted sequentially in synchronization with the latch pulse LP. Therefore, every time the latch pulse LP is input, the effective scanning electrode changes from ⁇ ⁇ ⁇ to ⁇ ⁇ 6 in order.
- the selection voltage V 0 or V 5 is applied only to the scan electrode Y 1, and the other scan electrodes ⁇ 2 to ⁇ ⁇ 6 are applied to the other scan electrodes ⁇ 2 to ⁇ 6.
- Non-selection voltage V4 or V2 is applied. Therefore, only the scanning electrode Y1 to which the selection voltage is applied becomes effective, and only the display dots formed by this scanning electrode Yi and the six signal electrodes XI to X6 become effective, and these display electrodes become effective.
- the dot is turned on or off according to the signal voltage applied to the signal electrodes X1 to X6.
- the effective scanning electrodes change in order from Y2 to Y6, and each time the display dots formed on each signal electrode are lit according to the signal voltage applied to the if electrode XI to XB, Is turned off.
- the polarity inversion control circuit 32 controls the lighting state of the display dot formed on the currently selected scan electrode Yn and the next selectable scan electrode ⁇ + l. Find out. Then, the logic state of the polarity inversion signal FRI supplied to the X driver 16 and the $ driver 24 is switched according to the checked lighting state.
- the specific operation of the polarity inversion control circuit 32 will be described by taking the display pattern of the liquid crystal panel 10 shown in FIG. 2 as an example.
- the value of Na + Nb is calculated by the mismatch detection circuit 38 and the counting circuit 4 of the polarity reversal control circuit 32.
- the magnitude comparison between Na + Nb and S Z 2 is performed by the magnitude ratio circuit 42.
- the polarity inversion circuit 44 performs the polarity inversion when the scan electrode is switched based on the comparison result by the magnitude comparison circuit 42 as follows.
- Na + Nb SZ2
- the polarity may or may not be inverted. However, in this embodiment, the polarity is inverted.
- FIGS. 6B to 6G show voltage waveforms applied to the signal electrodes XI to X6, respectively.
- the scanning voltage waveform applied to the scanning electrode Y2 is indicated by a dotted line.
- t1 to t6 indicate the time during which the selection voltage is applied to the scan electrodes Y1 to Y6, respectively.
- the liquid crystal panel 10 is driven by performing the following polarity inversion at each of the times t1 to t6.
- Time t 1 The liquid crystal panel 10 is driven using the first voltage group.
- Time t 2 Since the polarity inversion is performed, the liquid crystal panel 10 is driven using the second voltage group.
- Time t 3 Since the polarity inversion is not performed, the liquid crystal panel 10 is driven using the second voltage group.
- Time t4 Since the polarity inversion is performed, the liquid crystal panel 10 is driven using the first voltage group.
- Time t 5 Since the polarity inversion is performed, the liquid crystal panel 10 is driven using the second voltage group.
- Time t 6 Since the polarity inversion is not performed, the liquid crystal panel 10 is driven using the second voltage group.
- the amount of charge emitted by the liquid crystal panel 10 when the selected scanning electrode is switched from Y1 to Y2 is examined.
- the capacitance of the capacitor formed by each display dot is c, and the amount of charge and discharge from the capacitor formed by each signal electrode Xm and the scanning electrodes Y1 and Y2 is ignored.
- Each of the signal electrodes XI to X5 switches from the lighting voltage to the non-lighting voltage, but at the same time the polarity is inverted, so the voltage applied to the capacitor formed by each of the signal electrodes XI-X5 and the scanning electrodes Y3 to Y8 does not change. . Therefore, there is no charge release.
- the voltage applied to the signal electrode X6 is still the non-lighting voltage, but since it reverses its polarity, it is applied to the four display dots formed by the signal electrode X6 and the scanning electrodes Y3 to Y6. Voltage changes from 1 V to V. Therefore, the emitted charge is 4 X c 2 V coulomb. That is, when the selected scanning electrode is switched to the Y1 force, the liquid crystal panel 10 emits only 8 cV coulomb.
- the driving method of determining whether to perform the polarity inversion according to the display content of the liquid crystal panel 1 ° the charge and discharge of the charge generated by the capacitor formed by the scanning electrode and the symbol electrode can be reduced.
- power consumption for driving the liquid crystal panel 10 can be reduced.
- the 6 ⁇ 6 dot liquid crystal panel 10 shown in FIG. 2 was considered, but the actual liquid crystal panel has a scale of, for example, about 400 ⁇ 640 dots.
- the conventional driving method is used. Calculating the power consumption when displaying is as follows.
- the selected scanning electrode switches from ⁇ ( ⁇ is 1 to 4 or 0) to ⁇ + 1
- the voltage applied to all signal electrodes XI to ⁇ 640 on the screen is Switching from lighting voltage to non-lighting voltage or from non-lighting voltage to lighting voltage.
- a non-selection voltage is applied to the other scanning electrodes other than the scanning electrodes ⁇ and ⁇ + 1.
- each display dot has a capacitance of about 1 pF, during the period when the scan electrode ⁇ is selected, all of the other scan electrodes and the display panel other than the scan electrodes ⁇ and ⁇ + 1
- the signal is accumulated in the display dots (capacitors) created by the scanning electrodes ⁇ and other scanning electrodes other than ⁇ + 1 and all the signal electrodes Xi to ⁇ 640 on the screen.
- Charge q 2 the display dots (capacitors) created by the scanning electrodes ⁇ and other scanning electrodes other than ⁇ + 1 and all the signal electrodes Xi to ⁇ 640 on the screen.
- the power consumption is expected to be reduced to about 1 Z2.5, and about 10 Z in one frame period. It is expected that the power consumption will be about mA.
- the liquid crystal display device of the second embodiment controls the inversion of the polarity of the drive voltage applied to the liquid crystal panel 10 according to the pattern of characters, figures, and the like displayed on the liquid crystal panel.
- Such inversion control is referred to as “internal polarity inversion control”, and external polarity inversion control (hereinafter, such inversion control is referred to as “external polarity inversion control”).
- Examples of the external polarity inversion control include a case where the polarity is inverted for each frame as in the related art, and a case where the polarity is determined in units of a predetermined number of scanning electrodes disclosed in Japanese Patent Laid-Open No. 62-31825. In some cases, it is reversed.
- FIG. 7 is a diagram illustrating a configuration of a liquid crystal display device to which external polarity inversion control is added. In this liquid crystal display device, the polarity inversion is performed only when the polarity inversion by one of the internal polarity inversion control and the external polarity inversion control is instructed.
- the liquid crystal display device shown in FIG. 1 includes a liquid crystal panel 10, an X driver 16, a Y driver 24, a power supply circuit 30, a polarity inversion control circuit 32, and an exclusive OR gate (EX-OR) 50.
- Configurations other than EX-OR 50 are basically the same as the liquid crystal display device of the first embodiment shown in FIG. Therefore, description of the common part will be omitted, and the liquid crystal display device of the second embodiment will be described focusing on the difference, EX-0R50.
- the polarity inversion signal FRI output from the polarity inversion circuit 44 in the polarity inversion control circuit 32 is input to one input terminal of EX-0 R 50, and the other input terminal is externally input. External polarity inversion signal FRA is input.
- the external polarity inversion signal FRA is logically changed from “0" to "1” or from “1” to "0” in a cycle corresponding to the number of scanning electrodes included in the liquid crystal panel 10 or an arbitrary number of scanning electrodes. Is inverted. This cycle is not limited to one, and may have a plurality of cycles.
- the output terminal of the EX-OR 50 is connected to a level shifter circuit 22 in the X driver 16 and a level shifter circuit 28 in the Y driver 24, respectively.
- This EX-OR50 outputs the exclusive OR of the signals input to the two input terminals, so that the logic of either the polarity inversion signal FR I or the external polarity inversion signal FR A is inverted. At this time, the logic of the signal appearing at the output terminal is inverted. Therefore, when only one of the polarity K inverted signal FR I and the external polarity inverted signal FR A is inverted, the voltage applied to the signal electrodes XI to X6 and the scanning electrodes Yl to Y6 of the liquid crystal panel 10 is changed. Polarity inversion is performed.
- the polarity inversion when the polarity inversion is not performed for a long time depending on the display content of the liquid crystal panel 10, the polarity inversion is forcibly performed by the external inversion control. Therefore, it is possible to avoid a decrease in contrast that may be caused by the above.
- the polarity inversion is performed. I have to. Therefore, the number of bits of the counting circuit 40 is reduced, and the number of bits of data handled by the magnitude comparison circuit 42 is also reduced, so that the circuit configuration of the polarity inversion control circuit 32 is simplified.
- the liquid crystal display device according to the third embodiment has basically the same configuration as the liquid crystal display device according to the first embodiment shown in FIG. Compared to the first embodiment, the difference is that the number of pits in the counting circuit 40 is small and that the comparison target by the size comparison circuit 42 is changed from SZ2 to SZP. I have.
- the comparison by the magnitude comparison circuit 42 is performed based on 1 / P of the number S of the signal electrodes: Even if there is, basically, the polarity is inverted according to the display content of the liquid crystal panel 10. The charge and discharge of the capacitor formed by the scanning electrode and the signal electrode are reduced, and the power consumption for driving the LCD panel 10 can be reduced. Become.
- the influence of the capacitor formed by the display dot on the scanning electrode which is changed from selection to non-selection or from non-selection to selection is neglected. This effect is considered in the liquid crystal display device of the fourth embodiment.
- FIG. 8 is a diagram illustrating a configuration of a liquid crystal display device according to a fourth embodiment.
- the crystal display device includes a liquid crystal panel 10, an X diversity 16, a Y driver 24, a power supply circuit 30, and a polarity inversion control circuit 52.
- the configuration other than the polarity inversion control circuit 52 is basically the same as the liquid crystal display device of the first embodiment shown in FIG.
- the polarity inversion control circuit 52 includes an address generation circuit 34, a storage element 36, a mismatch detection circuit 38, a counting circuit 40, a polarity inversion circuit 44, a continuous non-lighting detection circuit 54, a counting circuit 56, an arithmetic operation circuit 58, and a magnitude comparison circuit 60. It is comprised including. Among them, the continuous non-lighting detection circuit 54, the counting circuit 56, the arithmetic operation circuit 58, and the size comparison circuit 60 are different from those in the first embodiment, and these will be described in detail below.
- the continuous non-lighting detection circuit 54 and the counting circuit 56 are provided for obtaining the above-mentioned Nd. That is, the continuous non-lighting detection circuit 54 sets both the data D and the data DT of the currently input scanning electrode corresponding to the immediately preceding scanning electrode output from the memory element 36 to “0”. It detects that both display dots adjacent to the two scanning electrodes are not lit.
- the counting circuit 56 counts the detection result by the continuous non-lighting detection circuit 54, and is constituted by, for example, a counter.
- the detection result of the continuous non-lighting detection circuit 54 is input to the enable terminal of the counter constituting the counting circuit 56.
- This counter counts up in synchronization with the clock signal CK only when a continuous non-lighting state is detected by the continuous non-lighting detection circuit 54, and the count value is output from the counter circuit 56 as Nd.
- This counter is reset when a latch pulse LP is input.
- the arithmetic operation circuit 58 calculates the value of (S ⁇ S ⁇ 4Nd) / (2S ⁇ 1) based on the count value (Nd) of the counting circuit 56 described above. If the value of the number S of signal electrodes is sufficiently large, 2 S-1 approaches 2 S, so instead of calculating the value of (S ⁇ S— 4 Nd) (2 S-1), (SZ2) -The value of (2Nd / S) may be calculated.
- the magnitude comparison circuit 60 calculates the calculation result of the arithmetic operation circuit 58 and the counting circuit 4 ⁇ . Compare the count value (Na + Nb). The comparison result is input to the polarity inversion circuit 44, and thereafter, the polarity inversion signal FRI is created and output by the polarity inversion circuit 44 in the same manner as in the first embodiment.
- the scanning electrode and the signal electrode are separated. Charge and discharge of electric charge to and from the formed capacitor can be minimized, and power consumption for driving the liquid crystal panel 10 can be reduced.
- the external polarity inversion control can be added similarly to the second embodiment.
- the EX-OR 50 shown by the dotted line in FIG. 8 is provided, the output of the polarity inversion circuit 44 (polarity inversion signal FRI) is input to one input terminal, and the other input terminal is connected to the other input terminal. Input the external polarity inversion signal FRA. Then, the output of EX-OR 50 may be used instead of the polarity inversion signal F RI output from the polarity inversion circuit 44.
- the power supply circuit 30 used in the liquid crystal display devices of the above-described first to fourth embodiments includes output terminals TC! Connected to the liquid crystal panel 10. There may be a capacitor between T5 and T5. In some cases, the power supply circuit 30 applies an output voltage by a voltage follower circuit using an arithmetic amplifier. In these cases, a part of the electric charge discharged from the liquid crystal panel 10 is accumulated in the capacitor in the power supply circuit 30. The manner in which the electric charge is stored varies depending on characteristics such as the capacitance of the capacitor in the power supply circuit 30 and the internal impedance, and characteristics such as the current discharging capability and the current absorbing capability of the operational amplifier.
- the power consumption tendency in the power supply circuit 30 with respect to Na, Nb. Ne. Nd described above may be different.
- the capacitance of the capacitor formed by the display dot of the liquid crystal panel 10 differs depending on whether or not the display dot is lit.
- the power consumption when the polarity is not inverted and when the polarity is inverted can be obtained as a function of Na, Nb, Nc, and Nd in experiments and the like.
- the first to fourth embodiments described above are performed. As with the liquid crystal display device of the example, the effect of reducing power consumption can be obtained.
- FIG. 9 is a diagram showing a detailed configuration of the power supply circuit 3 °.
- the power supply circuit 30 can have various configurations ⁇ FIG. 9 shows an example thereof.
- a power supply circuit 30 includes a voltage source 62 composed of a battery and an external power supply, five resistors 64, 66, 68, 70, 72 for dividing the voltage of the voltage source 62, and a voltage follower circuit. And operational amplifiers 74, 76, 78, 80 and five capacitors 82, 84, 86, 88, 90 that absorb inrush currents flowing into or out of terminals T0 to T5. And.
- the five giants 64, 66, 68, 70, and 72 are connected in series, and both ends of this series circuit are connected to the + and-terminals of the voltage source 62, respectively.
- the resistors 64, 66, 70, and 72 have a resistance value R
- the resistor 68 has a resistance value (k-4) R. Therefore, voltages V0 to V5 required for the six-level driving method appear at both ends of the series circuit of the five resistors 64, 66, 68, 70, and 72 and at a connection point between the resistors.
- Each of the four operational amplifiers 74, 76, 78, and 8 ° forms a voltage-hollow circuit as described above, and the voltage divided by the resistors 64, 66, 68, 70, and 72 is used as the voltage. Lower the impedance and output to terminals T1, T2, T3, and T4.
- the operational amplifier 74 has its non-inverting input terminal connected to the connection point between the resistors 64 and 66, and its inverting input terminal connected to the output terminal of the operational amplifier 74 itself. It is related to the child.
- the output terminal of the operational amplifier 74 is connected to the terminal T1.
- the operational amplifier 76 has its non-inverting input terminal connected to the connection point between the resistors 66 and 68, and its inverting input terminal connected to the output terminal of the operational amplifier 76 itself.
- the output terminal of the arithmetic and logic unit 76 is connected to the terminal T2.
- the operational amplifier 78 has a non-inverting input terminal connected to the connection point between the resistors 68 and 70, and an inverting input terminal connected to the output terminal of the operational amplifier 78 itself.
- the output terminal of the operational amplifier 78 is connected to the terminal T3.
- the operational amplifier 80 has its non-inverting input terminal connected to the connection point between the resistors 70 and 72, and its inverting input terminal connected to the output terminal of the operational amplifier 80 itself.
- the output terminal of the operational amplifier 80 is connected to the terminal T4.
- Each of the four operational amplifiers 74, 76, 78, and 80 has voltages V0 and V5 applied to the power supply terminal, and operates with these voltages.
- the five capacitors 82, 84, 86, 88, 90 are connected so as to connect each of the six terminals T0 to T5.
- all capacitors 82, 84, 86, 88, 90 have the same capacitance and impedance.
- the voltage VI appearing at the output terminal of the operational amplifier 74 is close to the drive voltage V0 of the operational amplifier 74. Therefore, the operational amplifier 74 has a small current discharge capability, and can flow only a small amount of current. Conversely, the voltage V4 appearing at the output terminal of the operational amplifier 80 is close to the drive voltage V5 of the operational amplifier 80. Therefore, the operational amplifier 80 has a low current sinking capability. When a current flows through the operational amplifier having a small suction capability, the rate of charging the capacitor connected to the output terminal of the operational amplifier increases, and the power consumption decreases.
- the amount of charge flowing from the capacitor created by this display dot to the operational amplifier 74 or 80 is Dot is lit and not lit When it changes to, it becomes larger than the amount of charge flowing from the capacitor made by the display dot to the operational amplifier 74 or 80.
- FIG. 10 is a diagram showing the configuration of the liquid crystal display device of the fifth embodiment.
- the liquid crystal display device shown in the figure includes a liquid crystal panel 1 °, an X driver 16, a Y driver 24, a power supply circuit 30, and a polarity inversion control circuit 92.
- the configuration other than the polarity inversion control circuit 92 is basically the same as that of the liquid crystal display device of the first embodiment shown in FIG.
- the polarity inversion control circuit 92 includes an address generation circuit 34, a storage element 36, four display state detection circuits 94, 96, 98, 100, and four counting circuits 1 0 2, 1 0 4, 1 06, 1 08, It is configured to include two arithmetic operation circuits 1 1 ⁇ , 1 1 2, a magnitude comparison circuit 1 14, and a polarity inversion circuit 44. Among them, four display state detection circuits 94, 96, 98, 100, four counting circuits 102, 104, 106, 108, two arithmetic operation circuits 1 1 ⁇ , 1 1 2, large and small Comparison circuit 1 14 The configuration is different from that of the embodiment, and these will be described in detail below.
- the display state detection circuit 94 and the counting circuit 102 are provided for obtaining the value Na described above.
- the display state detection circuit 94 sets the data DT corresponding to the immediately preceding scan electrode output from the storage element 36 to "1" indicating the lighting state, and the data of the currently input scan electrode. It detects that DT is "0" indicating a non-lighting state.
- the counting circuit 102 counts the detection result of the display state detection circuit 94, and is constituted by, for example, a counter.
- the detection result of the display state detection circuit 94 is input to the enable terminal of the counter constituting the counting circuit 102.
- This counter counts up in synchronization with the clock signal CK only when the display state detection circuit 94 detects that the display dot on the adjacent scanning electrode changes from the lighting state to the non-lighting state. .
- This count value is output from the counting circuit 1 • 2 as Na.
- this power supply is reset when a latch pulse LP is input.
- each of the display state detection times 96 and the counting circuit 104 are provided to obtain the value Nd described above.
- the counter in the counting circuit 104 counts up only when the display state detection circuit 96 detects that both the display dots on the adjacent scanning electrodes are in the non-lighting state. This count value is output from the counting circuit 104 as Nd.
- the display state detection circuit 98 and the counting circuit 106 are provided for obtaining the value Nc described above.
- the counter in the counting circuit 106 counts up only when the display state detection circuit 98 detects that both the display dots on the adjacent scanning electrodes are in the lighting state. This count value is output from the counting circuit 106 as N c.
- the display state detecting circuit 100 and the counting circuit 108 are provided for obtaining the value Nb described above. Only when the display state detection circuit 100 detects that the display dot on the adjacent scanning electrode changes from the non-lighting state to the lighting state, the counter in the counting circuit 108 counts up. This count value is output from the counting circuit 108 as N b.
- the arithmetic operation circuit 11 ° calculates the value of Nd ⁇ Na based on the count value (Na) of the counting circuit 102 and the count value (Nd) of the counting circuit 104.
- the arithmetic operation circuit 112 calculates the value of a (Nb-Nc) based on the count value (Nc) by the above-described counting circuit 106 and the count value (Nb) by the counting circuit 108 (
- the magnitude comparison circuit 114 performs magnitude comparison between the calculation result (Nd—Na) of the arithmetic operation circuit 110 and the calculation result a (Nb-Nc) of the arithmetic operation circuit 112. When the latter is large, the logic of the signal input from the magnitude comparison circuit 114 to the polarity inversion circuit 44 becomes "1".
- the polarity inversion circuit FRI is generated by the polarity inversion circuit 44 in the same manner as in the first embodiment.
- the driving method that determines whether to perform polarity reversal in consideration of the internal configuration of the power supply circuit 3 ⁇ , the charge and discharge of charges to and from the capacitor formed by the scanning electrode and the signal electrode are performed. It can be minimized, and the power consumption when driving the liquid crystal panel 10 can be reduced.
- the external polarity inversion control can be added similarly to the second embodiment.
- EX-OR 5 ° shown by the dotted line in Fig. 10 is provided, and the output of the polarity inversion circuit 44 (polarity inversion signal FR I) is input to one input terminal and the other input terminal is externally inverted. Input the signal FRA. Then, the output of EX-OR 5 ° may be used instead of the polarity inversion signal F RI output from the polarity inversion circuit 44.
- condition setting considering the asymmetry of the capability of the operational amplifier has been described.
- condition setting depending on the variation in the characteristics of the capacitor and the like can be similarly considered. .
- the liquid crystal display devices described in the first to fifth embodiments described above can be used by being incorporated in various electronic devices requiring display functions, and by reducing the power consumption of the liquid crystal display device.
- the power consumption of the entire electronic device in which the liquid crystal display device is incorporated can be reduced.
- the power supply circuit of the electronic device can be simplified, and the size and weight of the electronic device can be reduced.
- the capacity of the battery can be reduced, and when the same capacity battery is used, the electronic device can be operated for a long time.
- the liquid crystal display device of the seventh embodiment is characterized in that the polarity of the drive voltage applied to the liquid crystal panel is inverted in accordance with the pattern of characters, figures, etc. displayed on the liquid crystal panel. This point is the same as that of the above-described first embodiment and the like, but differs in that it enables the occurrence of display unevenness of the liquid crystal display device to be reduced.
- the liquid crystal display of this embodiment uses the IHAT method disclosed in Japanese Patent Application Laid-Open No. 5-46127. Hereinafter, the outline of the IHAT method will be described.
- a row electrode means a scanning electrode
- a column electrode means a signal electrode
- 0 corresponds to a display dot that does not light
- 1 corresponds to a display dot that lights
- k varies from 0 to (p-1) depending on the subgroup selected.
- the selection pattern of the row electrodes in the selected subgroup is
- the IHAT method is characterized in that it is driven in the following steps.
- a new row electrode selection pattern w 2 is selected, voltage of for column electrodes it is chosen in analogy to the procedure of (3) to (5), (6) and at the same time time columns and rows as well Apply voltage during T.
- all the selected patterns are successively selected for one sub-group, and then the process proceeds to the next sub-group. After the application of, the same processing may be performed by selecting the next selection pattern.
- the liquid crystal display device of the present embodiment is driven by the above-described IHAT method, and a case where the number of simultaneously selected scanning electrodes is 1 will be described as an example.
- the non-selection voltage is 0, the selection voltage is —V or + V, and the signal voltage is 1 V or + V. That is, when the selection voltage is + V, the lighting voltage is — v, and when the selection voltage is 1 V, the lighting voltage is + v. v, non-lighting voltage is -V.
- FIG. 11 is a diagram showing the configuration of the liquid crystal display device of the seventh embodiment.
- This liquid crystal display device has a polarity inversion control circuit 122, so that the polarity of the drive voltage applied to the liquid crystal panel 120 according to the pattern of characters, figures, etc. displayed by the liquid crystal display device 120. It is characterized in that AC driving is performed by reversing. By this polarity inversion, the occurrence of display unevenness on the liquid crystal panel 120 can be reduced.
- the liquid crystal display device shown in the figure has a liquid crystal panel 120 having a predetermined number of scanning electrodes and signal electrodes, an X driver 140 for applying a driving voltage to the liquid crystal panel 120, and a Y driver 148. And a power supply circuit 138 for generating a predetermined voltage, and a polarity inversion control circuit 122 for controlling the polarity inversion in accordance with the lighting state of the display dot on the liquid crystal panel 120.
- FIG. 12 is a diagram showing an example of a lighting state of each display dot in the liquid crystal panel 120 described above.
- the basic structure of the liquid crystal panel 120 is the same as that of the liquid crystal panel 10 of the first embodiment shown in FIG. In FIG. 12, the hatched display dots indicate that they are lit, and the other display dots indicate that they are not lit.
- the X-driver 140 applies lighting voltages and non-lighting voltages of -V and + V to the signal electrodes X1 to X6 of the liquid crystal panel 120, respectively.
- the X driver 140 includes a shift register circuit 142, a latch circuit 144, and a level shift circuit 146.
- the shift register circuit 142 converts the sequentially input six 1-bit data into 6-bit parallel data and outputs the data.
- the latch circuit 144 temporarily holds the 6-bit parallel data output from the shift register circuit 142, and has the same 6-bit capacity as the parallel data.
- the level shifter circuit 144 sets the voltage level according to each bit of the 6-bit data output from the latch circuit 144, and sets the voltage level for each signal electrode of the liquid crystal panel 120.
- the applied voltage is applied as lighting voltage or non-lighting voltage. Specifically, the lighting voltage and the non-lighting voltage are either 1 V or + V. Therefore, the level shifter circuit 146 appropriately selects one of these voltages and applies it to each signal electrode of the liquid crystal panel 120.
- the Y driver 148 applies a selection voltage or a non-selection voltage to each of the scanning electrodes Y1 to Y6 of the liquid crystal panel 12 °.
- ⁇ Driver 148 includes shift register circuit 150 and level shifter circuit 152
- the shift register circuit 150 has a 6-bit capacity, and shifts the input data signal DI in order in synchronization with the latch pulse signal L #. Therefore, data in which only one of the six bits is "1" is output, and the bit positions having this "1" are shifted in order.
- the level shift circuit 152 sets a voltage level according to each bit of the 6-bit parallel data output from the shift register circuit 150, and sets the voltage level for each scan electrode of the liquid crystal panel 120. Apply the voltage as a selection voltage or a non-selection voltage. Specifically, a voltage of 1 V or + V is applied as a selection voltage, and a voltage of 0 V is applied as a non-selection voltage. That is, when a non-selection voltage is applied, the scan electrode to which the non-selection voltage is applied is grounded.
- the power supply circuit 138 generates voltages of 1 V and + V as signal voltages, and voltages of 1 V and + V as scanning voltages, and applies these voltages to the X driver 14 ° and the ⁇ ⁇ driver 148, respectively. Specifically, the power supply circuit 138 supplies the voltages of —V and + V to the level shifter circuit 146 in the X driver 140 and supplies the voltages of 1 V and + V to the level shifter circuit 152 in the driver 148. I do.
- the polarity inversion control circuit 122 is configured to determine the number of display dots to be lit on the currently selected scan electrode and the number of the next display dot to be selected in accordance with the pattern of characters, figures, and the like displayed on the liquid crystal panel 120. The polarity of the signal voltage applied to the liquid crystal panel 120 and the polarity of the scanning voltage are switched based on the number of display dots lit on the scanning electrode.
- the polarity inversion control circuit 122 includes a counting circuit 124, a magnitude comparison circuit 126, a D-type flip-flop (D-FF) 128, an exclusive OR gate (EX-OR) 130, and a polarity inversion circuit 132. .
- the counting circuit 124 is for counting the number of display dots of the scanning electrode of interest in the lighting state. Specifically, it is composed of a counter.
- the latch pulse LP is input to the reset terminal of this counter, the clock signal C is input to the clock terminal, and the data DT is input to the enable terminal. Therefore, the counting circuit 124 is reset in synchronization with the latch pulse LP, and thereafter counts up in synchronization with the clock signal CK only when the data D is "1".
- the magnitude ratio circuit 126 compares the magnitude of a predetermined value (here, 3 which is half the number of signal electrodes of the liquid crystal panel 120) with the count value of the counting circuit 124.
- the D-FF 128 operates as a comparison result holding circuit, and holds the comparison result of the magnitude comparison circuit 126 in synchronization with the latch pulse LP.
- the EX-R 130 operates as an inversion condition determination circuit.
- the comparison result of the magnitude comparison circuit 126 is input to one input terminal, and the output Q of D-FF 128 is input to the other input terminal. . Since the D-FF 128 holds the comparison result of the display dot on the currently selected scan electrode, the EX-OR130 compares this comparison result with the display dot on the next selected scan electrode. It is determined whether or not the polarity should be inverted based on the comparison of ⁇ .
- the polarity inversion circuit 132 is composed of an EX-OR 134 and a D-FF 136, and the output of the D-FF 136 is inverted when the output of the EX-OR 130 is "1". It has become.
- the output of the T-F 136 is output from the polarity inversion control circuit 122 as a polarity inversion signal FRI, and is input to the level shifter circuit 146 in the X driver 140 and the level shifter circuit 152 in the Y driver 148.
- the following numbers M and N are defined, and whether to invert the polarity is determined based on these numbers and the total number S of the signal electrodes.
- I M-NI is the absolute value of the difference between the number of signal electrodes at which the voltage applied to the signal electrodes changes from the lighting voltage to the non-lighting voltage and the number of signal electrodes at which the voltage changes from the non-lighting voltage to the lighting voltage. That is, focusing on the unselected scan electrodes other than the two scan electrodes Yn and Yn + l described above, IM-NI is the sum of the voltage changes of the signal electrodes with respect to the non-selection voltage, and when this value is large, Causes a distortion in the voltage on the scan electrode according to this value.
- the polarity inversion control and control circuit 122 checks the lighting state of the display dot formed on the currently selected scan electrode Yn and the next selected scan electrode Yn + i on the liquid crystal panel 12 °. Then, the logic state of the polarity inversion signal FRI supplied to the X driver 140 and the Y driver 148 is switched according to the checked lighting state.
- the inversion control circuit 122 takes the display pattern of the liquid crystal panel 120 shown in FIG. A specific operation of the inversion control circuit 122 will be described.
- the basic operation of displaying a predetermined pattern on the liquid crystal panel 120 is the same as that of the first embodiment shown in FIG. 1, and therefore the description thereof will be omitted, and the polarity inversion control circuit 122 will be described in detail.
- the polarity inversion circuit 13 2 performs the polarity inversion when the scan electrode is switched according to the output of the EX-OR 130 as follows.
- the counting circuit 124 is reset in synchronization with the input latch pulse LP each time the selected scan electrode is switched. Then, the counting circuit 124 counts up only when the data DT input to the enable terminal in synchronization with the clock signal CK is "1" indicating the lighting state. Accordingly, when the data DT of the six signal electrodes is input, the counting circuit 124 outputs the number of display dots in the lighting state among the display dots on one scan electrode.
- the magnitude comparison circuit 126 determines that the count value of the counting circuit 124 is equal to the number S of the signal electrodes. If it is larger than half, "3", "1" is output as the comparison result. If it is smaller than "1", "0" is output as the comparison result.
- This comparison focus is taken into the D-FF 128 in synchronization with the latch pulse LP. Therefore, if the value output from the D-FF 128 is that of the currently selected scan electrode, the value output from the magnitude comparison circuit 126 is that of the next selected scan electrode. Will be.
- the EX-OR130 obtains the exclusive OR of the output of the D-FF 128 and the output of the magnitude comparison circuit 126. Therefore, one of the switching conditions (1) and (2) shown in Tables 5 and 6 is satisfied. That is, it is determined whether or not it has been performed.
- 13A to 13H are diagrams showing voltage waveforms applied to the respective electrodes when displaying the pattern shown in FIG. 12 on the liquid crystal panel 120 shown in FIG. 13A to 13F show voltage waveforms applied to the scan electrodes Y1 to Y6, respectively, and FIGS. 13G and 13A show voltage waveforms applied to the signal electrodes X2 and # 3, respectively. The voltage waveforms shown by solid lines in FIGS.
- 13G and 13 ⁇ ⁇ correspond to lighting voltages, and the voltage waveforms shown by dotted lines correspond to non-lighting voltages.
- t1 to t6 indicate the time during which the selection voltage is applied to the scan electrodes Y1 to Y6, respectively.
- the inversion condition is satisfied when the scan electrodes Y4 and Y6 are selected, so that the scan voltage and the scan voltage are synchronized in synchronization with the switching timing to these scan electrodes.
- the polarity inversion of the signal voltage is performed.
- the driving method for determining whether to perform polarity inversion according to the display content of the liquid crystal panel 120 it is possible to minimize the voltage distortion on the scanning electrodes and to generate display unevenness. Can be reduced.
- the case where the liquid crystal panel 120 is driven using the IHAT method has been described.
- the polarity inversion may be performed in exactly the same manner.
- the power supply circuit 138, the X driver 140, and the Y driver 148 used in the present embodiment use the power supply circuit 30, the X driver 16, and the Y driver 148 used in the first embodiment and the like. Must be replaced with driver 24. (Eighth embodiment)
- a forced polarity inversion control similar to the external polarity inversion control performed in the above-described second embodiment is added to the internal polarity inversion control performed in the seventh embodiment. It is characterized by doing.
- FIG. 14 is a diagram showing another example of the lighting state of each display dot in the above-described liquid crystal panel 12 °.
- the polarity inversion is not performed because the inversion condition is not always satisfied. Therefore, since the same non-lighting voltage is applied to the signal electrodes X1, X2, X4, X5, and X6, the display dots on each of these signal electrodes have a relatively low frequency component voltage. Will be applied.
- a non-lighting voltage and a lighting voltage are alternately applied to the signal electrode X3, a voltage having a relatively high frequency component is applied to the display dot on the signal electrode X3.
- the transmittance of each display dot of the liquid crystal panel 120 depends on the frequency component of the applied voltage, the transmittance of the display dot of the signal electrode X3 differs from that of the other signal electrodes. , Display unevenness occurs.
- the polarity inversion is forcibly performed at a certain period even when the inversion condition is not satisfied. Is what you do.
- FIG. 15 is a diagram showing a configuration of the liquid crystal display device of the present embodiment to which forced polarity inversion is added.
- the liquid crystal display device shown in the figure includes a liquid crystal panel 120, an X driver 140, a Y driver 148, a power supply circuit 138, and a polarity inversion control circuit 152.
- the configuration other than the polarity inversion control circuit 152 is basically the same as the liquid crystal display device of the seventh embodiment shown in FIG. Therefore, the description of the common part will be omitted, and the liquid crystal display device of the eighth embodiment will be described focusing on the polarity inversion control circuit 152 which is a different point.
- the polarity inversion control circuit 152 includes a counting circuit 124, a magnitude comparison circuit 126, a D-FF 128, an EX-OR 130, a periodic inversion circuit 154, and a polarity inversion circuit 156.
- a periodic inversion circuit 154 is interposed on the output side of the EX-OR 130. 11 in that the polarity inversion circuit 132 shown in FIG. 11 is replaced by a polarity inversion circuit 156.
- the periodic inversion circuit 154 is composed of a m-ary counter, and performs a counting operation in synchronization with the latch pulse LP.
- a carry signal is output from the periodic inversion circuit 154 at a rate of once.
- the polarity inversion circuit 156 is composed of an EX-OR 134, a D-FF 136, and an OR gate 158. At least one of the output of the EX-OR 130 and the output of the periodic inversion circuit 154 is "1". At one time, the output of D-FF 136 is inverted.
- the external polarity reversal control performed in the liquid crystal display device of the second embodiment described above is also for the purpose of forcible polarity reversal, and practically the present embodiment and the second embodiment are focused on. Is the same. Therefore, by replacing the EX-OR 50 of the second embodiment with a target, it is possible to cause the liquid crystal display device of the second embodiment to perform the same polarity inversion control as that of the present embodiment. Conversely, by replacing the OR gate 158 of this embodiment with EX-OR, it becomes possible to cause the liquid crystal display device of this embodiment to perform the same polarity inversion control as that of the second embodiment.
- the liquid crystal display device of the present embodiment performs polarity inversion only once when the inversion condition is satisfied a predetermined number of times in order to reduce display unevenness due to the above-described limitation of polarity inversion.
- FIG. 16 is a diagram illustrating the configuration of the liquid crystal display device of this embodiment in which the polarity inversion is restricted.
- the liquid crystal display device shown in FIG. 1 includes a liquid crystal panel 120, an X driver 140, a Y driver 148, a power supply circuit 138, and a polarity inversion control circuit 160.
- the configuration other than the polarity inversion control circuit 16 ° is basically the same as the liquid crystal display device of the seventh embodiment shown in FIG. Therefore, the description of the common part will be omitted, and the liquid crystal display device of the ninth embodiment will be described focusing on the difference, that is, the polarity inversion control circuit 16 °.
- the polarity inversion control circuit 160 includes a counting circuit 124, a magnitude comparison circuit 126, a D-FF 128, an EX-OR 130, an inversion limiting circuit 162, and a polarity inversion circuit 132. Compared with the polarity inversion control circuit 122 of the first embodiment shown in FIG. 11, the difference is that an inversion limiting circuit 162 is inserted between the EX-OR 130 and the polarity inversion circuit 132. .
- the inversion limiting circuit 162 is composed of an n-ary counter and performs a counting operation in synchronization with the latch pulse LP.
- the driving method that determines whether to perform polarity inversion according to the display content of the liquid crystal panel 12 ° is used, and a certain restriction is imposed on this polarity inversion, so that the voltage on the scanning electrode can be reduced. Distortion can be minimized, and display unevenness can be reduced.
- the presence or absence of the polarity inversion is determined depending on whether or not the inversion condition is satisfied. Therefore, depending on the content of the display on the liquid crystal panel 120, the inversion condition may or may not be satisfied each time the selected scanning electrode changes. Then, the polarity inversion is frequently performed. This polarity reversal reduces display unevenness on the entire display screen. Locally, a situation may occur when a previously dark portion suddenly becomes slightly brighter. Considering that human vision is insensitive to slow changes in brightness, but sensitive to rapid changes in brightness, the above-described rapid changes in brightness can cause partial display unevenness. It is the same as the occurrence, which will lower the display quality of the product.
- the frequency of the polarity inversion is set stepwise according to the number of times the inversion condition is satisfied within a predetermined period. Is changed. That is, for example, by shortening the period of polarity reversal when the number of times the reversal condition is satisfied during one frame period increases, the polarity reversal becomes almost equivalent to reversal of polarity when the reversal condition is satisfied discretely. Focusing on this, the frequency of the polarity inversion is changed stepwise according to the number of times that the inversion condition is satisfied within a predetermined frame period.
- FIG. 17 is a diagram showing the configuration of the liquid crystal display device of the present embodiment in which the frequency of polarity inversion is changed stepwise.
- the liquid crystal display device shown in FIG. It includes a driver 140, a ⁇ driver 148, a power supply circuit 138, and a polarity reversal control circuit 164.
- the configuration other than the polarity inversion control circuit 164 is basically the same as that of the liquid crystal display device of the seventh embodiment shown in FIG. Therefore, the description of the common part will be omitted, and the liquid crystal display device of the first embodiment will be described focusing on the polarity inversion control circuit 164 which is different from the first embodiment.
- the polarity inversion control circuit 164 includes a counting circuit 124, a magnitude comparing circuit 126, a D-FF 128, an EX-OR 130, a counting circuit 166, a counting and holding circuit 168, 170, 172, an average value calculating circuit 174, and a look-up. It comprises a table 176, a counting circuit 178, a matching detection circuit 180, and a polarity reversing circuit 182.
- the polarity inversion control circuit 122 of the seventh embodiment shown in FIG. 11 whether the inversion condition is satisfied by the counting circuit 124, the magnitude comparison circuit 126, the D-FF 128, and the EX-OR 130 The determination is the same, but the detailed operation of the subsequent polarity inversion processing is different.
- the counting circuit 166 is configured by a counter, and counts up in synchronization with the latch pulse LP when the output of the OR 13 ° input to the enable terminal is “1”. When the data signal DI is "1”, the signal is reset in synchronization with the latch pulse LP.
- the three count holding circuits 168, 170, and 172 take in and hold the data DT in synchronization with the latch pulse LP when the data-in signal DI is "1".
- the count holding circuit 168 takes in the count value output from the counting circuit 166 as data.
- the count holding circuit 170 captures the data held in the count holding circuit 168.
- the count holding circuit 172 takes in the data held in the count holding circuit 170.
- the average value calculation circuit 174 receives the respective data held in the count holding circuits 168, 170, 172 and calculates the average value of the three data. If the count holding circuits are provided in multiple stages, instead of calculating the average of the outputs of all the count holding circuits, for example, the count holding circuits located at regular intervals may be used. The average of only the output may be calculated.
- the weight of the data of the count and hold circuit 168 is 1, the weight of the data of the count and hold circuit 17 ° is 2, and the count and hold are performed.
- the weight of the data of the circuit 17 2 may be set to 3.
- the input data of the counting and holding circuit 172 is used as the average value of the data held by the counting and holding circuit 1668 and 170, and the average value of the counting and holding circuit 1668, 170 and 172 is obtained. It may be a two-stage circuit.
- the look-up table 176 receives the average value calculated by the average value calculation circuit 174, and outputs predetermined data corresponding to the average value on a one-to-one basis.
- the data output from the look-up table 176 is set to decrease as the average value input increases.
- This look-up table 176 is composed of, for example, ROM.
- the counting circuit 178 is composed of a counter and counts up in synchronization with the latch pulse LP. Then, the counting circuit 178 is reset in synchronization with the latch pulse L # according to the coincidence detection signal output from the coincidence detection circuit 180.
- the match detection circuit 180 compares the data output from the look-up table 176 with the count value of the counting circuit 178. If they match, the above-mentioned match detection signal is output.
- the polarity inversion circuit 18 2 is composed of, for example, a D-FF.
- a match detection signal is output from the match detection circuit 180 (when the logic of the output signal is “1”), a latch pulse is output.
- the inverted output of this D-FF is taken in synchronization with LP.
- this polarity inversion circuit 18 2 can be composed of a single D-FF with inverted output as shown in Fig. 17 ⁇ As shown, it can be constructed by combining D-FF and EX-HIR.
- the counting circuit 1666 counts up when the output power of the EX-OR 13 0 is “1”, that is, when the inversion condition is satisfied. Reset by DI. Therefore, the counting circuit 1666 counts the number of times where the inversion condition is satisfied in one frame period.
- the count holding circuit 1668 holds the number of inversion conditions satisfied in one frame period counted by the counting circuit 166.
- the count holding circuit 17 # holds the number for which the inversion condition has been satisfied in the immediately preceding frame period.
- the count holding circuit 17 2 holds the number for which the inversion condition has been satisfied in the immediately preceding frame period.
- the average value calculation circuit 174 calculates and outputs the average value of the numbers for which the inversion condition is satisfied in each of these three frames.
- Look-up table 176 outputs a predetermined value corresponding to the average value output from average value calculation circuit 174. Specifically, the look-up table 176 outputs a small value when the input average value is large.
- the counting circuit 178 is reset by the coincidence detection signal output from the coincidence detection circuit 180, and its count value is set to “ ⁇ ”.
- the counting circuit 178 operates as a (m + 1) -base counter, where m is a numerical value output from the lookup table 176. Therefore, when the latch pulse LP force is output ⁇ (m + 1) times, the coincidence detection signal output from the coincidence detection circuit 180 becomes "1".
- the polarity inversion circuit 182 inverts the logic of the polarity inversion signal FRI in order to perform one polarity inversion when the latch pulse LP force (m + 1) is output.
- the polarity inversion control circuit 164 of the liquid crystal display device of the present embodiment reduces the cycle of inverting the logic of the polarity inversion signal FRI when the number of times the inversion condition is satisfied in one frame period increases. Therefore, the number of polarity inversions in one frame period increases.
- the cycle of the inversion of the polarity inversion signal FRI changes with the average of the number of times that the inversion condition of a plurality of frames is satisfied, so even if the display content changes suddenly, the inversion of the logic of the polarity inversion signal FRI gradually increases.
- the liquid crystal display device of the present embodiment is configured to simultaneously select L scanning electrodes (L ⁇ 2) It is characterized by reducing display unevenness when a scanning electrode is selected.
- each row corresponds to a scanning electrode.
- “1 V” and “+ V” indicate scan electrodes to which a selection voltage is applied, and “0” indicates scan electrodes to which a non-selection voltage is applied.
- each column corresponds to a time change of the application state of the selection voltage or the non-selection voltage to each scanning electrode.
- the combination of the scanning voltages shown in the figure shows that the sum of the squares of each element of each column vector of the matrix is the same for all column vectors, and that the correspondence of the two different column vectors Are combined so that the sum of the products of the elements is zero. That is, the row vectors are combined so as to be orthogonal.
- a sequential selection voltage is applied to the scan electrodes based on the combinations set in the above-described matrix. Specifically, first, a selection voltage is applied to the L scanning electrodes in the combination indicated by the row vector in the first row of the matrix. Next, a selection voltage is applied to the next L scan electrodes in the combination indicated by the row vector in the second row. The application of the selection voltage in units of L scan electrodes is performed up to the row vector in the bottom row of the matrix, and then returns to the row vector in the first row.
- the lighting voltage or the non-lighting voltage is applied to each signal electrode in parallel with the application of the selection voltage. Specifically, a lighting voltage or a non-lighting voltage applied to each signal electrode is set as described below.
- FIG. 19 is a diagram showing the configuration of the liquid crystal display device of the eleventh embodiment.
- the liquid crystal display device shown in the figure has a liquid crystal panel 19 ⁇ having a predetermined number of scanning electrodes and signal electrodes, an X driver 21, which applies a driving voltage to the liquid crystal panel 190, and a Y driver 21. 8; a power supply circuit 2 ⁇ 8 for generating a predetermined voltage; and a polarity reversal control circuit 1992 for controlling polarity reversal according to the lighting state of the display dot of the liquid crystal panel 19 ⁇ .
- FIG. 20 is a diagram showing an example of a lighting state of a display dot in the above-described liquid crystal panel 19 °.
- the basic structure of the liquid crystal panel 190 is the same as that of the liquid crystal panel 120 of the seventh embodiment shown in FIG. In FIG. 20, the hatched display dots indicate that they are lit, and the other display dots indicate that they are not lit.
- the oX driver 210 is composed of a shift register circuit 212, a latch circuit 214, and a level shifter circuit 214.
- the shift register circuit 212 has a capacity of 2 ⁇ 6 bits, and shifts sequentially input 2-bit data by six. Each of the 2-bit data indicates whether the display dot formed by the corresponding signal electrode and the two scanning electrodes is in a lighting state or a non-lighting state.
- the latch circuit 214 holds each of the six 2-bit data output from the shift register circuit 212 at the time, and has a capacity of 2 ⁇ 6 bits, which is the same as these data. Yes.
- the level shift circuit 216 sets the voltage level according to each of the six 2-bit data output from the latch circuit 214, and sets this voltage level for each signal voltage of the liquid crystal panel 190. Apply the set voltage as lighting voltage or non-lighting voltage. Specifically, since the lighting voltage and the non-lighting voltage are any of —V, 0, and + v, the level shifter circuit 216 selects one of these voltages as appropriate and selects the liquid crystal panel 1 90 is applied to each signal electrode.
- the Y driver 218 applies a selection voltage or a non-selection voltage to each of the scanning electrodes Y1 to Y6 of the liquid crystal panel 190.
- L 2
- the driver 218 includes a shift register circuit 220, a latch circuit 222, and a level shift circuit 224.
- the shift register circuit 220 has a capacity of 2 ⁇ 6 bits, and shifts sequentially input 2-bit data in order of six values.
- the 2-bit data indicates the contents of the selection voltage applied to the two scanning electrodes selected at the same time. For example, “10” corresponds to + V, and "01" corresponds to -V. I have. “00” corresponds to 0 V which is a non-selection voltage.
- the latch circuit 222 temporarily holds each of the six 2-bit data output from the shift register circuit 220, and has the same capacity of 2 ⁇ 6 bits as these data. . -
- the level shift circuit 224 sets a voltage level according to each of the six 2-bit data output from the latch circuit 222, and transfers one of two selection voltages and one non-selection voltage to the liquid crystal panel. Apply to 190.
- the power supply circuit 2 ⁇ 8 applies a voltage of 1 V, 0, + V to the X driver 210 as a signal voltage, and applies a voltage of 1 V, 0, + V to the Y driver 218 as a scanning voltage.
- the polarity inversion control circuit 192 is a signal for inverting the polarity when two scan electrodes that are simultaneously selected are switched according to the pattern of characters and figures displayed on the liquid crystal panel 190.
- the sum of the change in the voltage of the electrode and the sum of the change in the voltage of the signal electrode in the case where the polarity inversion is not performed are compared. As a result, it is possible to suppress the distortion of the voltage generated on each scanning electrode other than the selected scanning electrode, and to reduce the display unevenness.
- the polarity inversion control circuit 192 includes an upper data counting circuit 194, a lower data counting circuit 196, an upper counting value holding circuit 198, a lower counting value holding circuit 20 °, a non-inverting operation circuit 202, an inversion operation circuit 204, and a magnitude comparison circuit. It comprises a circuit 206 and a polarity inversion circuit 132.
- the high-order data counting circuit 194 is reset in synchronization with the latch pulse L #, and performs a counting operation in synchronization with the clock signal CK only when the high-order bit of the input 2-bit data DT is "1". Do. Similarly, the lower data counting circuit 196 is reset in synchronization with the latch pulse L #, and only when the lower bit power of the input 2-bit data DT is "1", the clock signal CK Performs counting operation in synchronization with.
- the high-order count value holding circuit 198 is composed of a plurality of bits (three bits in this embodiment) of D-FF, and the count result of the high-order data count circuit 194 is synchronized with the latch pulse L #. And hold it.
- the lower count value holding circuit 200 is composed of a plurality of bits of D-FF, and captures and holds the count result by the lower data count circuit 196 in synchronization with the latch pulse L #.
- the non-inverting operation circuit 202 is constituted by using, for example, a gate array, and each of the counting result of the upper data counting circuit 194 and the lower data counting circuit 196 and the upper counting value holding circuit 19 8.
- the inversion operation circuit 204 is configured using, for example, a gate array, and the counting results of the upper data counting circuit 194 and the lower data counting circuit 196 and the upper counting value holding circuit 1 9 8, Based on the contents held in the lower count value holding circuit 200, calculate the sum of the voltage changes of the signal electrodes when the polarity is inverted.
- Each of the calculation results of the non-inversion operation circuit 202 and the inversion operation circuit 204 is input to the size comparison circuit 206, and the two calculation results are compared in magnitude.
- the magnitude comparison circuit 206 sets the logic of the output signal to "1" when the calculation result of the non-inversion operation circuit 202 is larger than the calculation result of the inversion operation circuit 204. In the opposite case, the output signal logic is " ⁇ ".
- the polarity inverting circuit 13 based on the comparison result by the magnitude comparing circuit 206, specifically, when the logic of the output signal of the magnitude comparing circuit 206 is “1”, the polarity inverting signal FRI Is inverted.
- the polarity inversion circuit 1332 itself is the same as that of the seventh embodiment shown in FIG. 11, and is composed of EX-OR13 and 0-F136.
- each row shows the state of the selection voltage applied to the scanning electrode
- each column shows the time change of the application state of the scanning voltage.
- two scanning electrodes of the liquid crystal panel 190 are sequentially selected.
- a selection voltage of 1 V is applied to the scanning electrode Y1
- a selection voltage of + V is applied to the scanning voltage Y2
- non-selection voltages are applied to the other scanning electrodes Y3 to Y6.
- Apply 0 V Similarly, select voltages of 1 V and + V are applied to Y 3 and Y 4, and then applied to Y 5 and Y 6.
- Select voltage + V and 1V are applied to Y1 and Y2, ⁇ 3 and ⁇ 4, ⁇ 5 and ⁇ 6, respectively.
- the product of the display state of the display dot and the state of the selected voltage of the scan electrode forming this display dot is calculated.
- the sum of the products is calculated. It looks like 1 ⁇ 3.
- the sum of the above-mentioned products is the same for the signal electrodes XI and ⁇ 6, and the same for all the signal electrodes X2 to ⁇ 5. For this reason, it is assumed that calculation is performed for the signal electrodes X1 and ⁇ 2.
- the inversion vector when the inversion vector is not used (when the polarity is not inverted), when the selection voltage is applied to the scan electrodes Y1 and Y2 in the first frame, the signal electrodes X2 to The sum for X5 is ⁇ .
- the selection voltage is applied to the scan electrodes Y3 and Y4 in the first frame, the sum of the signal electrodes X2 to X6 is 2. Therefore, when the selected scanning electrode switches from Y1 and Y2 to Y3 and Y4, a voltage change corresponding to the total change “2” occurs at the signal electrodes X2 to X5. That is, in the entirety of the signal electrodes X2 to X5, the total of the change in the voltage of each signal electrode is four times the total change “2”.
- the polarity inversion is performed by using the inversion vector.
- the polarity inversion control is performed when the sum is smaller than the above-mentioned sum.
- N2 Number of signal electrodes where signal voltage changes from + v to 0 ⁇ ⁇
- N 7 Number of signal electrodes where signal voltage changes from 1 V to + V
- N8 Number of signal electrodes where signal voltage changes from 1 V to 0 V
- N 9 Number of signal electrodes that maintain the signal voltage at -V
- N1 to N9, MU, ML, NU, and NL are also as follows.
- N 1 Number of signal electrodes whose signal voltage changes from + V to 1 V
- the absolute value difference between the total amount of signal voltage change without polarity reversal (MU—ML— ⁇ + NL) and the total amount of signal voltage change without polarity reversal (MU—ML + NU-NL) can be calculated by counting ⁇ , ML, NU, NL.
- the absolute value of the total change in signal voltage ( ⁇ — ML— NU + NL) when the polarity is not inverted is referred to as “the amount of change when non-inverted”, and the total amount of change in the signal voltage when the polarity is inverted (MU— The absolute value of ML + ⁇ —NL) is called “fluctuation at reversal”.
- FIG. 22 is a diagram illustrating the operation timing of the liquid crystal display device of the present embodiment.
- the operation B of the liquid crystal display device shown in FIG. 19 will be described in detail with reference to FIG. 22.
- the shift register circuit 212 in the X driver 210 is reset in synchronization with the falling edge of the latch pulse LP. After that, in synchronization with the falling edge of the clock signal CK, each of them takes in 2 bits of data DT.
- the fetched data DT is sequentially shifted in 2-bit units in synchronization with the clock signal CK.
- the shift register circuit 212 captures the same number of 2-bit data as the number of signal electrodes 6 of the liquid crystal panel 190, the shift register circuit 212 receives the same signal as the latch pulse LP.
- the latch circuit 214 that operates in anticipation takes in and holds 2-bit data corresponding to each signal electrode stored in the shift register circuit 212.
- the level shift circuit 216 selects one of V, 0, and + V according to the 2-bit data held in the latch circuit 214 and the logic state of the polarity inversion signal FRI input from the polarity inversion control circuit 192 at this time.
- the lighting voltage or the non-lighting voltage is applied to each signal electrode of the liquid crystal panel 190. Specifically, when the logic of the polarity inversion signal FRI is “0” and the higher order of the two-bit data held in the latch circuit 214 is “1”, the level shifter circuit 216 outputs + v If the lower order of the 2-bit data is "1”, the voltage is 1 V. If both bits of the 2-bit data are both "0", the voltage is 0 V. Is applied.
- the level shifter circuit 216 outputs a voltage of 1 V when the logic of the polarity inversion signal FRI is “1” and the higher order of the 2-bit data held in the latch circuit 214 is “1”.
- a voltage of + V is applied.
- both bits of the two-bit data are both "0"
- a voltage of 0 V is applied.
- the shift register circuit 220 in the Y driver 218 synchronizes with the clock signal CK and outputs two-bit scan data DY for determining two scanning electrodes to be selected. take in.
- the fetched scanning data DY is sequentially shifted in units of 2 bits in synchronization with the clock signal CK.
- the latch circuit 222 that operates in synchronization with the latch pulse LP includes a shift register circuit 220. It captures and stores 2-bit data corresponding to each scan electrode stored at 22 °.
- the level shifter circuit 224 determines whether or not the V and + V are to be output in accordance with the 2-bit data held in the latch circuit 222 and the logic state of the polarity inversion signal FRI input from the polarity inversion control circuit 192 at this time.
- the selection voltage or the non-selection voltage of 0 V, L is applied to each scanning electrode of the liquid crystal panel 190.
- the logic of the polarity inversion signal FRI is "0" and the latch circuit
- the selection voltage of + V is set.
- the selection voltage of -V is set.
- a selection voltage of 1 V is applied to the scanning electrode Y1
- a selection voltage of + V is applied to the scanning electrode Y2
- a selection voltage of 0 V is applied to the other scanning electrodes.
- the scanning electrodes 1 V and + V are set to 1 and +1 respectively
- the lit and non-lit display dots are set to 1 1 and +1 respectively.
- the polarity inversion control circuit 192 determines whether to perform polarity inversion in parallel with such a basic display operation, and inverts the logic of the polarity inversion signal FRI when performing polarity inversion.
- the detailed operation of the polarity inversion control circuit 192 is as follows.
- the high-order data counting circuit 194 is reset in synchronization with the latch pulse LP, and counts up only in the case of the high-order bit data of the data DT in synchronization with the clock signal CK. Therefore, when six 2-bit data DT corresponding to all the signal electrodes are input, the upper data counting circuit 194 determines the number of data DTs whose upper bits are "1", that is, the value ⁇ . Output as a count value. Similarly, the lower data counting circuit 196 outputs ML as a count value. Next, the upper count value holding circuit 198 captures and holds the count value of the upper data count circuit 194 in synchronization with the latch pulse LP.
- the upper count value holding circuit 198 takes in the value MU output as the count value and holds it as the value NU.
- the lower count value holding circuit 200 takes in the count value (value ML) of the lower data count circuit 196 and holds it as a value NL.
- the non-inversion operation circuit 202 converts the values MU, ML, NU, and NL output from the upper data counting circuit 194, the lower data counting circuit 196, the upper counting value holding circuit 198, and the lower counting value holding circuit 200.
- MU-ML + NU- NL is calculated based on the absolute value and the non-reversal fluctuation is output.
- the inversion operation circuit 204 calculates the absolute value of MU ⁇ ML ⁇ NU + NL and outputs the amount of change during inversion.
- the magnitude comparison circuit 206 receives the non-inversion fluctuation amount output from the non-inversion operation circuit 2 ⁇ 2 and the inversion fluctuation amount output from the inversion operation circuit 204 and receives these two inputs. Performs a magnitude comparison of values. Then, when the fluctuation amount at the time of non-inversion is larger than the fluctuation amount at the time of inversion, the comparison result is output as "1". When the comparison result of the magnitude comparison circuit 206 is “1”, the polarity inversion circuit 132 changes the logic of the polarity inversion signal FRI from “1” to “0” in synchronization with the latch pulse LP, or Inverts to "1".
- the polarity inversion control circuit 192 performs the polarity inversion when the selected scan electrode is switched, when the total of the fluctuations in the voltage of the signal electrode is smaller when the polarity is inverted, and when the sum is larger, the polarity is inverted. Control not to invert the polarity.
- the sum of the differences between the voltage changes of each signal electrode is minimized. Therefore, voltage distortion on the scanning electrodes can be minimized, and display unevenness can be reduced.
- liquid crystal display devices described in the seventh to eleventh embodiments described above can be used by being incorporated in various electronic devices having a display function.
- electronic devices include a personal computer, a word processor, an electronic organizer, a work station, and the like, and the liquid crystal display device of the present invention is used as these display devices. If this is the case, display unevenness is small and high-quality display is possible.
- the present invention is, of course, not limited to the above-described embodiment.
- the case where forced reversal control is used together is described, and in the ninth embodiment, the case where the polarity reversal is restricted is described. It may be used in combination with other embodiments.
- the present invention by performing the polarity inversion control according to the display pattern of the liquid crystal panel using the polarity inversion control circuit, power consumption can be reduced, and display unevenness can be reduced. The occurrence can be suppressed.
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69320438T DE69320438T2 (de) | 1992-05-14 | 1993-05-14 | Flüssigkristallanzeigeeinheit und elektronisches gerät unter verwendung dieser einheit |
EP93910342A EP0597117B1 (en) | 1992-05-14 | 1993-05-14 | Liquid crystal display and electronic equipment using the liquid crystal display |
US08/170,355 US5576729A (en) | 1992-05-14 | 1993-05-14 | Liquid crystal display device and electronic equipment using the same |
JP52006093A JP3531164B2 (ja) | 1992-05-14 | 1993-05-14 | 液晶表示装置及びそれを用いた電子機器 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12214192 | 1992-05-14 | ||
JP4/122141 | 1992-05-14 | ||
JP24222792 | 1992-09-10 | ||
JP4/242227 | 1992-09-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1993023845A1 true WO1993023845A1 (en) | 1993-11-25 |
Family
ID=26459332
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1993/000639 WO1993023845A1 (en) | 1992-05-14 | 1993-05-14 | Liquid crystal display and electronic equipment using the liquid crystal display |
Country Status (5)
Country | Link |
---|---|
US (1) | US5576729A (ja) |
EP (1) | EP0597117B1 (ja) |
JP (1) | JP3531164B2 (ja) |
DE (1) | DE69320438T2 (ja) |
WO (1) | WO1993023845A1 (ja) |
Cited By (3)
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CN100356424C (zh) * | 2004-11-03 | 2007-12-19 | 东南大学 | 等离子体显示屏的功耗自动调整装置及方法 |
US7382343B2 (en) | 1998-10-27 | 2008-06-03 | Sharp Kabushiki Kaisha | Display panel driving method, display panel driver circuit, and liquid crystal display device |
WO2008139504A1 (ja) * | 2007-04-27 | 2008-11-20 | Fujitsu Limited | 表示装置の駆動方法及び表示装置 |
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GB9302997D0 (en) * | 1993-02-15 | 1993-03-31 | Secr Defence | Multiplex addressing of ferro-electric liquid crystal displays |
US5528256A (en) * | 1994-08-16 | 1996-06-18 | Vivid Semiconductor, Inc. | Power-saving circuit and method for driving liquid crystal display |
JPH0876093A (ja) * | 1994-09-08 | 1996-03-22 | Texas Instr Japan Ltd | 液晶パネル駆動装置 |
US6229515B1 (en) * | 1995-06-15 | 2001-05-08 | Kabushiki Kaisha Toshiba | Liquid crystal display device and driving method therefor |
JP3417514B2 (ja) * | 1996-04-09 | 2003-06-16 | 株式会社日立製作所 | 液晶表示装置 |
JPH09325319A (ja) * | 1996-06-07 | 1997-12-16 | Sharp Corp | 単純マトリクス型液晶表示装置およびその駆動回路 |
EP1583071A3 (en) * | 1998-02-09 | 2006-08-23 | Seiko Epson Corporation | Electrooptical apparatus and driving method therefor, liquid crystal display apparatus and driving method therefor, electrooptical apparatus and driving circuit therefor, and electronic equipment |
EP0990940A4 (en) | 1998-02-23 | 2002-10-23 | Seiko Epson Corp | METHOD FOR CONTROLLING AN ELECTRO-OPTICAL DEVICE, CIRCUIT FOR CONTROLLING AN ELECTRO-OPTICAL DEVICE, ELECTRO-OPTICAL DEVICE AND ELECTRONIC DEVICE |
JP3412131B2 (ja) * | 1998-06-23 | 2003-06-03 | 株式会社日立製作所 | 液晶表示装置 |
US6587145B1 (en) * | 1998-08-20 | 2003-07-01 | Syscan Technology (Shenzhen) Co., Ltd. | Image sensors generating digital signals from light integration processes |
KR100870018B1 (ko) * | 2002-06-28 | 2008-11-21 | 삼성전자주식회사 | 액정 표시 장치 및 그 구동 방법 |
JP4754166B2 (ja) * | 2003-10-20 | 2011-08-24 | 富士通株式会社 | 液晶表示装置 |
KR101209039B1 (ko) * | 2005-10-13 | 2012-12-06 | 삼성디스플레이 주식회사 | 액정 표시 장치의 구동 장치 및 이를 포함하는 액정 표시장치 |
JP4943505B2 (ja) | 2007-04-26 | 2012-05-30 | シャープ株式会社 | 液晶表示装置 |
WO2008139695A1 (ja) * | 2007-04-27 | 2008-11-20 | Sharp Kabushiki Kaisha | 液晶表示装置 |
CN101750765B (zh) * | 2008-12-18 | 2011-12-28 | 北京京东方光电科技有限公司 | 液晶显示器公共电极线断线不良的检测方法 |
CN102930843B (zh) * | 2012-10-31 | 2015-04-29 | 旭曜科技股份有限公司 | 源极驱动装置和平面显示器 |
JP6270411B2 (ja) * | 2013-10-25 | 2018-01-31 | シャープ株式会社 | 表示装置、電子機器、および表示装置の制御方法 |
TWI521496B (zh) * | 2014-02-11 | 2016-02-11 | 聯詠科技股份有限公司 | 緩衝電路、面板模組及顯示驅動方法 |
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JPH0546127A (ja) * | 1991-08-16 | 1993-02-26 | Asahi Glass Co Ltd | 液晶表示素子の駆動法 |
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- 1993-05-14 WO PCT/JP1993/000639 patent/WO1993023845A1/ja active IP Right Grant
- 1993-05-14 DE DE69320438T patent/DE69320438T2/de not_active Expired - Fee Related
- 1993-05-14 EP EP93910342A patent/EP0597117B1/en not_active Expired - Lifetime
- 1993-05-14 US US08/170,355 patent/US5576729A/en not_active Expired - Lifetime
- 1993-05-14 JP JP52006093A patent/JP3531164B2/ja not_active Expired - Lifetime
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JPS6231825A (ja) * | 1985-08-02 | 1987-02-10 | Hitachi Ltd | 液晶表示装置用駆動回路 |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7382343B2 (en) | 1998-10-27 | 2008-06-03 | Sharp Kabushiki Kaisha | Display panel driving method, display panel driver circuit, and liquid crystal display device |
CN100356424C (zh) * | 2004-11-03 | 2007-12-19 | 东南大学 | 等离子体显示屏的功耗自动调整装置及方法 |
WO2008139504A1 (ja) * | 2007-04-27 | 2008-11-20 | Fujitsu Limited | 表示装置の駆動方法及び表示装置 |
JPWO2008139504A1 (ja) * | 2007-04-27 | 2010-07-29 | 富士通株式会社 | 表示装置の駆動方法及び表示装置 |
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JP4992969B2 (ja) * | 2007-04-27 | 2012-08-08 | 富士通株式会社 | 表示装置の駆動方法及び表示装置 |
Also Published As
Publication number | Publication date |
---|---|
JP3531164B2 (ja) | 2004-05-24 |
EP0597117A4 (en) | 1994-12-07 |
EP0597117B1 (en) | 1998-08-19 |
DE69320438D1 (de) | 1998-09-24 |
DE69320438T2 (de) | 1999-03-18 |
EP0597117A1 (en) | 1994-05-18 |
US5576729A (en) | 1996-11-19 |
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