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WO1993011561A1 - Procede de fabrication d'un circuit integre de puissance ayant un composant vertical de puissance - Google Patents

Procede de fabrication d'un circuit integre de puissance ayant un composant vertical de puissance Download PDF

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Publication number
WO1993011561A1
WO1993011561A1 PCT/DE1992/000955 DE9200955W WO9311561A1 WO 1993011561 A1 WO1993011561 A1 WO 1993011561A1 DE 9200955 W DE9200955 W DE 9200955W WO 9311561 A1 WO9311561 A1 WO 9311561A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
vertical power
etching
control circuit
producing
Prior art date
Application number
PCT/DE1992/000955
Other languages
German (de)
English (en)
Inventor
Helmut Gassel
Bernward MÜTTERLEIN
Holger Vogt
Günther Zimmer
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE4201910A external-priority patent/DE4201910C2/de
Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority to EP92923661A priority Critical patent/EP0614573A1/fr
Publication of WO1993011561A1 publication Critical patent/WO1993011561A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats

Definitions

  • the present invention relates to a method for producing an integrated power circuit with a vertical power component and a control circuit for driving the vertical power component. Furthermore, the present invention relates to a method for producing an integrated power circuit with at least two vertical power components.
  • Integrated circuits with a power component and a control circuit for driving the power component have been known as "intelligent power semiconductor circuits 11" to the person skilled in the art under the term “smart power” for several years.
  • JP Mille A very high voltage technology (up to 1200 V) for vertical smart power ICs, Proceedings of the Symposium on High Voltage and Smart Power ICs, volume 89-15, pages 517 to 525, 1989; and K.Owyang, functional integration for power components, microelectronics, 4: 252- 254, 1990.
  • the power component is usually isolated from the control circuit by a pn junction.
  • latch-up there is a risk of so-called "latch-up".
  • a fundamental disadvantage of SOI technology is that an undesirable control effect of the substrate cannot be avoided.
  • the substrate acts via the buried insulator like a second gate electrode on transistors that are integrated in the film. If potential differences occur between the substrate and the film, this can lead to threshold voltage shifts and to changes in the switching state of the transistors, as described in the following specialist publication: K. Yallup, B. Lanc and S. Edwards, Back gate effects in thick film SOI CMOS devices, IEEE International SOI Conference, pages 48 to 49, 1991.
  • a method for producing an isolated, single-crystalline silicon island is already known from WO 91/13463, which is insulated from the underlying substrate by a buried silicon dioxide layer and by trenches in the lateral direction.
  • a gas sensor element is integrated within the silicon island.
  • EP-0150827A2 Semiconductor structures are known from EP-0150827A2 and from EP-0444370A1, in which a part of the semiconductor material is removed by an anisotropic etching process.
  • this anisotropic etching process is used to structure a pressure sensor with a silicon membrane.
  • EP-0444370A1 discloses the production of a buried dielectric layer by means of wafer bonding, which serves as an etching stop layer for producing the recess by the anisotropic etching process. Neither of these two documents deals with the production of vertical power components.
  • the present invention is based on the object of specifying a method for producing an integrated circuit with a vertical power component and a control circuit, by means of which influences of switching operations of the vertical power component on the control circuit are avoided.
  • the invention is based on the above-
  • the prior art is based on the object of specifying a method for producing an integrated circuit with at least two vertical power components, in which influences of switching operations of a vertical power component on another vertical power component are avoided.
  • FIG. 1 shows a cross-sectional illustration of a first embodiment of an integrated power circuit with vertical power components and a control circuit
  • FIG. 2 shows a cross-sectional illustration of a second embodiment of an integrated power circuit with vertical power components and a control circuit
  • FIG. 3 shows a plan view of a third embodiment of an integrated power circuit according to the invention in the form of a monolithically integrated full-bridge circuit
  • FIG. 4 shows a cross-sectional illustration of a fourth embodiment of the integrated power circuit according to the invention with two vertical power components
  • FIG. 5 shows a cross-sectional illustration of a fifth embodiment of an integrated power circuit with a vertical power component and one Control circuit.
  • an integrated power circuit which is denoted in its entirety by reference number 1, comprises two vertical power components 2, 3 and a control circuit 4 arranged between the vertical power components 2, 3.
  • the vertical power components 2, 3 are implemented as vertical n-channel IGBTs.
  • Each vertical n-channel IGBT 2, 3 comprises a source 5, a gate 6 above an n "epitaxial layer 7, which in turn is arranged on a p + substrate 8, which serves as a drain.
  • the control circuit 4, which is shown in FIG ⁇ th embodiment has an NMOS transistor 9 and a PMOS transistor 10, is located above a rear etching recess 11 and is delimited from the etching recess 11 by an etching stop layer 12.
  • the control circuit 4 is in the lateral direction with respect to the vertical n-channel IGBTs 2, 3 isolated by a LOCOS insulation 13.
  • a low-doped n "layer 7 is epitaxially grown on the p + substrate 8.
  • Oxygen is locally implanted in the epitaxial layer 7 in order to produce the etching stop layer 12.
  • This oxygen implantation step is optionally followed by a high-temperature step in order to avoid crystal defects generated by the oxygen implantation to heal.
  • field rings as edge structures of the vertical power components 2, 3 are generated in an additional process step of the standard CMOS process. Since the structures of the vertical power components 2, 3 are bevelled on both sides on the back, field rings can be omitted in this embodiment, since the edge closure is brought about by this so-called "beveling".
  • the field rings 14 as edge structures of the power units are produced in the embodiment according to FIG. 2 by boron implantation and subsequent out-diffusion.
  • a protective layer is applied to the front of the wafer, while the back is masked and the mask structure in the area of the etching stop layer 12 is opened using a conventional photolithographic technique.
  • the mask is also removed in the region of the outer edges of the vertical power components 2, 3.
  • the substrate is then etched to produce the etching recess 11 on the rear side and to form the bevels 14, whereupon the mask is removed.
  • the buried etch stop layer 12 is separated by a SIMOX process (separation by IMplanted OXygen).
  • buried dielectrics can also be produced as an etch stop layer using other SOI technologies (silicone-on-insulator).
  • SOI technologies silicon-on-insulator
  • the wafer bonding method is mentioned for this purpose, which is described in the following technical publication: WP Maszara, Silicon-On-Insualtor by Wafer-Bonding: A review, J. Electrochem. Soc, 138: 341, 1991.
  • SOI technology is also suitable as SOI technology, which is described in the following specialist publication: A. Nakagawa, Impact of dielectric isolation technology on power ICs, ISPSD, pages 16 to 21, 1991
  • the etch stop layer 12 can be formed by a pn junction or by high-dose implantation of boron or carbon.
  • etch stop layer 12 In deviation from this, it is also possible to use an epitaxial silicon germanium layer as the etch stop layer 12 and, in the case of electrochemical methods, a pn junction as an etch stop.
  • the thickness of the semiconductor membrane on which the control circuit 4 is formed can be adjusted as desired on the one hand via the depth of the buried etch stop layer 12 and on the other hand by means of an additional epitaxial layer.
  • Lateral isolation of the silicon film on which the control circuit 4 is formed is not only possible with LOCOS.
  • dielectric isolation using a trench or isolation using a blocked pn junction can also be effected.
  • a vertical power component 2, 3 is not only the IGBT described, but any other vertical power component can be used without restriction. This includes unipolar and bipolar components, such as DMOS transistors and thyristors. In deviation from the structures shown, inverse doping can also be used in each case. The maximum reverse voltage of the vertical power components is not restricted by the technology according to the invention.
  • CMOS control circuit 4 In addition to the CMOS control circuit 4 shown in the exemplary embodiment, other circuit technologies can also be implemented, such as NMOS circuits or bipolar circuits, which can also contain lateral high-voltage transistors and sensors.
  • the etching recess 11 on the back can be filled in order to increase the mechanical stability or to change the electrical properties.
  • insulating materials such as polyimides can be used here.
  • P.Guillotte and T. Martiska, Polyimide solves chip isolation problems. Semiconductor International, 14 (5): 146-148, 1991.
  • the edge termination of the power component does not necessarily have to take place by means of a field ring structure, as is shown in FIG. 2.
  • Other edge structures can also be used.
  • additional edge structures can be dispensed with entirely, since in this case the potential profile is reduced by the beveled Edges changes so that the surface field strength in the edge areas can be reduced.
  • control circuit 4 is enclosed by the vertical power devices 2, 3. However, it is also possible to position the control circuit outside the vertical power components. As shown in FIG. 3, by combining several such structures on a chip, for example, a complete, compact bridge circuit can be generated, which in the example shown there in plan view comprises four power transistors 15, 16, 17, 18, each with Edge structures 22 are provided, which are controlled by control circuits 23 arranged in the interspaces. The control circuits are enclosed by an etch stop layer 24.
  • FIG. 4 shows a further embodiment of an integrated power circuit 1 according to the invention, which comprises vertical power components 2, 3, but no control circuit is provided.
  • Reference numerals corresponding to the reference numerals of previous figures denote identical or similar parts, so that a renewed explanation can be omitted.
  • this integrated power circuit 1 with the at least two vertical power components 2, 3, the process steps for producing the vertical power components 2, 3 are first carried out, whereupon a lateral insulation layer 13 is produced between these vertical power components 2, 3.
  • This insulation layer 13 can consist either of thermal oxide or of CVD oxide.
  • a front protective layer and a rear mask layer (not shown in each case) are then applied, whereupon the rear mask layer is structured photolithographically in order to define a recess in the mask layer below the insulation layer 13.
  • the substrate is then etched on the back until the lateral is reached Insulation layer 13.
  • the power component shown on the right in the figure is a p-channel IGBT with an n + substrate 20, which forms the drain electrode, a p "drift path 21, an insulated gate 22 and a source electrode 23.
  • the left-hand ver ⁇ tical power component 3 is an n-channel HVDM ⁇ S-Transi ⁇ stor, which also has the n + substrate 20 as a drain electrode and further comprises an n'-drift path 24, a gate electrode 25 and a source electrode 26 .
  • the power components 2, 3 can also include control circuits which are arranged in the substrate material in the previously customary manner by means of SIMOX technology.
  • the etch stop is formed by the implanted oxide layer, which then only serves to separate the power parts. As a result, the etching stop can be designed with small geometric dimensions.
  • the method described last for producing an integrated power circuit with two vertical power components can be modified in such a way that a power component can be modified by a control circuit is replaced.
  • the result is a method for producing an integrated power circuit 1 with a vertical power component 2, 3 and a control circuit 4 for controlling the vertical power component 2, 3, with the following method steps: performing process steps for producing the vertical power component 2, 3 and the control circuit 4; Generate a lateral isola- tion layer 13 between the vertical power device 2, 3 and the control circuit 4; Applying a front protective layer; photolithographic production of a rear mask layer with a recess below the lateral insulation layer 13; and back-etching the substrate.
  • the power component shown on the left is an HVDMOS transistor 2 with an n + substrate 30, which forms the drain electrode, an n ⁇ drift path 31, a gate 32 and a source electrode 33.
  • the CMOS control circuit 4 shown on the right-hand side comprises an NMOS transistor 35, which lies within a p-well 36, and a PMOS transistor 37. These transistors 36, 37 lie above the n "epitaxial layer 31, which is on the n + -
  • the substrate 30 is located, as already explained, the power component 2 and the control circuit 4 are separated from one another by the insulation layer 13 formed by a thermal silicon oxide, below which the etching recess 11 on the rear side lies, and here too the control circuit 4 is influenced excluded by the power component 2.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

Un circuit intégré de puissance (1) comprend soit un composant vertical de puissance (2, 3) et un circuit (4) de commande du composant vertical de puissance (2, 3), soit uniquement des composants verticaux de puissance (2, 3). Afin d'éviter que les processus de commutation du composant vertical de puissance (2, 3) n'exercent des influences indésirables sur le circuit de commande (4), on applique pendant la fabrication du circuit intégré de puissance (1) une couche d'arrêt de gravure (12) sous la zone semiconductrice dans laquelle le circuit de commande (4) sera formé, puis on produit le circuit de commande (4) et le composant vertical de puissance (2, 3) selon des étapes usuelles de fabrication. On applique ensuite sur la galette une couche antérieure de protection et une couche postérieure de masquage. Après avoir structuré le masque afin de créer une ouverture au-dessous de la couche d'arrêt de gravure (12), on grave par attaque la face postérieure du substrat jusqu'à ce qu'on atteigne la couche d'arrêt de gravure (12). Selon un autre mode de réalisation, après avoir effectué les étapes de fabrication des composants verticaux de puissance (2, 3) et après avoir appliqué une couche latérale isolante (13) entre les composants verticaux de puissance, on applique une couche antérieure de protection et une couche postérieure de masquage, puis on crée dans la couche postérieure de masquage un évidement situé au-dessous de la couche latérale isolante, à travers lequel on grave par attaque la face postérieure du substrat jusqu'à ce qu'on atteigne la couche latérale isolante.
PCT/DE1992/000955 1991-11-29 1992-11-12 Procede de fabrication d'un circuit integre de puissance ayant un composant vertical de puissance WO1993011561A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP92923661A EP0614573A1 (fr) 1991-11-29 1992-11-12 Procede de fabrication d'un circuit integre de puissance ayant un composant vertical de puissance

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DEP4139394.5 1991-11-29
DE4139394 1991-11-29
DEP4201910.9 1992-01-24
DE4201910A DE4201910C2 (de) 1991-11-29 1992-01-24 Verfahren zum Herstellen einer Halbleiterstruktur für eine integrierte Leistungsschaltung mit einem vertikalen Leistungsbauelement

Publications (1)

Publication Number Publication Date
WO1993011561A1 true WO1993011561A1 (fr) 1993-06-10

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Application Number Title Priority Date Filing Date
PCT/DE1992/000955 WO1993011561A1 (fr) 1991-11-29 1992-11-12 Procede de fabrication d'un circuit integre de puissance ayant un composant vertical de puissance

Country Status (2)

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EP (1) EP0614573A1 (fr)
WO (1) WO1993011561A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0626100B1 (fr) * 1992-02-12 1998-10-07 Daimler-Benz Aktiengesellschaft Procede de fabrication d'une structure a semiconducteur et structure a semiconducteur fabriquee selon le procede

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3591465A (en) * 1969-09-15 1971-07-06 Us Navy Selective silicon groove etching using a tantalum oxide mask formed at room temperatures
US4072982A (en) * 1974-07-04 1978-02-07 Siemens Aktiengesellschaft Semiconductor component with dielectric carrier and its manufacture
EP0444370A1 (fr) * 1989-12-29 1991-09-04 Telemecanique Dispositif semi-conducteur à régime activé aminci et son procédé de fabrication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3591465A (en) * 1969-09-15 1971-07-06 Us Navy Selective silicon groove etching using a tantalum oxide mask formed at room temperatures
US4072982A (en) * 1974-07-04 1978-02-07 Siemens Aktiengesellschaft Semiconductor component with dielectric carrier and its manufacture
EP0444370A1 (fr) * 1989-12-29 1991-09-04 Telemecanique Dispositif semi-conducteur à régime activé aminci et son procédé de fabrication

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
AKIO NAKAGAWA: "IMPACT OF DIELECTRIC ISOLATION TECHNOLOGY ON POWER ICS.", PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND IC'S. BALTIMORE, APRIL 22 - 24, 1991., NEW YORK, IEEE., US, vol. SYMP. 3, 22 April 1991 (1991-04-22), US, pages 16 - 21., XP000218967 *
MIKROELEKTRONIK Bd. 4, Nr. 6, 1990, Seiten 256 - 259 R. BOGUSZEWICS ET AL 'Leistungsschalter für 500 V mit dielektrisch isolierter CMOS-Signalelektronik' in der Anmeldung erwähnt *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0626100B1 (fr) * 1992-02-12 1998-10-07 Daimler-Benz Aktiengesellschaft Procede de fabrication d'une structure a semiconducteur et structure a semiconducteur fabriquee selon le procede

Also Published As

Publication number Publication date
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