WO1993003546A1

WO1993003546A1 - Analog-to-digital converter

Info

Publication number: WO1993003546A1
Application number: PCT/CA1991/000262
Authority: WO
Inventors: David Andrew Bell
Original assignee: David Andrew Bell
Priority date: 1991-07-26
Filing date: 1991-07-26
Publication date: 1993-02-18

Abstract

Currently available flash-type analog-to-digital converters (ADCs) use large quantities of voltage comparators, resistors and logic gates. An 8-bit flash ADC uses 255 comparators, 256 resistors, and a large number of logic gates in the priority encoder which is connected at the comparator outputs. This invention results in an 8-bit ADC that produces the digital output right at the output terminals of 8 voltage comparators. No priority encoder is needed, and therefore no logic gates are required. As well as the 8 voltage comparators, 8 operational amplifiers and 53 resistors are required for an 8-bit version of this new type of ADC. The circuit operates by setting the bias voltage levels for the comparators by means of digital-to-analog converters (DACs). The inputs to each DAC are a reference voltage level and the higher order digital outputs. Substantial component savings are effected for ADCs with any number of output bits.

Description

ANALOG-TO-DIGlTAL CONVERTER DESCRIPTION

1. Introduction

This invention relates to analog-to-digital converters (ADCs) used in electronics equipment.

2. Analog-to-Digital Converters (ADCs)

Flash-type ADCs (also known as parallel-type) are the fastest and in some ways the simplest of all analog-to-digital converters currently available in integrated circuit form. The major disadvantage of flash converters is that they use large quantities of voltage comparators, resistors and logic gates. For example, an 8-bit flash ADC uses 255 comparators and 256 resistors, in addition to the large quantity of logic gates in the priority encoder section of the converter. A 12-bit flash converter would require 4,095 comparators and 4,096 resistors, as well as all of the logic gates in the priority encoder.

3. Improved ADC Circuit

I have discovered that flash-type analog-to-digital conversion can be performed by a number of voltage comparators equal to the desired output bit number, if the bias levels of the voltage comparators are controlled by means of digital-to-analog converters connected to some of the ADC output terminals. The digital output is taken directly from the comparator output terminals, so that no priority encoder is required. The new circuit is very much simpler than other ADC circuits, and results in a very substantial reduction in the number of components required. Because of its component economy the new circuit is referred to in this patent application as an Economic Analog-to-Digital Converter (EADC). An 8-bit EADC can be constructed using only 8 voltage comparators, 8 operational amplifiers, 53 resistors, and no logic gates. A 12-bit EADC requires only 12 comparators, 12 op-amps, 103 resistors, and no logic gates.

4 Economic Analog-to-Digital Converter (EADC) Circuit

Circuit Description

The principles apply equally to EADC circuits with any number of output bits, however, for simplicity the circuit of a 4-bit EADC is described and its operaton is explained. The 4-Bit EADC circuit shown in Fig. 1 consists of four voltage comparators (C_A, C_B, C_c and

C_D), four operational amplifiers (A_A, A_B, A_C and A_D), and twenty-three resistors (R₁ through R₂₃).

Resistors R₁₉ through R₂₃ constitute a potential divider which provides four negative reference voltage levels (V_rA, V_rB, V_rC and V_rD) derived from the negative supply voltage -V_EE. Operational amplifier

A_A together with resistors R₈, R₉, R₁₀, R₁₁ and R₁₈ constitute a digital-to-analog converter (DAC). (Other type of DAC circuits may be substituted.) Similarly, digital-to-analog converters are consititued by: (op-amp A_B and resistors R₇, R₁₂, R₁₃ and R₁₇), (op-amp A_C and resistors R₆, R₁₄ and R₁₆), (op-amp A_D and resistors R₅ and R₁₅). The DACs produce bias voltages (V_bA, V_bB, V_bC and V_bD) at the nonin verting input terminals of the comparators. The analog input voltage (V_i) is applied simultaneously to the inverting input terminals of all four comparators, and the 4-Bit digital output is taken directly from the comparator output terminals (A, B, C and D). The comparator output stages are open-circuited transistor collector terminals, which are connected via resistors R₁ through R₄ to ground level, as illustrated.

Note that the inputs to the DAC which supplies bias voltage V_bA to comparator C_A are: reference voltage V_rA, and digital outputs B, C and

D. Similarly, the inputs to the DAC which supplies V_bB to C_B are: V_rB, and digital outputs C and D. The inputs to the DAC which supplies V_bC to C_C are: V_rC, and output D. Reference voltage V_rD constitutes the sole input to the DAC which supplies V_bD to C_D. Thus, the inputs to each DAC are its reference voltage and the higher order digital outputs. This means that partial digital-to-analog conversion from the digital outputs is employed to generate the bias voltage for each comparator.

Circuit Operation

The particular 4-bit EADC circuit discussed below is designed for a ± 10 V supply, and for an analog input which goes from zero to a maximum of 1.5 V. The reference voltage levels are: V_rA = -100 m V, V_rB = -200 m V, V_rC = -400 mV, and V_rD = -800 mV. Resistors R₈ and R₁₈ are equal in resistance, as are all similarly located resistors in the op-amp DAC circuits. Thus, the voltage gain of the op-amp circuits (from the reference voltage input to the op-amp output) is -1, and the initial bias voltage levels at the comparator noninverting inputs are, V_bA =

+ 100 mV, V_bB = +200 mV, V_bc = +400 mV, and V_bD = +800 mV. With V_i equal to zero, the comparator outputs are all high, close to ground level. Because the comparator outputs are all at zero, there are no inputs from the comparators to the op-amp DAC circuits. Reading from terminals D, C, B and A, the digital output at this time is 0000.

When V_i is increased to 100 mV, the voltage at the inverting input terminal of C_A equals that at the noninverting input, and C_A output switches to approximately -V_EE. No other comparators are affected, because V_i is still below the bias voltage levels for C_B, C_c and C_D.

Taking the negative output voltage from C_A as logic 1, and ground as logic zero, the complete digital output reading from terminals D, C, B and A is now 0001.

When V_i is increased to 200 mV, the voltage at the inverting input terminal of C_B becomes equal to that its noninverting input. The output of comparator C_B now switches to approximately -V_EE. The C_B output at terminal B is fed via resistor R₉ to op-amp A_A , which controls the bias level for C_A. With correct selection of the ratio of resistors R₉ and R₈, the C_A bias voltage is raised to,

= 100 mV + 200 mV

= 300 mV

Since V_bA is now greater than V^ the output of C_A returns to ground level. The digital output at D C B A now reads 0010.

Increasing V_i to 300 mV causes C_A output to switch lew once again, without affecting the outputs of any other comparator. This gives a digital output reading of 001 1.

With V_i raised to 400 mV, the voltage at the inverting input terminal of C_c becomes equal to the bias level V_bC at its noninverting input. Consequently, C_c output switches to approximately -V_EE, providing an input via resistors R₁₀ and R₁₂ to op-amps A_A and A_B. Once again assuming correct selection of resistor values, the bias voltage for C_B is raised to,

V_bB = -(V_rB + V_rC)

= 200 mV + 400 mV

= 600 mV

Thus, with V_i = 400 mV, C_B output returns to ground level. The bias level forC_A is now determined by V_rA and the outputs of C_B and C_C.

= 100 mV + 0 + 400 mV

= 500 mV

With V_i = 400 mV, C_A output returns to ground, and only C_A output is low. The decimal output reading is 0100.

If the analog input is further increased from 400 mV, the condition of the comparators remains unchanged until V_i = V_bA = 500 mV. At this point, C_A output once again switches low, and the digital output readi ng becomes 0101.

Extending the above discussion to consided the effect of increasing V_i in appropriate steps from zero to 1.5 V, a table of comparator bias voltages and the digital outputs for various levels of analog input voltage is produced, (Table 1). Table 1 shows that, as the analog input voltage is increased, the comparator outputs change state to faithfully produce the correct digital equivalent of the analog input.

Resistor Calculations

With the inverting input terminal of op-amp A_A always at ground level

(virtual ground), the voltage across resistor R₁₈ is V_rA. The current (l₁₈) through R18 is selected to be very much larger than the input bias current of the operational amplifier. Then,

R₁₈ = V_rA /I₁₈

Assuming that the inputs via R₉, R₁₀ and R₁₁ are initially zero, feedback resistor R₈ is made equal to R₁₈, to give a voltage gain of

V_bA/ V _rA = -1

The other similarly-arranged op-amp circuit resistors are all made equal to R₁₈, to give similar voltage gains. Thus,

R₅ = R₁₅ = R₁₈, R₆ = R₁₆ = R₁₈ and R₇ = R₁₇ = R₁₈

When a low level output from C_B is applied via resistor R₉ to op-amp A_A, the bias level at the C_A inverting input is to be 300 mV, ( 100 mV due to V_rA, and 200 mV produced by the C_B output). Note that the 200 mV is the equivalent of V_rB. This gives, R₉ = R₈ x

For this particular circuit,

C_B output = V_EE = - 10 V and V_rB = 200 mV.

Therefore, R₉ = 50 R₈

Bq similar reasoning, R₁₀ = R₁₂ = R₈ x

= 25 R₈

and

R₁₁ = R₁₃ = R₁₄ = R₈ x

= 12.5 R₈

Resistor R₃ has no effect on the current passed through R₉, because the output of C_B is at ground level when R₃ and R₉ are directly in series.

Therefore, resistors R₁ through R₄ should be selected only to pass an acceptable current through the open-collector output transistors in the voltage comparators.

Comments

EADC circuits can be designed to produce any number of output bits, up to 32 bits or greater. (An 8-bit EADC circuit is shown in Fig. 2.) Any convenient set of reference voltage levels may be employed. The digϊtal-to-analog converter sections of the circuit can be designed to operate with a voltage gain equal to 1, greater than 1, or less than 1. The circuit may be rearranged to give positive voltage outputs (instead of negative voltages) to represent logic 1. For the circuit shown in Fig. 1, the maximum level of the analog input voltage that may be converted depends upon the supply voltage, which determines the reference voltage levels and the comparator output voltages. The analog input may be made independent of the supply voltage by the use of commonly known voltage stabilization and clipping techniques. The resistors connected at the outputs of the voltage comparators (R₁ through R₄ in Fig. 1) would be part of the comparators in an integrated circuit ADC. Therefore, these resistors should not be counted as seperate components for the purposes of comparison with other types of ADC.

5. Applications

The EADC is applicable in the myriad situations in computing and general electronics circuitry where analog-to-digital conversion is required. A modification of the EADC principle can be employed for directly converting an analog input voltage into a digital display. The EADC may be employed in integrated circuit or discrete component form, or in a combination of the two.

Claims

CLAIMS The embodiments of the invention in which an exclusive propertg or privilege is claimed are defined as follows:

1. An analog-to-digital converter circuit consisting of voltage level comparing circuits (comparators), digital-to-analog converters (any type), and voltage reference sources; connected (as

illustrated in Figs. 1 and 2) such that the analog input voltage appears at one input terminal of each comparator, the bias voltage levels at the other input terminals of the comparators are provided by the DAC outputs (using any suitable type of DAC), the inputs to the DACs are derived from the voltage reference sources and the comparator outputs, thus producing the digital output directly at the comparator output terminals.

2. A circuit, as described in claim 1, in which the bias voltages for the comparator circuits are set by the digital-to-analog

converters in accordance with the digital output and the reference voltages.