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WO1992019010A1 - Procede de fabrication de plaques minces dont les structures superficielles presentent des hauteurs ou profondeurs differentes - Google Patents

Procede de fabrication de plaques minces dont les structures superficielles presentent des hauteurs ou profondeurs differentes Download PDF

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Publication number
WO1992019010A1
WO1992019010A1 PCT/EP1992/000836 EP9200836W WO9219010A1 WO 1992019010 A1 WO1992019010 A1 WO 1992019010A1 EP 9200836 W EP9200836 W EP 9200836W WO 9219010 A1 WO9219010 A1 WO 9219010A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
outer layers
etching
central layer
thickness
Prior art date
Application number
PCT/EP1992/000836
Other languages
English (en)
Inventor
Ary Saaman
Original Assignee
Westonbridge International Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Westonbridge International Limited filed Critical Westonbridge International Limited
Publication of WO1992019010A1 publication Critical patent/WO1992019010A1/fr

Links

Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04B—POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS
    • F04B43/00—Machines, pumps, or pumping installations having flexible working members
    • F04B43/02—Machines, pumps, or pumping installations having flexible working members having plate-like flexible members, e.g. diaphragms
    • F04B43/04—Pumps having electric drive
    • F04B43/043—Micropumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

Definitions

  • the present invention relates to a method of manufacturing thin plates having surface structures of different depths or hights on one or both sides of the plate.
  • a starting wafer having a central layer of a first material which is covered on at least one side with outer layers of a second material, at least portions of said outer layers having different thicknesses;
  • first etching or growing operation carrying out a first etching or growing operation at which first depressions or deposits are produced in or on the central layer at locations corresponding to the holes in said thinner portions of the outer layers, said first depressions or deposits having an essentially uniform intermediary depth or hight;
  • said uniform thickness essentially corresponding to the difference between the initial thicknesses of the portions of different thicknesses of the outer layers in order to remove the residual layer of the thicker portions of said outer layers within the cavities previously produced in the thicker portions of said outer layers such as to expose the central layer at locations corresponding to said cavities in the thicker portions of said outer layers;
  • the method as described above may be applied for the manufacture of wafers which carry surface structures of different depths on both sides or on one side only.
  • the starting wafer comprises two outer layers on opposite sides of the central layer, the thickness of one outer layer or of a portion thereof being smaller than the thickness of the other outer layer or a portion thereof.
  • the starting wafer comprises an outer layer on one side of the central layer only, whereby this one outer layer comprises portions of different thicknesses.
  • a starting wafer is produced, whereby said wafer comprises a central layer of silicon and outer layers of silicon oxide.
  • the method according to the present invention uses a silicon wafer who's outer oxide layers have different initial thicknesses which may be produced by first oxidizing both sides of a silicon plate to essentially the same thickness to form said outer oxide layers and subsequently reducing the thickness of one of said outer layers. H
  • the thickness of this one oxide layer is reduced by an etching operation.
  • a silicon wafer with surface structures of different depths on one or both sides of the wafer may be produced with as few as one single lithographic process step by which initial cavities in both outer layers are produced in a process where this one or more photolithographic steps may be performed on essentially planar surfaces, i.e. before any etching of depressions in the silicon is performed.
  • the removing of said essentially uniform thickness of said thicker outer layer is carried out by an etching operation which guarantees that the same thickness of the oxide layer is etched away at surface areas which were not etched before as well as in surface areas where first cavities had already been produced, such that the central layer will be exposed if the thickness which is etched away in this second etching operation corresponds to at least the initial difference of thicknesses of the thinner and thicker outer layers minus the small amount of oxide material which is undesirably but unavoidably etched away during the etching step on the material of the central layer. .
  • etching of the cavities in the outer layers and the etching of the depressions in the central layer are carried out with different etching agents, whereof at least the agent for the etching of the central layer is essentially selective such as to produce depressions only in the central layer while remaining inoffensive for the outer layers.
  • One of the possible applications for the method according to the present invention is for the production of wafers such as the ones carrying membranes for micropumps which are comprised of a portion of such a wafer, the membranes being constituted of surface structures of the wafer which form the pump membrane or valve components for cooperation with valve seats which are arranged on other parts of the micropump, which other parts are independent from the wafer but with which said valve components may come into releasable contact.
  • Fig. 1 shows an untreated silicon plate
  • Fig. 2 shows a silicon wafer having a central layer and two oxide layers of same thickness
  • Fig. 3 is the silicon wafer of Fig. 2, whereby one oxide layer has been entirely reduced in thickness;
  • Fig. 4 shows the silicon wafer of Fig. 3 wherein the two oxide layers have received a pattern of etched cavities
  • Fig. 5 is the wafer of Fig. 4 after a first etching operation on the central layer
  • Fig. 6 is the wafer of Fig. 5 after a uniform thickness of the oxide layers has been etched away;
  • Fig. 7 is the wafer of Fig. 6 after a second etching operation on the central layer
  • Fig. 8 is a simplified schematic illustration of a wafer carrying membranes as used in a micropump.
  • Figs. 1 and 2 do not require particular attention as they only illustrate the starting silicon plate 1 and the resulting wafer 2 therefrom after the silicon plate 1 has been oxidized e.g. in a suitable furnace under oxidizing atmosphere.
  • the resulting wafer 2 comprises thus a central layer 8 and outer oxide layers 9 and 10 of more or less the same thickness.
  • the wafer 3 thus comprises a central layer 8 a thinner oxide layer 9a having a thickness "a" and the thicker oxide layer 10, having a thickness "b".
  • the reduction of the thickness of layer 9a has been carried out by a one-sided etching operation or by any other kind of method known in the art.
  • Fig. 3 also shows masks 16 and 16a which are used to define the surface structures produced lateron during the photolithographic/etching process step. In the following description only positive photoresists will be considered for the sake of simplicity, other resists may be understood to be usable in analogous ways.
  • Figs. 2 and 3 show the simple case where the central layer is covered by two oxide layers of different thicknesses, each of which is uniform over the entire surface.
  • one or both oxide layers may include areas of different thicknesses, whereby the initial reduction of the thickness of the portion of the oxide layers which correspond to areas in which deeper final depressions or higher deposits are to be produced later, are obtained by local etching.
  • Fig. 4 illustrates the result of this lithographic/etching process during which both oxide layers were coated with a photosensitive layer (reference number I I in Fig. 3) and the masks were applied to both sides of the wafer on top of the photosensitive layers 11, which masks exposed all those parts of the surfaces of the wafer which were to be kept inert during the following etching operation.
  • the assembly was exposed to UV light and the portions of the surfaces which were left free by the mask were thus activated by UV light to a state in which they became resistant to the used etching agent and thus inhibited access of the etching agent to the oxide layer.
  • the photosensitive layer In the covered areas the photosensitive layer remained soluble in the etching agent and permitted thus access for the agent to the oxide layer, resulting in the formation of cavities 12 and 12a in the two oxide layers at such covered portions of the surfaces, the depth of said cavities being a function of the etching time and other parameters.
  • the duration of the etching step was selected such as to permit complete dissolution of the thinner oxide layer 9a at the desired locations whereas the thicker oxide layer 10 only received cavities which did not traverse the entire thickness of the thicker oxide layer 10a but left a residual layer 10c of a thickness x within the cavities 12a. ?
  • the thickness of the thinner oxide layer was selected initially as two thirds of the thickness of the thicker oxide layer, and since the cavities in both oxide layers are of the same depth, it is trivial that the thickness x of the residual oxide layer 10c within the cavities 12a is one third of the thickness of the originally thicker oxide layer 10.
  • Fig. 5 illustrates the wafer 5 as obtained from wafer 4 of Fig. 4 after a first etching step on the central layer 8.
  • Immersion of the wafer into KOH for example does not significantly attack the oxide layers, but etches first depressions 13 of an intermediary depth y into the parts of the central layer 8 which are exposed to the solution through the holes 12 in the thinner oxide layer 9b, whereas the entire side of the thicker oxide layer is only insignificantly but uniformly affected by this etching step.
  • a double-sided etching step is carried out on the side of the thicker oxide layer 10a in order to take away a uniform thickness x of both oxide layers 10a and 9b all over the surface, i.e. within and outside the cavities 12a.
  • the thickness x of the eliminated portion of the thicker oxide layer is identical to the thickness x of the residual layer within the previously formed cavities 12a. The results of this step are shown in Fig. 6.
  • This double-sided etching step is calculated such as to eliminate the residual oxide layer 10c within the cavities 12a in the thicker oxide layer 10b while the portions of the thicker oxide layer which were not etched previously are reduced in thickness to e.g. a value essentially corresponding to the thickness of the remainders of the initially thinner oxide layer 9a.
  • This step results in the exposure of the central layer 8 at locations corresponding to the previously produced cavities 12a.
  • Fig. 7 shows the wafer 7 obtained from wafer 6 of Fig. 6 after a second etching step on the central layer 8, whereby the latter receives second depressions 14 on the side of the initially thicker oxide layer 10a, which second depressions have a depth z' while the first depressions 13 in the central layer 8 on the side of the initially thinner oxide layer 9a are deepened from their initial intermediary depth y to their final depth z which represents in principle the sum of y plus z'.
  • the speed of the deepening of the depressions in the central layer is somewhat dependent on the cross section of the cavities in the oxide layers, so as to produce slightly deeper depressions where the cavities are wider because of the easier access of fresh etching agent to and easier removal of dissolved material from the etching locations. It may be envisaged to take advantage of this effect in order to produce differences in the depths of the produced depressions in the central layer.
  • Figs. 7 and 8 show finished wafers 7 and 8 which have surface structures of different depths on both sides.
  • the wafer of Fig. 8 forms membranes 15 such as currently used e.g. in the art of manufacturing micropumps, where such wafers are used as integral elements, carrying membranes usefull for pumping movements or as valve elements.
  • the wafer of Fig. 8 has been produced by a process in which the upper side of the starting wafer included areas of different oxide thicknesses. Consequently, depressions 13b are shallower than depressions 13a and the two membranes 15a and 15 are therefore of different thicknesses.
  • the thinner oxide layer had a thickness of 1.0 micrometers, the thicker layer of 1.5 micrometers and first cavities of 1.0 micrometers were formed in both layers such that the central layer was exposed through the cavities in the thinner layer whereas a residual thickness of 0.5 micrometers remained in the cavities of the thicker layer.
  • a first KOH etching step the areas outside the cavities of the thinner oxide layer were insignificantly reduced from 1.0 to 0.9 micrometer thickness whereas depressions of desired depths were produced in the central layer.
  • the thickness of the thicker oxide layer was reduced outside the cavities from 1.5 to 1.4 micrometers and the residual oxide layer within the cavities of the thicker layer was reduced from 0.5 to 0.4 micrometers.
  • the wafer was submitted to an etching process which reduced the thickness of all oxide surfaces by 0.4 micrometers, so that the remaining oxide layer of the initially thinner outer layer became 0.5 micrometer and the initially thicker oxide layer came down to 1.0 micrometers at locations outside the cavities, whereas the residual oxide layer within the cavities on the side of the initially thicker oxide layer completely disappeared.
  • a following second KOH etching step increased the depth of the previously produced first depressions on the side on the initially thinner outer layer, whereas at the same time second depressions were produced on the side of the initially thicker outer layer at locations corresponding to the previously formed cavities therein.
  • the method of the present invention may also be used in applications where portions of the central layer have to be etched through their entire thickness in order to produce through holes therein.
  • first depressions of any desired dimensions are produced in one side of the wafer (as in the process step preceding Fig. 5) such as to almost traverse the central layer whereafter the second etching step (preceding Fig. 7) only finishes off the remaining part from the opposite side.
  • the second etching step preceding Fig. 7
  • the starting material is not at all limited to silicon and the outer layers need not be oxides. Other materials are equally susceptible to be processed according to the described method. Further, as already mentioned above, the differences in the initial thickness of the two outer layer need not be confined to layers on opposite sides of the central layer but may also be applied to specific areas on the same side of the wafer. It is also possible to provide wafers having areas of a number of different thicknesses on one or both sides.
  • the invention has also been described with respect to etching processes only, it being understood that the reverse processes, i.e. growing processes wherein deposition layers are produced on areas of the exposed central layer, may also be carried out in a way analogous to the described process steps for the etching processes.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)

Abstract

On produit à l'aide d'un processus spécial une tranche de silicium (2-8) dont l'un et/ou l'autre des côtés présente(nt) des structures superficielles dont les profondeurs ou les hauteurs sont différentes, ladite tranche étant destinée, par exemple, à s'intégrer à une micropompe. Afin de réduire le nombre d'étapes de photogravure dans un processus de production exigeant plusieurs étapes d'attaque ou de croissance, la tranche de départ (3) comporte une couche centrale (8) dont les deux faces sont revêtues de couches d'oxyde (9a, 10) dont les épaisseurs diffèrent. Dans une première phase du processus, on forme dans les deux couches d'oxyde (9a, 10) des cavités superficielles (12, 12a) traversant entièrement la couche moins épaisse (9b) mais n'atteignant pas la couche centrale (8) du côté de la couche d'oxyde plus épaisse (10a). Tandis que la première étape d'attaque ou de croissance sur la couche centrale (8) s'effectue sur la tranche (5) en n'attaquant que le côté de la couche centrale (8) qui porte la couche moins épaisse (9a) pendant que l'autre côté est toujours entièrement revêtu de la couche plus épaisse (10a, 10c), la seconde étape d'attaque ou de croissance sur la couche centrale (8) s'effectue une fois que l'on a réduit la couche plus épaisse (10a) de manière à mettre à nu ladite couche centrale (8) au niveau des cavités formées initialement (12a). De ce fait, les creux (14) formés au cours de ladite seconde étape d'attaque du côté de la couche d'oxyde initialement plus épaisse sont moins profonds. Dans le cas d'un processus de croissance, les premiers dépôts sont moins élevés que les creux (13) ou les dépôts formés de l'autre côté au cours des deux étapes d'attaque ou de croissance.
PCT/EP1992/000836 1991-04-15 1992-03-27 Procede de fabrication de plaques minces dont les structures superficielles presentent des hauteurs ou profondeurs differentes WO1992019010A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9107935.1 1991-04-15
GB9107935A GB2254830A (en) 1991-04-15 1991-04-15 Manufacturing thin plates having surface structures of different depths or heights

Publications (1)

Publication Number Publication Date
WO1992019010A1 true WO1992019010A1 (fr) 1992-10-29

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PCT/EP1992/000836 WO1992019010A1 (fr) 1991-04-15 1992-03-27 Procede de fabrication de plaques minces dont les structures superficielles presentent des hauteurs ou profondeurs differentes

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AU (1) AU1457592A (fr)
GB (1) GB2254830A (fr)
WO (1) WO1992019010A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4938742A (en) * 1988-02-04 1990-07-03 Smits Johannes G Piezoelectric micropump with microvalves
WO1990015929A1 (fr) * 1989-06-14 1990-12-27 Westonbridge International Limited Micropompe perfectionnee

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4938742A (en) * 1988-02-04 1990-07-03 Smits Johannes G Piezoelectric micropump with microvalves
WO1990015929A1 (fr) * 1989-06-14 1990-12-27 Westonbridge International Limited Micropompe perfectionnee

Also Published As

Publication number Publication date
AU1457592A (en) 1992-11-17
GB9107935D0 (en) 1991-05-29
GB2254830A (en) 1992-10-21

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