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WO1992008230A1 - Fichier de registre rapide a cinq points d'acces capable de lire et d'ecrire simultanement et tolerant un dephasage des impulsions d'horloge - Google Patents

Fichier de registre rapide a cinq points d'acces capable de lire et d'ecrire simultanement et tolerant un dephasage des impulsions d'horloge Download PDF

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Publication number
WO1992008230A1
WO1992008230A1 PCT/US1991/008057 US9108057W WO9208230A1 WO 1992008230 A1 WO1992008230 A1 WO 1992008230A1 US 9108057 W US9108057 W US 9108057W WO 9208230 A1 WO9208230 A1 WO 9208230A1
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WO
WIPO (PCT)
Prior art keywords
register file
tri
data
write
state
Prior art date
Application number
PCT/US1991/008057
Other languages
English (en)
Inventor
James H. Hesson
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Publication of WO1992008230A1 publication Critical patent/WO1992008230A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Definitions

  • This invention relates to data processing systems, semiconductor logic circuits and, more particularly, to multiport register files that support simultaneous read and write operations.
  • High-speed local memory incorporated in a microprocessor system is generally termed a register file.
  • the register file is typically the first level of high- speed storage, it is beneficial from the compiler's point of view for it to be as large as possible. Latency time associated with the processing of data will be minimized if data may be both written to and read from the same register file location, or from different register file locations during a single clock cycle. As clock frequencies continue to increase, clock skew (as a percentage of the clock cycle) also increases, thus necessitating a register file design with a high degree of immunity to that phenomenon.
  • microprocessor systems are designed for data input in both byte and multi-byte formats (i.e., byte, 16- bit halfword, 32-bit word, and 64-bit doubleword) . Additionally, as a means to enhance system reliability, memory error correction may also be desireable. Both of these requirements make difficult the design of a register file that is both large and fast.
  • the first is to provide support for both 32- bit words and 64-bit doublewords within the register file; the second is to provide a means to simultaneously write to and read from a single register or different registers of the register file during a single clock cycle; the third is to provide a means to format input data loaded to the register file as bytes, halfwords, words or doublewords; the fourth is to provide a means to correct the data stored within the register file using the syndrome bits of a modified Hamming code; the fifth is to allow operation of the register file at clock frequencies in excess of 100MHz with a high degree of immunity to clock skew; and the sixth is that the register file is manufacturable using existing semiconductor production equipment.
  • the improved register file is a memory register array having input ports which are formatted by means of a high ⁇ speed multiplexer. Such formatting is required to support memory-to-register file load operations for byte, halfword (2-byte) , word (4-byte) , and doubleword operands.
  • a modified Hamming error correction code (ECC)
  • ECC Hamming error correction code
  • ECC Hamming error correction code
  • ECC syndrome bits By altering the conventional sequence of events, error correction for the improved register file is performed during the format decode and format operations, thus permitting the generation of ECC syndrome bits to occur in parallel with the formatting operations.
  • ECC is enabled, any byte, halfword, and word store operations are packed within the processor so that all external memory store operations remain 64-bit in width.
  • Formatted and corrected data passes through latches that both sample the input on the low state of a single phase master clock, and hold the input data through the high state of the next clock cycle.
  • Cells within the register file array may be characterized as being of the feedback-type latch variety, having multiple tri-state inverter input paths for the writing of data, and multiple tri-state inverter output paths for the reading of data.
  • a tri-state inverter provides the feedback within each array cell. The feedback inverter is tri-stated during each write operation, thus increasing circuit speed and permitting simultaneous read and write operations to be performed on the same cell during a single machine cycle. As multiple input sources exist for each register file cell, the feedback tri-state inverter must be disabled whenever any of the input sources desire to write data to that cell.
  • the address decode operation is performed during the high state (first phase) of the clock cycle and gated by the clock when the clock is in the low state.
  • a write operation is terminated by the positive clock edge while the data is held valid for the first half of the next clock cycle. Moreover, the input data to the write port is held for the first half of the next clock cycle.
  • isolation buffers consisting of tri-state buffers are used to both isolate the bit lines and to buffer the bit lines as data is accessed.
  • each register file cell tri- state output device sees only the tri-state output capacitance of its seven neighboring cells, the output capacitance of an upper tri-state isolation buffer, and the input capacitance of a lower tri-state isolation buffer.
  • An output read multiplexer is used to select a data bit or its complement depending on the register block source location.
  • Figure 1 is a block diagram showing the architecture of a five-port register file
  • Figure 2 is logic diagram for an input format array cell of first write port WPl
  • Figure 3 is a logic diagram of an input format array cell for second write port WP2 ;
  • Figure 4 is a logic diagram of the second high-speed multiplexer designated as item 33 of Figure' 3;
  • Figure 5 is a logic diagram for a core cell within the five-port register file
  • Figure 6 depicts a tri-state inverter building block
  • Figure 7 is a circuit diagram of the tri-state inverter building block depicted in Figure 6;
  • Figure 8 is a logic diagram for a write decoder cell
  • Figure 9 is a timing diagram depicting write timing cycles for the first write port WPl and the second write port WP2;
  • Figure 10 is a logic diagram of an isolation buffer array cell;
  • Figure 11 is a logic diagram depicting a single column within the register file core array, showing isolation buffer positions
  • Figure 12 is a logic diagram showing output pipeline compensation register elements for readports RD1 and RD2;
  • Figure 13 is a logic diagram showing output pipeline compensation register elements for readport RD3.
  • Figure 1 is a block diagram of the architecture for a five-port register file unit.
  • the unit contains thirty- two 64-bit doublewords. Each 64-bit doubleword is constructed from a pair of 32-bit words, which permits loads and stores to be effected as 32-bit or 64-bit operands.
  • Three of the five ports, RD1, RD2 and RD3, are read ports, while the remaining two ports, WPl and WP2 are write ports.
  • Read ports RD1 and RD2 are associated with an execution unit of the system data processor, while read port RD3 is associated with the data load store unit, which performs all data load store operations between main memory and the register file.
  • Write port WPl is associated with the execution unit, while write port WP2 is associated with the data load store unit.
  • WPl format unit 1 formats execution unit results as either word (32-bit integer, 32- bit single precision floating point) or doubleword (64-bit integer and 64-bit double precision floating point) quantities.
  • WP2 format unit 2 formats data being loaded from external memory. It contains support for an ECC modified Hamming code with 64 data bits and eight check bits. When ECC is enabled, the unit will flip a single erroneous data bit at a location specific to a syndrome vector (bits S0-S7) generated by an ECC unit (not shown) .
  • the register file unit is further partitioned into eight array sections 3 with eight doublewords per section.
  • Isolation buffers 4 through 9 are positioned between each array section 3, and serve the dual purpose of isolating bit lines and providing drive current to read output ports RD1, RD2, and RD3.
  • isolation buffers 8 and 9 decouple the array section containing words W32 through W47 from the array section containing words W48 through W63 by being driven to a tri-state condition.
  • Isolation buffer arrays 4, 5, 6 and 7 function as drivers during such a read operation.
  • Formatting is required to support memory-to-register file load operations for byte, halfword (2-byte) , word (4- byte) and doubleword operands. Formatting is performed separately for each write port.
  • each array doublesection consisting of eight doublewords, is serviced by a pair of odd and even write decoders.
  • Odd write decoders are items 10-OD, 11-OD, 12-OD and 13-OD
  • even write decoders are items 10-EV, 11-EV, 12-EV and 13-EV.
  • both write decoders 10-OD and 10-EV are activated.
  • the cell comprises an input high-speed multiplexer 21 and a latch 22 enabled by the low phase of the clock signal CLK. Multiplexing is achieved by selecting one of the data inputs, INO through INK, via their respective enable control inputs, ENO through ENK and enable-bar control inputs ENOB through ENKB, from the WPl format decoders (items 14-OD and 14-EV of Figure 1) .
  • a pair of series inverters 23 and 24 serve to buffer the output of first write port WPl format unit 1.
  • second write port WP2 is formatted by means of a first high-speed multiplexer 31. Multiplexing is achieved by selecting one of the data inputs, INO through INM, via their respective enable control inputs, ENO through ENM and enable-bar control inputs ENOB through ENMB, from the WP2 format decoders (items 15-OD and 15-EV) of Figure 1) . If a Hamming error correction code (ECC) is enabled, syndrome vector bits SO through S7 will designate a single bit error location within a doubleword operand. The syndrome vector and its complement (not shown) are decoded by an error location decoder 32 which performs an 8-bit AND operation.
  • ECC Hamming error correction code
  • a second high ⁇ speed multiplexer 33 will flip the incorrect bit within the doubleword operand.
  • a normal sequence for performing error correction on operands during load operations requires error correction to be performed prior to a format decode operation, the formatting operation itself and the load- to-register file operation. By altering the normal sequence of events, error correction is performed subsequent to the format decode and format operations, thus permitting the generation of ECC syndrome bits to occur in parallel with the formatting operation.
  • ECC is enabled, any byte, halfword, and word store operations must be packed within a 64-bit quantity within the processor so that all external memory store operations remain 64-bit in width. Formatted and corrected data passes through latches 34 that sample the input on the low state of a single phase master clock CLK, and hold the input data through the high state of the next clock cycle.
  • the second high-speed multiplexer 33 depicted in Figure 3 is formed from a pair of tri-state inverters 41 and a single inverter 42.
  • cells within the register file array may be characterized as being of the feedback-type latch variety, having multiple tri-state inverters 51 in the data write path, and multiple tri-state inverters 52 in the data read path.
  • a tri-state inverter 53 provides feedback within each array cell. Feedback inverter 53 is tri- stated during each write operation, thus increasing circuit speed and permitting simultaneous read and write operations to be performed on the same cell during a single machine, cycle. As multiple input sources WPl and WP2 are routed to each register file cell, feedback tri-state inverter 53 must be disabled whenever any of the input sources desire to write data to that cell.
  • Tri-state inverter building block 61 is used as the building block for the register file cell depicted in Figure 5.
  • Tri- state inverters 51, 52 and 53, shown in Figure 5 are functionally identical to tri-state inverter building block 61.
  • tri-state inverter building block 61 is constructed by connecting a pair of series P- channel MOSFETs Ql and Q2 with a pair of series N-channel MOSFETs Q3 and Q4.
  • write decoder cell logic diagram of Figure 8 write decode for each cell within first write port WPl is performed by a six-input AND block 81, while write address decode for each cell within second write port WP2 is performed by a six-input AND block 82, in conjunction with an enable bar control signal DLAT1. If either AND block 81 or AND block 82 signal a write operation to a particular cell, the feedback clock signal WCLK and its complement WCLKB are generated.
  • All clock timing signals (WCLK, WCLK1, WCLK2 and their complements) are gated by a master clock signal CLK. Furthermore, an enabled transmission gate 83, having enable and enable bar signals tied off, is interposed in each clock complement signal path in order to equalize the delay in the complemented and uncomplemented clock paths.
  • a timing sequence is depicted for a write to write port 1 followed by a write to write port 2.
  • the timing signals in this Figure correspond to like-named signals in Figures 5 and 8.
  • the write address decode operation is performed during the high state (first phase) of the clock cycle and gated by the clock when the clock is in the low state.
  • a write operation is terminated by the positive clock edge while the data is held valid for the first half of the next clock cycle.
  • the input data to the write port is held for the first half of the next clock cycle.
  • the isolation buffer array cell of Figure 10 the cell is formed from three tri-inverters 101, 102 and 103 that are functionally identical to the tri- state inverter depicted in Figure 7. From Figure 1, as read ports RD1 and RD2 exit the bottom of the register file and read port RD3 exits the top of the register file, the tri-state inverters which form the isolation buffer cell are directed accordingly.
  • the signals RB1EN, RB2EN, RB3EN and their complements are the isolation buffer array enable signals generated by the isolation read decoders ISDECO, ISDEC1 and ISDEC2 of Figure 1.
  • each register file cell tri-state output device sees only the tri-state output capacitance of its seven neighboring cells, the output capacitance of an upper tri-state isolation buffer, and the input capacitance of a lower tri- state isolation buffer.
  • an output multiplexer 121 is associated with each column of each read port (RD1 and RD2) .
  • Each multiplexer is used to select a data bit or its complement depending on the word source location within the register file.
  • an output multiplexer 131 is also associated with each column of third read port RD3. Each multiplexer is used to select a data bit or its complement depending on the word source location within the register file.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Un réseau de fichiers de registres de mémoire accessibles dans le format à la fois à un mot et à deux mots comporte des cellules de mémoire de type à bascule à réaction, comportant au moins deux chemins inverseurs à trois états (RP1, RP2, RP3) utilisés dans la sortie de données. Un inverseur à trois états (53) transmet la réaction à l'intérieur de chaque cellule du réseau. Cet inverseur de réaction est à trois états pendant chaque opération d'écriture, augmentant ainsi la vitesse du circuit et permettant l'exécution d'opérations de lecture et d'écriture simultanées dans la même cellule pendant un seul cycle machine. Les corrections d'erreurs sont effectuées pendant le décodage du format et les opérations relatives au format de sorte que la production du bit de syndrôme du code de corrections d'erreurs (ECC) peut avoir lieu parallèlement au formatage. Les opérations de synchronisation améliorées mantiennent la symétrie des signaux de synchronisation de fichiers de registre et permettent une tolérance élevée du déphasage des impulsions d'horloge. On utilise des tampons d'isolation à trois états (4, 5, 6,7, 8 et 9) afin de réduire le temps d'accès de lecture.
PCT/US1991/008057 1990-10-26 1991-10-28 Fichier de registre rapide a cinq points d'acces capable de lire et d'ecrire simultanement et tolerant un dephasage des impulsions d'horloge WO1992008230A1 (fr)

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US60403290A 1990-10-26 1990-10-26
US604,032 1990-10-26

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422857A (en) * 1989-11-21 1995-06-06 Matsushita Electric Industrial Co., Ltd. Semiconductor memory unit having overlapping addresses
FR2724472A1 (fr) * 1994-09-14 1996-03-15 Suisse Electronique Microtech Automate insensible aux delais d'horloge
US5590087A (en) * 1993-05-05 1996-12-31 Hewlett-Packard Company Multi-ported data storage device with improved cell stability
EP1050885A1 (fr) * 1999-05-03 2000-11-08 STMicroelectronics S.A. Mémoire à accès multiple
US10868531B2 (en) 2016-03-31 2020-12-15 Thine Electronics, Inc. Signal-multiplexing device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4491937A (en) * 1982-02-25 1985-01-01 Trw Inc. Multiport register file
US4610004A (en) * 1984-10-10 1986-09-02 Advanced Micro Devices, Inc. Expandable four-port register file
US4654826A (en) * 1984-08-20 1987-03-31 National Semiconductor Corporation Single device transfer static latch
US4719596A (en) * 1986-03-19 1988-01-12 International Business Machines Corporation Register providing simultaneous reading and writing to multiple ports
JPH01122093A (ja) * 1987-11-06 1989-05-15 Hitachi Ltd 半導体記憶装置
US4933909A (en) * 1988-12-19 1990-06-12 Bull Hn Information Systems Inc. Dual read/write register file memory

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4491937A (en) * 1982-02-25 1985-01-01 Trw Inc. Multiport register file
US4654826A (en) * 1984-08-20 1987-03-31 National Semiconductor Corporation Single device transfer static latch
US4610004A (en) * 1984-10-10 1986-09-02 Advanced Micro Devices, Inc. Expandable four-port register file
US4719596A (en) * 1986-03-19 1988-01-12 International Business Machines Corporation Register providing simultaneous reading and writing to multiple ports
JPH01122093A (ja) * 1987-11-06 1989-05-15 Hitachi Ltd 半導体記憶装置
US4933909A (en) * 1988-12-19 1990-06-12 Bull Hn Information Systems Inc. Dual read/write register file memory

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422857A (en) * 1989-11-21 1995-06-06 Matsushita Electric Industrial Co., Ltd. Semiconductor memory unit having overlapping addresses
US5631869A (en) * 1989-11-21 1997-05-20 Matsushita Electric Industrial Co, Ltd. Semiconductor memory unit having overlapping addresses
US5590087A (en) * 1993-05-05 1996-12-31 Hewlett-Packard Company Multi-ported data storage device with improved cell stability
FR2724472A1 (fr) * 1994-09-14 1996-03-15 Suisse Electronique Microtech Automate insensible aux delais d'horloge
EP1050885A1 (fr) * 1999-05-03 2000-11-08 STMicroelectronics S.A. Mémoire à accès multiple
US6718452B1 (en) 1999-05-03 2004-04-06 Stmicroelectronics S.A. Storage array supporting a plurality of instruction modes
US10868531B2 (en) 2016-03-31 2020-12-15 Thine Electronics, Inc. Signal-multiplexing device

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