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WO1992006495A1 - Dispositif micro-electronique composite libere des contraintes thermiques - Google Patents

Dispositif micro-electronique composite libere des contraintes thermiques Download PDF

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Publication number
WO1992006495A1
WO1992006495A1 PCT/US1991/006627 US9106627W WO9206495A1 WO 1992006495 A1 WO1992006495 A1 WO 1992006495A1 US 9106627 W US9106627 W US 9106627W WO 9206495 A1 WO9206495 A1 WO 9206495A1
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WIPO (PCT)
Prior art keywords
substrate
reduced rigidity
region
component
volume
Prior art date
Application number
PCT/US1991/006627
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English (en)
Inventor
James C. Young
Original Assignee
E.I. Du Pont De Nemours And Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by E.I. Du Pont De Nemours And Company filed Critical E.I. Du Pont De Nemours And Company
Priority to CA002091465A priority Critical patent/CA2091465A1/fr
Priority to JP3517867A priority patent/JPH06503207A/ja
Publication of WO1992006495A1 publication Critical patent/WO1992006495A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate

Definitions

  • the invention relates to composite microelectronic devices which are configured to reduce the thermally induced stresses in the device generated by ordinary operation.
  • microelectronic devices such as VLSI (very large scale integration) silicon chips
  • VLSI very large scale integration
  • a typical composite package is comprised of a ceramic substrate on which is mounted firmly an integrated circuit (IC) chip.
  • the IC chip is electrically interconnected to a plurality of conductive and dielectric layers surrounding the chip which are also firmly attached to the substrate, but spatially separated from the chip.
  • Figures 1 and 2a show a typical composite package with a chip wire-bonded across a narrow channel to interconnected multiple conductive and dielectric layers surrounding the chip, and both the chip and the multilayer structure are attached firmly to a common base substrate.
  • This type of package involves several materials with different coefficients of thermal expansion and moduli of elasticity. A difference between operating temperatures and the temperature at which the package was manufactured results in thermally induced stresses and deformations that affect the reliability. They are very difficult to eliminate due to the inherent mismatch in the coefficients of thermal expansion between the multilayer component, usually made of copper and polyimide, and the silicon chip.
  • the conventional approach in this situation is to select a substrate material that produces the lowest stresses in both the chip and the multilayer component.
  • the present invention provides an improved substrate design that reduces the mechanical interaction among the three.
  • the invention is directed to a microelectronic device comprising a rigid substrate having a component mounted thereon, the component having a plurality of sides and an electrically functional layer adjacent to at least two sides of the component and the electrically functional layer being separated by a guard band, the volume of the substrate underlying the guard band having one or more regions of reduced rigidity which permit the substrate to flex, thereby to dissipate mechanical stresses generated therein when the device is subjected to heating.
  • guard band refers to the unoccupied surface area of a substrate which by virtue of physical spacing serves to isolate adjacent electrically functional elements mounted on the substrate.
  • Figure 1 is an orthographic projection of a conventional composite microelectronic package.
  • Figure 2a is a schematic section of a conventional composite microelectronic package and figures 2b through 2e are schematic sections of microelectronic packages which have been configured in accordance with the invention.
  • Figure 3a is a graphical representation of the in- plane normal stresses of a conventional microelectronic package and 3b is a graphical representation of such stresses in a like microelectronic package which has been configured in accordance with the invention.
  • Figure 4 is a bar chart which compares the in-plane thermal stresses of ungrooved and grooved substrates.
  • Figure 5 is a bar chart which compares the in-plane thermal stresses of copper layers on both ungrooved and grooved substrates.
  • Figure 6 is a bar chart which compares the in-plane thermal stresses of a silicon die mounted on both ungrooved and grooved substrates.
  • the patent is directed to a photoresist process for forming grooves in semiconductor materials for the purpose of isolation of integrated circuits.
  • the patent does not disclose or suggest the function of grooves in substrates for any reason.
  • the invention is based upon fabricating the substrate in such a manner that the attached chip expands and contracts at a rate relatively independently of the expansion and contraction rates of the remaining interconnected package components that are also attached to the substrate.
  • the substrate in accordance with the present invention includes a small flexible substrate region of reduced rigidity having a finite surface area wherein the area occupies a substantial space beneath the guard band that separates the chip and the surrounding package components.
  • This region of reduced rigidity is connected to two rigid substrate sections wherein one rigid section supports the chip and the other supports the remaining interconnected package components.
  • the flexible section provides a forgivable mechanical linkage between the two rigid sections wherein the chip attached to one rigid section can expand and contract more or less independently, irrespective of the expansion and contraction of other package components attached to the other rigid section.
  • the small flexible section can be a flexible material (Fig. 2b) or a thin section (Fig. 2c-e) formed by continuous or discontinuous grooves.
  • Fig. 2b the thermally-induced stress and deformation in the chip caused by other package components, or vice versus, are extremely small so that the changes for chip or interconnects failures are reduced.
  • the complete substrate or package has the traditional exterior dimensional appearance and overall is still very rigid structurally so that it can be handled with traditional package assembly methods. -.
  • Figures 1 and 2a illustrate the structure of a conventional composite microelectronic package consisting of an inert ceramic substrate 1 on which is firmly mounted an integrated circuit chip 3.
  • the substrate can be made of such materials as A1N, SiC, AI 2 O3, Si, quartz, mullite, cordierite and galium arsenide.
  • the chip 3 is adhered to substrate 1 by means of an adhesive layer 5 which may be either inorganic and/or organic in nature.
  • the adhesive layer also known as the die- attach layer, is an organic thermoplastic or thermoset polymer such as those which are disclosed in EP 88104940.7, which is incorporated herein by reference.
  • a dielectric layer 7 Surrounding the chip 3 is a dielectric layer 7 on which is mounted a series of conductive signal/power planes 9.
  • the chip and dielectric layer 7 are separated by a guard plane and the chip 3 is connected electrically to the signal/power planes 9 by a series of fine conductive wires 11 which are typically made of gold or copper metal.
  • the substrate 1 of Figure 1 has not been grooved or otherwise stress-relieved in accordance with the invention.
  • Figures 2b through 2e illustrate devices similar to that of Figures 1 and 2a, but differ in that each has a region of reduced rigidity to effect relief of the thermally induced stresses.
  • the reduced rigidity region is comprised of a solid material 13b which is a more flexible solid than the rigid material of the remainder of the substrate.
  • Figure 2c illustrates a package in accordance with the invention in which the region of reduced rigidity consists of a groove 13c cut into the top of the substrate and extending through about 80% of the substrate thickness.
  • the groove can be continuous around the outer edges of the chip or it can be intermittent or discontinuous so long as the degree of stress relief is sufficient.
  • Figure 2d illustrates a package in accordance with the invention in which the region of reduced rigidity is comprised of two grooves 13d - one extending into the substrate from the top of the substrate and the other from the bottom of the substrate.
  • Figure 2e then illustrates a similar package in which the region of reduced rigidity is a single groove 13e extending into the substrate from the bottom of the substrate.
  • the region or regions of reduced rigidity may extend continuously or discontinuously around the edges of the component so long as the region of reduced rigidity is sufficient to provide the desired degree of stress relief.
  • the ratio of the modulus of elasticity of the substrate containing a region of reduced rigidity to the modulus of elasticity of the remainder of the substrate (Modulus Ratio) be less than 0.3.
  • the grooves or other configuration which constitute the regions of reduced rigidity should not extend through more than 80% of the thickness of the substrate.
  • the term "rigid substrate” refers to substrates having a modulus of elasticity before modification in accordance with the invention of at least lOGpa.
  • the regions of reduced rigidity can be round-bottomed or square-bottomed, they can have vertical or sloped sides. In general, the sides of the grooves need not correspond with the edge of the guard level and the outer edge of the chip. Nevertheless, such configurations are preferred.
  • the over ⁇ riding consideration is whether the reduced rigidity regions are of sufficient volume to render the Modulus Ratio below 0.3 and preferably below 0.1. Compliance with this criterion of Modulus Ratio can readily be determined by direct measurement of the moduli or it can be determined by computer modeling and analysis of the system.
  • the substrate can be made simply of a single base material such as those mentioned above or it can be a composite material consisting of a dispersion of particles or fibers in a matrix of a base material or base material mixture. Fibers can be used as a substrate filler in order to increase substrate strength. On the other hand, heat-conductive materials may be added as well in order to increase the ability of the substrate to conduct heat away from the microelectronic component. In general, substrates will be on the order of 40-80 mils in thickness of which 60 mils is typical. Thermally induced stresses on the substrate tend to be directly related to thickness, whereas stresses in the surrounding dielectric layers tend to be inversely related to substrate thickness.
  • the regions of reduced rigidity, which are most frequently grooves be as close as possible to the chip but not underlying the chip.
  • the grooves surrounding a component will not exceed about 10 mils in width, which is the usual maximum width of the guard band in most composite packages.
  • the groove depth should not exceed about 80% of the substrate thickness. A substrate thickness of at least 10 mils should remain to avoid excessively weakening the mechanical strength of the substrate.
  • grooves When grooves are used to form the reduced rigidity region, they can be left open or they can be filled with a flexible material such as an elastomeric polymer or other non-rigid filler material.
  • Substrate (3.81x3.81x0.153cm) Laminant (2 planes with 1.53x1.53 cm cavity) Copper Layer (3.81x3.81x0.0036 cm) Dielectric Layer (3.81x3.81x0.0025 cm) Adhesive (3.81x3.81x0.0025 cm)
  • Groove dimensions are presented with the calculated maximum stresses shown in Table 1.
  • Table 1 data are presented showing the maximum in-plane thermal stresses incurred by the copper layer, the die attach adhesive and the die itself when they are heated to 170°C and allowed to cool to 20°C under ambient temperature conditions.
  • maximum stress data are given for these components on an ungrooved substrate and substrates having three groove configurations and several groove sizes. These data show that all three groove configurations - single groove up, single groove down and double grooves up - were effective to reduce residual in-plane thermal stresses in all three components. However, the double groove up configuration was most effective and the single groove up configuration was significantly more effective than the single groove down configuration.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Boîtier micro-électronique comprenant un substrat rigide (1) sur lequel est monté un composant (3) comportant une pluralité de faces ainsi qu'une couche électriquement fonctionnelle (9) adjacente à au moins deux faces du composant (3), le composant (3) et la couche électriquement fonctionnelle (9) étant séparés dans l'espace par une bande de protection (7), le volume du substrat (1) situé au-dessous de la bande de protection (7) présentant au moins une région (13d) de rigidité réduite permettant audit substrat (1) de dissiper les contraintes thermiques générées dans celui-ci lorsque le dispositif est soumis à un chauffage.
PCT/US1991/006627 1990-09-27 1991-09-18 Dispositif micro-electronique composite libere des contraintes thermiques WO1992006495A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002091465A CA2091465A1 (fr) 1990-09-27 1991-09-18 Dispositif microelectronique a joint de dilatation
JP3517867A JPH06503207A (ja) 1990-09-27 1991-09-18 熱的歪み緩和複合超小形電子デバイス

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58893090A 1990-09-27 1990-09-27
US588,930 1990-09-27

Publications (1)

Publication Number Publication Date
WO1992006495A1 true WO1992006495A1 (fr) 1992-04-16

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Application Number Title Priority Date Filing Date
PCT/US1991/006627 WO1992006495A1 (fr) 1990-09-27 1991-09-18 Dispositif micro-electronique composite libere des contraintes thermiques

Country Status (5)

Country Link
EP (1) EP0551395A4 (fr)
JP (1) JPH06503207A (fr)
CN (1) CN1061491A (fr)
CA (1) CA2091465A1 (fr)
WO (1) WO1992006495A1 (fr)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4315160A1 (de) * 1993-05-07 1994-11-17 Bodenseewerk Geraetetech Halterung für Mikrosysteme
WO1997004629A1 (fr) * 1995-07-14 1997-02-06 Olin Corporation Boitier electronique a grille soudee
DE19609929A1 (de) * 1996-03-14 1997-09-18 Ixys Semiconductor Gmbh Leistungshalbleitermodul
EP0865082A1 (fr) * 1995-11-28 1998-09-16 Hitachi, Ltd. Dispositif a semi-conducteur, procede de production de ce dispositif, et substrat encapsule
DE19740330A1 (de) * 1997-09-13 1999-03-25 Bosch Gmbh Robert Trägerplatte für Mikrohybridschaltungen
EP1334647A1 (fr) * 2000-10-20 2003-08-13 Silverbrook Research Pty. Limited Support pour circuits integres
WO2003073500A1 (fr) * 2002-02-28 2003-09-04 Infineon Technologies Ag Substrat pour dispositif a semi-conducteur
EP1410700A1 (fr) * 2000-10-20 2004-04-21 Silverbrook Research Pty. Limited Support de circuit integre a cavites
DE10361106A1 (de) * 2003-12-22 2005-05-04 Infineon Technologies Ag Halbleiterbauteil mit einem Halbleiterchip und einer steifen Umverdrahtungsplatte und Verfahren zur Herstellung derselben
DE102006015241A1 (de) * 2006-03-30 2007-06-28 Infineon Technologies Ag Halbleiterbauteil mit einem Kunststoffgehäuse und teilweise in Kunststoff eingebetteten Außenkontakten sowie Verfahren zur Herstellung des Halbleiterbauteils
US8237260B2 (en) 2008-11-26 2012-08-07 Infineon Technologies Ag Power semiconductor module with segmented base plate
DE102011014584A1 (de) * 2011-03-21 2012-09-27 Osram Opto Semiconductors Gmbh Anschlussträger für Halbleiterchips und Halbleiterbauelement
US9499393B2 (en) 2015-02-06 2016-11-22 Mks Instruments, Inc. Stress relief MEMS structure and package

Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
JP2006300904A (ja) * 2005-04-25 2006-11-02 Matsushita Electric Works Ltd 物理量センサ
JP2011014615A (ja) * 2009-06-30 2011-01-20 Denso Corp センサ装置およびその製造方法
JP2012019034A (ja) * 2010-07-07 2012-01-26 Toyota Motor Corp 半導体パッケージの構造
CN103515347B (zh) * 2012-06-29 2016-05-11 环旭电子股份有限公司 组装结构

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DE4315160A1 (de) * 1993-05-07 1994-11-17 Bodenseewerk Geraetetech Halterung für Mikrosysteme
WO1997004629A1 (fr) * 1995-07-14 1997-02-06 Olin Corporation Boitier electronique a grille soudee
US5952719A (en) * 1995-07-14 1999-09-14 Advanced Interconnect Technologies, Inc. Metal ball grid electronic package having improved solder joint
US6621160B2 (en) 1995-11-28 2003-09-16 Hitachi, Ltd. Semiconductor device and mounting board
EP0865082A1 (fr) * 1995-11-28 1998-09-16 Hitachi, Ltd. Dispositif a semi-conducteur, procede de production de ce dispositif, et substrat encapsule
EP0865082A4 (fr) * 1995-11-28 1999-10-13 Hitachi Ltd Dispositif a semi-conducteur, procede de production de ce dispositif, et substrat encapsule
US6404049B1 (en) 1995-11-28 2002-06-11 Hitachi, Ltd. Semiconductor device, manufacturing method thereof and mounting board
US6563212B2 (en) 1995-11-28 2003-05-13 Hitachi, Ltd. Semiconductor device
DE19609929A1 (de) * 1996-03-14 1997-09-18 Ixys Semiconductor Gmbh Leistungshalbleitermodul
DE19609929B4 (de) * 1996-03-14 2006-10-26 Ixys Semiconductor Gmbh Leistungshalbleitermodul
DE19740330A1 (de) * 1997-09-13 1999-03-25 Bosch Gmbh Robert Trägerplatte für Mikrohybridschaltungen
EP1334647A4 (fr) * 2000-10-20 2006-05-03 Silverbrook Res Pty Ltd Support pour circuits integres
US7402896B2 (en) 2000-10-20 2008-07-22 Silverbrook Research Pty Ltd Integrated circuit (IC) carrier assembly incorporating serpentine suspension
US7974102B2 (en) 2000-10-20 2011-07-05 Silverbrook Research Pty Ltd Integrated circuit carrier assembly
US7919872B2 (en) 2000-10-20 2011-04-05 Silverbrook Research Pty Ltd Integrated circuit (IC) carrier assembly with first and second suspension means
EP1410700A4 (fr) * 2000-10-20 2006-05-03 Silverbrook Res Pty Ltd Support de circuit integre a cavites
EP1334647A1 (fr) * 2000-10-20 2003-08-13 Silverbrook Research Pty. Limited Support pour circuits integres
US7187086B2 (en) 2000-10-20 2007-03-06 Silverbrook Research Pty Ltd Integrated circuit arrangement
US7221043B1 (en) 2000-10-20 2007-05-22 Silverbrook Research Pty Ltd Integrated circuit carrier with recesses
US7470995B2 (en) 2000-10-20 2008-12-30 Silverbrook Research Pty Ltd Integrated circuit (IC) carrier assembly with suspension means
EP1410700A1 (fr) * 2000-10-20 2004-04-21 Silverbrook Research Pty. Limited Support de circuit integre a cavites
WO2003073500A1 (fr) * 2002-02-28 2003-09-04 Infineon Technologies Ag Substrat pour dispositif a semi-conducteur
DE10361106A1 (de) * 2003-12-22 2005-05-04 Infineon Technologies Ag Halbleiterbauteil mit einem Halbleiterchip und einer steifen Umverdrahtungsplatte und Verfahren zur Herstellung derselben
DE102006015241A1 (de) * 2006-03-30 2007-06-28 Infineon Technologies Ag Halbleiterbauteil mit einem Kunststoffgehäuse und teilweise in Kunststoff eingebetteten Außenkontakten sowie Verfahren zur Herstellung des Halbleiterbauteils
US8237260B2 (en) 2008-11-26 2012-08-07 Infineon Technologies Ag Power semiconductor module with segmented base plate
DE102011014584A1 (de) * 2011-03-21 2012-09-27 Osram Opto Semiconductors Gmbh Anschlussträger für Halbleiterchips und Halbleiterbauelement
US9159658B2 (en) 2011-03-21 2015-10-13 Osram Opto Semiconductors Gmbh Connection carrier for semiconductor chips and semiconductor component
US9499393B2 (en) 2015-02-06 2016-11-22 Mks Instruments, Inc. Stress relief MEMS structure and package
US9850123B2 (en) 2015-02-06 2017-12-26 Mks Instruments, Inc. Stress relief MEMS structure and package

Also Published As

Publication number Publication date
JPH06503207A (ja) 1994-04-07
EP0551395A1 (fr) 1993-07-21
EP0551395A4 (en) 1993-08-25
CA2091465A1 (fr) 1992-03-28
CN1061491A (zh) 1992-05-27

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