+

WO1992003848A2 - Empilage de circuits integres - Google Patents

Empilage de circuits integres Download PDF

Info

Publication number
WO1992003848A2
WO1992003848A2 PCT/GB1991/001459 GB9101459W WO9203848A2 WO 1992003848 A2 WO1992003848 A2 WO 1992003848A2 GB 9101459 W GB9101459 W GB 9101459W WO 9203848 A2 WO9203848 A2 WO 9203848A2
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
conductive material
integrated circuit
electrically conductive
plug
Prior art date
Application number
PCT/GB1991/001459
Other languages
English (en)
Other versions
WO1992003848A3 (fr
Inventor
Niko Miaoulis
Original Assignee
Lsi Logic Europe Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Europe Plc filed Critical Lsi Logic Europe Plc
Publication of WO1992003848A2 publication Critical patent/WO1992003848A2/fr
Publication of WO1992003848A3 publication Critical patent/WO1992003848A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • This invention relates to the stacking of a plurality of integrated circuits on top of each other, and also to the product of that process and the intermediate product which forms part of the stack.
  • an integrated circuit comprising a substrate having holes therethrough, said holes being filled with plugs of electrically conductive material which protrude above the surface of the substrate on at least one face of the substrate.
  • the invention also includes a stack of integrated circuits wherein the circuits are spaced from each other by the protruding plugs and are electrically interconnected by one or more such plugs of conductive material.
  • a method of fabricating a wafer for an integrated circuit which comprises the steps of making a hole through a wafer with an electrically insulating surface layer in the hole, and filling the hole with an elect "ically conductive material to form a plug which protrudes above the surface of the wafer on at least one face of the wafer.
  • a method of fabricating a wafer for an integrated circuit comprising the steps of making a well in the wafer with an electrically insulating surface layer, filling the well with a plug of electrically conductive material, grinding the wafer, to remove the wafer material below the well thereby to expose the bottom of the electrically conductive material, and providing a protruding portion of electrically conductive material at at least one end of the plug.
  • Figs. 1 to 5 show the stages in the fabrication of the intermediate product of the invention.
  • Fig. 6 shows a stack of individual integrated circuit chips.
  • the first stage in the fabrication process of a silicon wafer 10 of initial thickness T is the creation of a plurality of deep wells 12 in the silicon wafer. These can be made by a suitable etching or cutting process.
  • the wells 12 can be purpose-designed contact areas or existing bond pad sites, and the depth of the wells will depend upon the desired final wafer thickness.
  • each well 12 is coated with a suitable insulating medium to form an insulating layer 14. If the wells are cut by a laser, with oxygen present, this will form a silicon oxide layer on the surface of the well, and in this case there will be no need for a separate insulating layer 14.
  • the wells 12 are then filled with a suitable electrically conductive material 16, up to the top surface of the wafer, to form a plug.
  • the underside of the wafer 10 is ground away to reduce the wafer to a lesser thickness t. This exposes the conductive material 16 at the back surface of the wafer, as shown in Fig. 4.
  • the back of the wafer is covered by a suitable layer 18 of electrically insulating material and holes are made through this to the electrical contacts which are constituted by the plugs of electrically conductive material 16.
  • the back contact areas are covered by a "bump" of suitable electrically conductive material in order form a protruding pad 20.
  • Each pad 20 contacting the top surf ⁇ ⁇ of the plug of the adjacent chip one has an electrical contact which extends through the plurality of chips and forms a continuous through contact.
  • a suitable wire bond 22 can be connected to the through contact plug.
  • the individual chips can be stacked together after wafer sawing, or a combination of different chips can be combined together.
  • the protruding pad is at the bottom of the wafer, one could alternatively or additionally provide a protruding pad at the upper face of the wafer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Une plaquette de circuits intégrés (10) est pourvue d'une fiche traversante (16), fabriquée à partir d'un matériau électroconducteur, qui fait saillie au-dessus de la surface de la plaquette de sorte que l'on puisse empiler les circuits intégrés afin qu'ils demeurent espacés les uns des autres, mais électriquement interconnectés par les fiches (16) qui s'étendent à travers eux en contact réciproque.
PCT/GB1991/001459 1990-08-28 1991-08-28 Empilage de circuits integres WO1992003848A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB909018766A GB9018766D0 (en) 1990-08-28 1990-08-28 Stacking of integrated circuits
GB9018766.7 1990-08-28

Publications (2)

Publication Number Publication Date
WO1992003848A2 true WO1992003848A2 (fr) 1992-03-05
WO1992003848A3 WO1992003848A3 (fr) 1992-07-23

Family

ID=10681284

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1991/001459 WO1992003848A2 (fr) 1990-08-28 1991-08-28 Empilage de circuits integres

Country Status (2)

Country Link
GB (1) GB9018766D0 (fr)
WO (1) WO1992003848A2 (fr)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994025982A1 (fr) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Structuration de contact pour connexions verticales a puces
WO1994025981A1 (fr) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Procede de fabrication de composants semiconducteurs a interconnexions verticales
EP0693778A3 (fr) * 1994-07-20 1997-01-02 Mitsubishi Electric Corp Dispositif semi-conducteur avec dissipateur de chaleur intégré
WO1998019337A1 (fr) 1996-10-29 1998-05-07 Trusi Technologies, Llc Circuits integres et procedes de fabrication correspondants
EP0851492A3 (fr) * 1996-12-06 1998-12-16 Texas Instruments Incorporated Structure de substrat à montage de surface et méthode
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
EP1233444A3 (fr) * 1992-04-08 2002-12-11 LEEDY, Glenn J. Fabrication de circuit intégré à partir d'une membrane d'isolation diélectrique
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
WO2003003423A1 (fr) 2001-06-29 2003-01-09 Xanoptix, Inc. Procede et appareil a dispositif optique actif a cote superieur
WO2002049107A3 (fr) * 2000-12-13 2003-04-17 Medtronic Inc Procede d'empilement de des semiconducteurs dans un instrument medical implante
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6848177B2 (en) 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
EP1503406A2 (fr) 1996-10-29 2005-02-02 Tru-Si Technologies, Inc. Plots de contact en face arrière d'une puce semiconductrice
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US6908845B2 (en) 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
EP1248295A3 (fr) * 2001-04-06 2005-07-13 Shinko Electric Industries Co. Ltd. Elément semi-conducteur, structure de connection, dispositif semi-conducteur utilisant plusieurs de ces éléments et procédés de fabrication
WO2008005586A3 (fr) * 2006-06-30 2008-02-07 Sony Ericsson Mobile Comm Ab Boîtier de composants de circuit intégré à puces à bosses empilées pour bus de transfert de données à large bande
US8841778B2 (en) 1997-04-04 2014-09-23 Glenn J Leedy Three dimensional memory structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6714625B1 (en) 1992-04-08 2004-03-30 Elm Technology Corporation Lithography device for semiconductor circuit pattern generation
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843554A (ja) * 1981-09-08 1983-03-14 Mitsubishi Electric Corp 半導体装置
US4897708A (en) * 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
US4954875A (en) * 1986-07-17 1990-09-04 Laser Dynamics, Inc. Semiconductor wafer array with electrically conductive compliant material

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1233444A3 (fr) * 1992-04-08 2002-12-11 LEEDY, Glenn J. Fabrication de circuit intégré à partir d'une membrane d'isolation diélectrique
US5767001A (en) * 1993-05-05 1998-06-16 Siemens Aktiengesellschaft Process for producing semiconductor components between which contact is made vertically
WO1994025982A1 (fr) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Structuration de contact pour connexions verticales a puces
WO1994025981A1 (fr) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Procede de fabrication de composants semiconducteurs a interconnexions verticales
US5846879A (en) * 1993-05-05 1998-12-08 Siemens Aktiengesellschaft Contact structure for vertical chip connections
US5864169A (en) * 1994-07-20 1999-01-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including plated heat sink and airbridge for heat dissipation
EP0693778A3 (fr) * 1994-07-20 1997-01-02 Mitsubishi Electric Corp Dispositif semi-conducteur avec dissipateur de chaleur intégré
EP1387401A3 (fr) * 1996-10-29 2008-12-10 Tru-Si Technologies Inc. Circuits intégrés et procédés de fabrication correspondants
EP0948808A4 (fr) * 1996-10-29 2000-05-10 Trusi Technologies Llc Circuits integres et procedes de fabrication correspondants
US6420209B1 (en) 1996-10-29 2002-07-16 Tru-Si Technologies, Inc. Integrated circuits and methods for their fabrication
EP1503406A3 (fr) * 1996-10-29 2009-07-08 Tru-Si Technologies, Inc. Plots de contact en face arrière d'une puce semiconductrice
US6184060B1 (en) 1996-10-29 2001-02-06 Trusi Technologies Llc Integrated circuits and methods for their fabrication
EP1503406A2 (fr) 1996-10-29 2005-02-02 Tru-Si Technologies, Inc. Plots de contact en face arrière d'une puce semiconductrice
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
WO1998019337A1 (fr) 1996-10-29 1998-05-07 Trusi Technologies, Llc Circuits integres et procedes de fabrication correspondants
EP2270845A3 (fr) * 1996-10-29 2013-04-03 Invensas Corporation Circuits intégrés et leurs procédés de fabrication
US6639303B2 (en) 1996-10-29 2003-10-28 Tru-Si Technolgies, Inc. Integrated circuits and methods for their fabrication
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP0851492A3 (fr) * 1996-12-06 1998-12-16 Texas Instruments Incorporated Structure de substrat à montage de surface et méthode
US8841778B2 (en) 1997-04-04 2014-09-23 Glenn J Leedy Three dimensional memory structure
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
WO2002049107A3 (fr) * 2000-12-13 2003-04-17 Medtronic Inc Procede d'empilement de des semiconducteurs dans un instrument medical implante
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
EP1248295A3 (fr) * 2001-04-06 2005-07-13 Shinko Electric Industries Co. Ltd. Elément semi-conducteur, structure de connection, dispositif semi-conducteur utilisant plusieurs de ces éléments et procédés de fabrication
WO2003003423A1 (fr) 2001-06-29 2003-01-09 Xanoptix, Inc. Procede et appareil a dispositif optique actif a cote superieur
EP1410425A4 (fr) * 2001-06-29 2009-12-09 Cufer Asset Ltd Llc Procede et appareil a dispositif optique actif a cote superieur
US7112887B2 (en) 2002-03-28 2006-09-26 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6908845B2 (en) 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6848177B2 (en) 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
WO2008005586A3 (fr) * 2006-06-30 2008-02-07 Sony Ericsson Mobile Comm Ab Boîtier de composants de circuit intégré à puces à bosses empilées pour bus de transfert de données à large bande

Also Published As

Publication number Publication date
WO1992003848A3 (fr) 1992-07-23
GB9018766D0 (en) 1990-10-10

Similar Documents

Publication Publication Date Title
WO1992003848A2 (fr) Empilage de circuits integres
KR100830581B1 (ko) 관통전극을 구비한 반도체 소자 및 그 형성방법
US7525186B2 (en) Stack package having guard ring which insulates through-via interconnection plug and method for manufacturing the same
US6838774B2 (en) Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US6040235A (en) Methods and apparatus for producing integrated circuit devices
US6548391B1 (en) Method of vertically integrating electric components by means of back contacting
US8415807B2 (en) Semiconductor structure and method for making the same
US7099139B2 (en) Integrated circuit package substrate having a thin film capacitor structure
US5804464A (en) Semiconductor chip kerf clear method for forming semiconductor chips and electronic module therefore
US20020163072A1 (en) Method for bonding wafers to produce stacked integrated circuits
US5196377A (en) Method of fabricating silicon-based carriers
US20060202347A1 (en) Through electrode, package base having through electrode, and semiconductor chip having through electrode
US6025277A (en) Method and structure for preventing bonding pad peel back
US20050156330A1 (en) Through-wafer contact to bonding pad
CN102163588B (zh) 半导体装置与其制造方法
JPH0945848A (ja) マルチチップ・スタック用の導電性モノリシックｌ接続を備えたエンドキャップ・チップおよびその製造方法
WO1996002071A1 (fr) Circuit integre encapsule
US6638867B2 (en) Method for forming a top interconnection level and bonding pads on an integrated circuit chip
US8921984B2 (en) Through silicon via in semiconductor device
US6617198B2 (en) Semiconductor assembly without adhesive fillets
US6124149A (en) Method of making stackable semiconductor chips to build a stacked chip module
US6852570B2 (en) Method of manufacturing a stacked semiconductor device
KR102714218B1 (ko) 반도체 패키지
US20060160339A1 (en) Soi contact structure(s) and corresponding production method
CN114334902A (zh) 熔丝结构及形成方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): GB JP US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FR GB GR IT LU NL SE

AK Designated states

Kind code of ref document: A3

Designated state(s): GB JP US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FR GB GR IT LU NL SE

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载