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WO1992002048A1 - Procede de fabrication d'un dispositif a semiconducteur - Google Patents

Procede de fabrication d'un dispositif a semiconducteur Download PDF

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Publication number
WO1992002048A1
WO1992002048A1 PCT/JP1991/000990 JP9100990W WO9202048A1 WO 1992002048 A1 WO1992002048 A1 WO 1992002048A1 JP 9100990 W JP9100990 W JP 9100990W WO 9202048 A1 WO9202048 A1 WO 9202048A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor device
thin film
ferroelectric
electrode
Prior art date
Application number
PCT/JP1991/000990
Other languages
English (en)
Japanese (ja)
Inventor
Akira Fujisawa
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Publication of WO1992002048A1 publication Critical patent/WO1992002048A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Definitions

  • the present invention relates to a method for manufacturing a semiconductor memory element, and more particularly, to a method for manufacturing a non-volatile semiconductor device using an electrically polarizable ferroelectric layer as a substrate.
  • the information is given by applying a voltage to the corresponding electrodes on the upper and lower sides (corresponding to the row and column address in the case of a normal semiconductor device), thereby polarizing the area of intersection of these electrodes. It was able to be memorized.
  • the reading process can be performed, for example, by piezoelectric or pyroelectric activation of a specific memory area or by destructive reading.
  • the residual polarization of the ferroelectric allows information to be retained forever without supplying external power.
  • the peripheral devices that is, the electronic control devices required for writing and reading information, are relatively complicated and require a long access time. Therefore, in the late 70's it was proposed to integrate ferroelectric storage elements directly or together with the control module. (R. C. Cook, U.S. Pat. No. 4,149,302 (1979)).
  • 601 is a P-type silicon substrate
  • 602 is a LOCOS oxide film for element isolation
  • 603 and 604 are N-type diffusion layers serving as a source and a drain, respectively.
  • 605 is a game And reference numeral 606 'denotes an interlayer insulating film.
  • Reference numeral 608 denotes a ferroelectric film, which is sandwiched between a lower electrode 607 and an upper electrode 609 to constitute a capacitor. In such a structure stacked on top of a MOS-type semiconductor device, it is necessary to perform wiring to connect the ferroelectric electrode to the high-concentration diffusion layers that serve as the source and drain on the semiconductor substrate. There is a problem that the element area increases.
  • An object of the present invention is to solve such a problem, and it is an object of the present invention to provide a method for manufacturing a semiconductor device with low cost and high integration. Disclosure of the invention
  • a high concentration diffusion layer of a semiconductor substrate and an electrode formed so as to sandwich the ferroelectric layer are provided. Forming a connection hole for connecting to one of the electrodes;
  • FIG. 1 shows a main cross-sectional view of a semiconductor device based on an electrically polarizable ferroelectric layer according to the present invention.
  • FIG. 2 to FIG. 5 are main cross-sectional views of a manufacturing process of a capacitance element of a semiconductor device using an electrically polarizable ferroelectric layer as a substrate according to the present invention.
  • FIG. 6 shows a main cross-sectional view of a conventional semiconductor device using an electrically polarizable ferroelectric layer as a substrate.
  • FIG. 1 shows a main sectional view of a semiconductor device according to the present invention.
  • 101 is, for example, a P-type Si surface.
  • Reference numeral 102 denotes an N-type high-concentration impurity diffusion layer formed by, for example, an ion implantation method, which serves as a source and a drain of the MOS transistor.
  • Reference numeral 103 denotes a gate oxide film of the MOS transistor, which is formed by, for example, thermal oxidation of a silicon substrate.
  • Reference numeral 104 denotes an LOCOS oxide film for element isolation.
  • Reference numeral 105 denotes a gate electrode formed of, for example, N-type polysilicon.
  • Forming an S i 0 2 with 1 0 6 1 1 0 is the interlayer insulating film, for example chemical vapor deposition.
  • Reference numeral 108 denotes a ferroelectric layer according to the present invention.
  • the material is either P b T i 0 3 of the ferroelectric layer is present invention, PZT, or a PL Zeta T, are suitable amount excessively Ho ⁇ a lead component to its stoichiometric composition It is formed on one electrode (hereinafter, referred to as a lower electrode) sandwiching a capacitor by setting a target to 107 by a sputtering method using a target.
  • the lower electrode 107 is made of, for example, platinum, and is formed by, for example, sputtering.
  • Reference numeral 109 denotes another electrode (hereinafter, referred to as an upper electrode) for the lower electrode of the capacitor, for example, formed by sputtering aluminum.
  • the aluminum layer functions as an upper electrode and is Although it also has a role as a trace, it goes without saying that it may be separated and formed of different materials and layers.
  • the lower electrode of the capacitive element is formed directly on the high-concentration diffusion layer, the wiring area is reduced, and as a result, the element area is small and high integration is possible.
  • FIG. 2 to FIG. 5 are cross-sectional views showing main steps for manufacturing the capacitive element of the semiconductor device of the present invention shown in FIG. 1. A preferred embodiment will be described step by step.
  • connection holes in.
  • the diameter of the connection hole is, for example, 5 / zm
  • the thickness of the S i 0 2 is 2 0 0 0 people.
  • Such connection holes are formed, for example, by patterning a resist on the interlayer insulating film by a photolithographic technique, and then, for example, by etching with an aqueous solution of hydrofluoric acid.
  • platinum 107 serving as a lower electrode is made 100 A by sputtering, for example, and PZT 108 serving as a ferroelectric layer is made 200 0 by sputtering, for example.
  • a photoresist 410 is formed on the ferroelectric thin film 108, for example, a photoresist 410 is formed. Thereafter, a photoresist to be a mask layer is left in a region to be a capacitive element by using photolithography technology.
  • the lower electrode of the capacitive element using a ferroelectric layer as a substrate is formed on the high-concentration diffusion layer of the semiconductor substrate, it has become possible to fabricate a highly integrated nonvolatile semiconductor device. Further, since the lower electrode layer and the ferroelectric layer of the capacitor were patterned at the same time, the process could be simplified.

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  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Dans un dispositif à semiconducteur dans lequel sont formés des éléments de condensateur ayant des couches ferro-électriques servant de substrats, il est possible d'augmenter la densité des éléments, grâce à un trou de connexion formé dans une couche de diffusion (102) à forte concentration, sur laquelle on dépose une électrode (107) et un film ferro-électrique (108) auxquels on donne ensuite simultanément des formes prédéterminées par une technique de photolithographie.
PCT/JP1991/000990 1990-07-24 1991-07-24 Procede de fabrication d'un dispositif a semiconducteur WO1992002048A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2/195860 1990-07-24
JP2195860A JPH0482265A (ja) 1990-07-24 1990-07-24 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
WO1992002048A1 true WO1992002048A1 (fr) 1992-02-06

Family

ID=16348195

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1991/000990 WO1992002048A1 (fr) 1990-07-24 1991-07-24 Procede de fabrication d'un dispositif a semiconducteur

Country Status (3)

Country Link
EP (1) EP0495113A4 (fr)
JP (1) JPH0482265A (fr)
WO (1) WO1992002048A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3161836B2 (ja) * 1992-10-19 2001-04-25 シャープ株式会社 半導体記憶装置
DE69434606T8 (de) * 1993-08-05 2007-05-16 Matsushita Electric Industrial Co., Ltd., Kadoma Halbleiterbauelement mit Kondensator und dessen Herstellungsverfahren
US6544844B2 (en) 1999-10-08 2003-04-08 Macronix International Co., Ltd. Method for forming a flash memory cell having contoured floating gate surface
US6413818B1 (en) 1999-10-08 2002-07-02 Macronix International Co., Ltd. Method for forming a contoured floating gate cell

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251760A (ja) * 1988-03-31 1989-10-06 Seiko Epson Corp 強誘電体記憶装置
JPH0249471A (ja) * 1988-05-27 1990-02-19 Toshiba Corp 半導体装置とその製造方法
JPH02112282A (ja) * 1988-10-21 1990-04-24 Olympus Optical Co Ltd 半導体デバイス

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251760A (ja) * 1988-03-31 1989-10-06 Seiko Epson Corp 強誘電体記憶装置
JPH0249471A (ja) * 1988-05-27 1990-02-19 Toshiba Corp 半導体装置とその製造方法
JPH02112282A (ja) * 1988-10-21 1990-04-24 Olympus Optical Co Ltd 半導体デバイス

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0495113A4 *

Also Published As

Publication number Publication date
EP0495113A1 (fr) 1992-07-22
JPH0482265A (ja) 1992-03-16
EP0495113A4 (en) 1992-11-19

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