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WO1991016765A1 - Interrupteur pour charges inductives - Google Patents

Interrupteur pour charges inductives Download PDF

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Publication number
WO1991016765A1
WO1991016765A1 PCT/CA1991/000130 CA9100130W WO9116765A1 WO 1991016765 A1 WO1991016765 A1 WO 1991016765A1 CA 9100130 W CA9100130 W CA 9100130W WO 9116765 A1 WO9116765 A1 WO 9116765A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
switch
current
power supply
inductive load
Prior art date
Application number
PCT/CA1991/000130
Other languages
English (en)
Inventor
Gyula Eisenbart
John Geerligs
Original Assignee
Nova Corporation Of Alberta
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA002014724A external-priority patent/CA2014724A1/fr
Priority claimed from US07/529,467 external-priority patent/US5072141A/en
Application filed by Nova Corporation Of Alberta filed Critical Nova Corporation Of Alberta
Priority to JP91507459A priority Critical patent/JPH05506342A/ja
Publication of WO1991016765A1 publication Critical patent/WO1991016765A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08146—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in bipolar transistor switches

Definitions

  • the present invention relates to switches and in particular to a switch for use with an inductive load.
  • a switch for an inductive load comprising:
  • a switch for an inductive load having first and second terminals comprising: first semiconductor switch means for connection between said first terminal and a high potential terminal of a power supply; second semiconductor switch means for connection to said second terminal and a low potential terminal of said power supply, said first and second switch means and said inductive load forming a series circuit with said first and second switch means being responsive to control signals to connect and disconnect said first and second terminals to said high potential and low potential terminals respectively; a plurality of first current paths including a first rectifying element and extending from said second terminal to said high potential terminal; a plurality of second current paths including a second rectifying element and extending from said first terminal to said low potential terminal; and means provided in said first and second current path and being connected between said inductive load and said rectifying element for inhibiting reverse recovery current through said respective first and second rectifying elements upon operating of said first and second switch means to disconnect said inductive load from said power supply and for dissipating energy in said switch occurring as a result of said reverse recovery current.
  • the means to inhibit reverse recovery currents is in the form of an inductive element connected in series with the first and second rectifying elements and the means to dissipate energy is in the form of a choke energy path in communication with the current path.
  • the current path includes a plurality of first and second rectifying elements, each of which is connected between the respective terminals in parallel. It is also preferred that the choke energy path includes a third rectifying element and a resistive element connected in series.
  • the semiconductor switches are field effect transistors, and therefore in operation the inductors inhibit reverse recovery current peak through the diodes upon operation of the transistors to connect the load to the power supply for a time period sufficient for the field effect transistors to turn fully on.
  • an inductive circuit comprising: a power supply having a high potential terminal and a low potential terminal; an inductive load; and a switch operable to connect and disconnect said inductive load between said high potential and low potential terminals, said switch including: first semiconductor switch means connected between said first terminal and a high potential terminal of a power supply; second semiconductor switch means connected to said second terminal and a low potential terminal of said power supply, said first and second switch means and said inductive load forming a series circuit with said first and second switch means being responsive to control signals to connect and disconnect said first and second terminals to said high potential and low potential terminals respectively; a plurality of first current paths including a first rectifying element and extending from said second terminal to said high potential terminal; a plurality of second current paths including a second rectifying element and extending from said first terminal to said low potential terminal; and means provided in said first and second current path and being connected between said inductive load and said rectifying element for inhibiting reverse recovery current through said respective first and second rectifying elements upon
  • the present invention provides advantages in that due to the provision of the inductors in the parallel current paths, the peak reverse recovery currents through the diodes are reduced and delayed until the transistors are fully on. This operation reduces the effect of oscillations occurring due to stray inductance and capacitance in the switch on the gate of the transistor switches and reduces the overall oscillation energy in the switch.
  • the resistor and diode in the choke energy paths function as resistive dampers to dissipate energy stored in the current path inductors and oscillation energy rapidly. Furthermore, since peak reverse recovery currents through the diodes in the current paths are reduced and delayed and since the resulting oscillation energy is conveniently dumped by the choke energy paths, power - A -
  • Figure 1 is a schematic of a conventional prior art H- bridge switch
  • Figure 2 is a schematic drawing of the present switch. BEST MODE FOR CARRYING OUT THE INVENTION
  • the switch 10 includes a pair of field effect transistors (FETs) 14, 16 respectively located on opposite sides and connected in series with the inductive load 12.
  • FET 14 has its drain terminal connected to the positive terminal 18 + of a power supply 18 and its source terminal connected to one terminal of the inductive load 12.
  • FET 16 has its drain terminal connected to the other terminal of the load and its source terminal connected to the negative terminal 18 " of the power supply 18.
  • Diode 20 has its anode connected to the negative terminal 18 " and its cathode connected to the one terminal of the inductive load 12.
  • Diode 22 has its anode connected to the other terminal of the inductive load 12 and its cathode connected to the positive terminal 18 + of the power supply 18.
  • Inductors L s representing the stray inductance due to wiring and the lead inductance of the diodes 20, 22 are shown, each inductor L s being in series with one of the diodes.
  • Capacitors C s representing the capacitance of the diodes 20, 22 respectively are also shown, each capacitor C s being in parallel with the diodes and in series with the stray inductance L s .
  • the stray inductance L s and the stray capacitance C s in each leg of the bridge switch 10 form a resonant circuit which rings at its natural frequency when energized.
  • gating signals are supplied to the FETs 14, 16 for a duration T/2 (this being equal to the switch duty cycle) by gate drivers (not shown) so that they conduct. This in turn connects the inductive load 12 between the terminals of the power supply 18.
  • the gating signals are applied to the FETs, the FETs 14, 16 to through a sequence of transitional steps before they reach their fully on condition as will be described below.
  • the gate of the FETs 14, 16 charge and when the gate threshold is reached, the FETs begin to conduct current proportional to the gate charge.
  • the drain to source voltage of each FET begins to fall at a rate primarily determined by the drain to gate capacitance (shown as C g d in Figure 1) and the current capability of the gate driver.
  • the apparent gate capacitance increases as the drain to source voltage approaches the gate to source voltage and the rate of drain voltage change decreases. The drain voltage thus falls to its final fully on value as determined by the load current and the static on-resistance of the FETs.
  • the gating signals are removed from the FETs 14, 16 for a duration T/2.
  • the FETs stop conducting going through the same sequence of transitional steps previously described with respect to FET turn on but in the reverse order.
  • This operation of the FETs 14, 16 isolates the inductive load 12 from the power supply 18.
  • the inductive load 12 generates a voltage across its terminals in an attempt to maintain the current I through itself.
  • the diodes 20, 22 are forward biased by the voltage and conduct allowing current to flow from the negative terminal 18 " to the positive terminal 18 + of the power supply.
  • the stray capacitance C s is effectively removed from the legs of the bridge switch 10 so that energy exchange with the stray inductance L s is minimal.
  • This current through the inductive load 12 decreases by delta I, the same value as above and the process is repeated. If it is desired to increase the current through the load 12, the duty cycle is manipulated appropriately until the desired current level is reached. Once this occurs, the duty cycle is returned to a 50% value so that the FETs 14, 16 remain on and off for equal periods of time. Under this condition, a steady state unidirectional current flows through the inductive load 12 with a small ripple.
  • the gating signals are re-applied to the FETs 14, 16 causing them to turn on following the sequence of transitional steps previously described.
  • the gating signals have been re-applied to the FETs, it is desired to have the diodes effectively removed from the switch 10 and establish an open circuit in the legs of the bridge switch 10.
  • the diodes 20, 22 have conducted during the FET off condition, they hold a residual charge and cannot stop conducting until the charge has been dissipated. During the charge dissipation, the diodes form an effective short circuit.
  • the FETs 14 and 16 are capable of conducting current due to the application of gating signals, two current paths are formed from the positive terminal 18* to the negative terminal 18 " of the power supply.
  • the first current path is constituted by FET 14 and diode 20 while the other current path is constituted by diode 22 and FET 16. This of course allows a large reverse recovery current to flow through the FETs 14 and 16 respectively. As the charge is removed from the diodes 20, 22, the reverse recovery current through the diodes falls rapidly to zero.
  • the FETs 14, 16 are capable of carrying their full rated current within less than 100 nanoseconds (ns) while the diodes 20, 22 begin to turn off. At this time, the drain of the FETs is still high and within 50ns after the load current has been taken by the FETs, the reverse recovery current through the diodes 20, 22 collapses due to the removal of the residual charge.
  • the present switch shown in Figure 2 is provided and is generally indicated by reference numeral 100.
  • the switch 100 includes a pair of field effect transistors (FETs) Qi and Q 2 located on opposite sides and connected in series with an inductive load 102 such as a magnetic bearing.
  • FET Q-] has its drain terminal Di connected to a positive source conductor 104.
  • the source terminal S T of the FET Q- ⁇ is connected to a conductor 106 which extends to one terminal L-) of the inductive load 102.
  • a conductor 108 extends from the other terminal L 2 of the inductive load 102 and is connected to the drain terminal D 2 of FET Q 2 .
  • the source terminal S 2 of the FET Q 2 is connected to a negative source conductor 110.
  • the gate terminals G-] and G 2 of the FETs Q T and Q 2 respectively are connected to a gate driver 112, each driver of which receives gate driving signals from a controller 114 via a fibre optic cable 116.
  • a plurality of parallel current paths 120 extend between the conductor 106 and the negative source conductor 110.
  • Each current path 120 includes an inductor 122 and a free-wheeling diode 124 connected in series.
  • the diodes 124 and inductors 122 are arranged so that the anode of each diode 124 is connected to conductor 110 and the cathode of each diode is connected to one terminal of the inductor 122.
  • the other terminal of the inductors 122 are connected to conductor 106.
  • a choke energy path 126 is associated with each current path 120 and includes a diode 128 connected in series with a resistor 130.
  • each choke energy path The diode 128 and resistor 130 in each choke energy path are arranged so that the anode of the diode is connected to its associated current path 120 at the junction of the inductor 122 and the diode 124.
  • the cathode of each diode 128 is connected to one terminal of the resistor 130 while the other terminal of the resistors 130 are connected to conductor 104.
  • a plurality of current paths 132 extend between the conductor 108 and the positive source conductor 104.
  • Each of the current paths 132 also includes an inductor 134 connected in series with a free-wheeling diode 136.
  • the diodes 136 and inductors 134 are arranged so that the anode of each diode 136 is connected to one terminal of the inductor 134 and the cathode of each diode is connected to conductor 104.
  • the other terminal of the inductors 134 are connected to conductor 108.
  • a choke energy path 138 is associated with each of the current paths 132 and includes a diode 140 connected in series with a resistor 142.
  • each choke energy path 138 The diode 140 and resistor 142 in each choke energy path 138 are arranged so that the cathode of the diode 140 is connected to its associated current path 132 at the junction of the inductor 134 and the diode 136.
  • the anode of each diode 140 is connected to one terminal of the resistor 142 while the other terminal of the resistor 142 is connected to conductor 110.
  • the positive or high potential terminal E + of a power suppl E is connected to the positive source conductor 104 while the negative or low potential terminal E " of the power supply E is connected to the negative source conductor 110 via power supply bars (not shown) .
  • ESR equivalent series resistance
  • ESL low equivalent series inductance
  • the controller 114 When it is desired to energize the inductive load 102, the controller 114 generates gate driving commands for both FETs Qi and Q 2 which are conveyed to the drivers 112 via the optical fibers 116.
  • the gate drivers 112 in turn supply gating signals to their respective FETs so that the FETs Q-
  • the gating signals are supplied to each FET for a duration T/2, assuming that the switch is operated at a 50% duty cycle.
  • the FETs Q- and Q 2 reach their fully on condition, the FETs provide a closed circuit between their respective drain and source terminals thereby connecting the inductive load 102 between the positive and negative terminals of the power supply E via the conductors 104, 106, 1O8 and 110. This of course permits current to flow between the power supply terminals in the direction of arrow 144 thereby energizing the inductive load.
  • the controller 114 removes the gate driving commands. This of course causes the gate bias applied to the gate terminals of the FETs d and Q 2 by the drivers 112 to be removed. Once the gate bias has been removed, the FETs d and Q 2 cease conducting and establish an open circuit between their respective source and drain terminals in the manner previously described for FETs 14 and 16.
  • the inductive load Once the FETs Q-. and Q 2 isolate the inductive load 102 from the power supply E, the inductive load generates a voltage across its terminals to attempt to maintain the current through itself. Once the voltage is generated by the inductive load, the diodes 124, 136 in each of the two sets of current paths 120, 132 respectively conduct so that current is applied back to the positive terminal E + . The current applied back to the power supply E decreases in the manner previously described with respect to the conventional switch.
  • the inductors 122, 134 are provided in the current paths 132.
  • a current is established in each of the inductors 134 in the direction of arrow 146.
  • the inductors 134 function to generate a voltage across its terminals in an attempt to maintain the current through themselves in the direction of arrow 146. This initial voltage generated by the inductors 134 inhibits the reverse recovery current flow through the current paths.
  • the reverse recovery current peak can be delayed until the FETs Q-, and Q 2 are substantially in their fully on condition.
  • each inductor 122, 134 limits the rate of change of current through the diodes 124, 136 and thus, the peak reverse recovery current through each diode 124, 136 is reduced. This decreases power dissipation in the FETs Qi and Q 2 and hence the switch 100.
  • the peak reverse recovery current flow in the switch 100 is delayed until the FETs Q- ⁇ and Q 2 are fully on, the effect of oscillations on the gates of the FETs is greatly diminished.
  • the provision of the multiple current paths connected in parallel reduces further the stray inductance in the switch 100 and thus, reduces oscillation energy in the switch resulting due to strays.
  • the choke energy paths 126, 138 are provided.
  • the choke energy paths conveniently dump the energy stored in the inductors 122, 134 into the resistors 130, 142 via the fast low capacitance diodes 128, 140 respectively.
  • the choke energy paths function as resistive dampers which minimize oscillations occurring in the resonant circuits formed due to strays.
  • the present switch has been found to be capable of handling currents in excess of 50 amperes through an inductive load in the form of a magnetic bearing while connected to a 160 volt power supply E and while operating at a switching rate of 40 KHz yet only requiring an inexpensive air cooling system.
  • the present switch provides advantages in that since the reverse recovery currents in the switch are inhibited and since the peak reverse recovery current is delayed until the FETs reach a fully on condition, power dissipation in the switch is reduced. This permits the switch to be operated at switching rates exceeding conventional switching rates while only requiring an air cooling system. Moreover, since the multiple current drains reduce stray inductance and peak reverse currents, oscillation energy in the switch is reduced.
  • each FET being located in one leg of the bridge switch 100, it should be realized that a plurality of FETs arranged in parallel with their drain terminals interconnected to form a single input terminal and with their source terminals interconnected to form a single output terminal may be used. This parallel arrangement of FETs is particularly suitable in high power applications. In the case where two sets of parallel FETs are used, the drivers 112 supply gating signals to each FET in the set.
  • switch has been described with respect to a switch for a magnetic bearing it will be appreciated that the switch is also applicable to other applications are constrained by difficult inductive loads.
  • present switch has been described as using FETs, it should be apparent to those of skill in the art that other semiconductor switches such as bipolar junction transistors (BJTs) and the like may be used. It should also be apparent to those of skill in the art that modifications and variations may be made to the present invention without departing from the scope thereof as defined by the appended claims.

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  • Electronic Switches (AREA)

Abstract

Un interrupteur pour une charge inductive comprend une première branche munie d'un premier transistor à effet de champ (Q1) relié entre une borne (L1) de la charge (102) et une borne haute tension (E+) d'une alimentation, et une deuxième branche comportant un deuxième transistor à effet de champ (Q2) relié entre l'autre borne (L2) de la charge (102) et la borne basse tension (E-) de l'alimentation. Une pluralité de chemins de courant (136) situés de part et d'autre des bornes de charge (L1, L2) sont reliés en parallèle et s'étendent depuis une borne de charge (L1, L2) à l'une des bornes d'alimentation (E-, E+). Chaque chemin de courant comprend un inducteur (122, 134) relié en série avec une diode (124, 136). Un chemin d'énergie de réactance est associé à chaque chemin de courant et comprend une diode (128, 140) reliée en série avec des résistances (130, 142). Les inducteurs (122, 134) disposés dans les chemins de courant inhibent le courant de rétablissement inverse à travers les diodes (124, 136), tandis que les chemins d'énergie de réactance dissipent l'énergie d'oscillation dans l'interrupteur dès que les transistors sont activés pour effectuer le branchement de la charge inductive aux bornes de l'alimentation.
PCT/CA1991/000130 1990-04-17 1991-04-12 Interrupteur pour charges inductives WO1991016765A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP91507459A JPH05506342A (ja) 1990-04-17 1991-04-12 誘導負荷用スイッチ

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CA002014724A CA2014724A1 (fr) 1990-04-17 1990-04-17 Commutateur pour charges inductives
CA2,014,724 1990-04-17
US07/529,467 US5072141A (en) 1990-05-29 1990-05-29 High speed high power H-bridge switch for inductive loads
US529,467 1990-05-29

Publications (1)

Publication Number Publication Date
WO1991016765A1 true WO1991016765A1 (fr) 1991-10-31

Family

ID=25674073

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA1991/000130 WO1991016765A1 (fr) 1990-04-17 1991-04-12 Interrupteur pour charges inductives

Country Status (4)

Country Link
EP (1) EP0525042A1 (fr)
JP (1) JPH05506342A (fr)
AU (1) AU7678091A (fr)
WO (1) WO1991016765A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6919651B2 (en) 2002-11-26 2005-07-19 Siemens Aktiengesellschaft Circuit arrangement for high-speed switching of inductive loads
US7019579B2 (en) 2002-11-13 2006-03-28 Siemens Aktiengesellschaft Circuit arrangement for rapidly controlling in particular inductive loads
US7098652B2 (en) 2001-11-07 2006-08-29 Siemens Aktiengesellschaft Analytical circuit for an inductive sensor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2087110A1 (fr) * 1992-01-14 1993-07-15 Hiroshi Tsushima Procede de formation de motifs de couleur

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3237220A1 (de) * 1981-10-07 1983-05-26 Mitsubishi Electric Corp Inverter
DE3639495A1 (de) * 1986-11-20 1988-05-26 Licentia Gmbh Beschaltung der schalter von pulswechselrichtern und gleichstrom-halbleiterstellern fuer den mehrquadrantenbetrieb
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3237220A1 (de) * 1981-10-07 1983-05-26 Mitsubishi Electric Corp Inverter
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge
DE3639495A1 (de) * 1986-11-20 1988-05-26 Licentia Gmbh Beschaltung der schalter von pulswechselrichtern und gleichstrom-halbleiterstellern fuer den mehrquadrantenbetrieb

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098652B2 (en) 2001-11-07 2006-08-29 Siemens Aktiengesellschaft Analytical circuit for an inductive sensor
US7019579B2 (en) 2002-11-13 2006-03-28 Siemens Aktiengesellschaft Circuit arrangement for rapidly controlling in particular inductive loads
US6919651B2 (en) 2002-11-26 2005-07-19 Siemens Aktiengesellschaft Circuit arrangement for high-speed switching of inductive loads

Also Published As

Publication number Publication date
AU7678091A (en) 1991-11-11
EP0525042A1 (fr) 1993-02-03
JPH05506342A (ja) 1993-09-16

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