WO1991009422A1 - Procede de fabrication de films isolants sans craquelures avec couche intermediaire en verre sog - Google Patents
Procede de fabrication de films isolants sans craquelures avec couche intermediaire en verre sog Download PDFInfo
- Publication number
- WO1991009422A1 WO1991009422A1 PCT/CA1990/000448 CA9000448W WO9109422A1 WO 1991009422 A1 WO1991009422 A1 WO 1991009422A1 CA 9000448 W CA9000448 W CA 9000448W WO 9109422 A1 WO9109422 A1 WO 9109422A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- deposited
- sog
- dielectric
- spin
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000011229 interlayer Substances 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000002131 composite material Substances 0.000 claims abstract description 18
- 238000005336 cracking Methods 0.000 claims abstract description 16
- 239000011521 glass Substances 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 117
- 239000000463 material Substances 0.000 claims description 19
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- 230000006835 compression Effects 0.000 claims description 10
- 238000007906 compression Methods 0.000 claims description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 10
- 229910000838 Al alloy Inorganic materials 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 6
- 238000005334 plasma enhanced chemical vapour deposition Methods 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 206010010144 Completed suicide Diseases 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910020211 SiOxHy Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001182 laser chemical vapour deposition Methods 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 229910052745 lead Inorganic materials 0.000 claims 2
- 239000013307 optical fiber Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 28
- 235000012431 wafers Nutrition 0.000 description 15
- 210000000009 suboesophageal ganglion Anatomy 0.000 description 11
- -1 Siloxanes Chemical class 0.000 description 7
- 238000000576 coating method Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 5
- 150000004760 silicates Chemical class 0.000 description 5
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000009833 condensation Methods 0.000 description 3
- 230000005494 condensation Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000178 monomer Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 231100000572 poisoning Toxicity 0.000 description 2
- 230000000607 poisoning effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910008051 Si-OH Inorganic materials 0.000 description 1
- 229910006358 Si—OH Inorganic materials 0.000 description 1
- 239000002318 adhesion promoter Substances 0.000 description 1
- 150000001298 alcohols Chemical class 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052909 inorganic silicate Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/02—Optical fibres with cladding with or without a coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates to method of making crack-free insulating films comprising a Spin-on glass (SOG) layer, and insulating films made thereby.
- SOG Spin-on glass
- SOG Spin-on glasses
- monomers are polymerized by condensation and release water, solvent, and alcohol.
- the condensed material is a thin solid film having mechanical, chemical and electrical properties which depend on the starting composition, and the coating and curing process. A good starting solution can give bad results if the coating and curing sequence is not optimized.
- Siloxanes methyl-, ethyl-, phenyl-, butyl-, doped or undoped
- Planarization is the filling in of the trenches and crevices formed when a plurality of layers, some of which might be subsequently etched back, are deposited on a substrate. Planarization is used over polysilicon, refractory metals, polycides, suicides, aluminum and aluminum alloys, copper, and gold or otehr conductive materials. The main goal is to smooth/eliminate steps and enhance step coverage by the dielectrics and interconnects. Planarization technology becomes increasingly important when the scale of integrated circuits is in the micron and submicron region. Of the many dielectric planarization techniques, SOG planarization is a particularly attractive method; it is relatively simple, economical and is capable of high throughput.
- the quasi-inorganic siloxane SOGs have a more flexible structure due to the presence of organic radicals, which prevent complete cross-linking of the SiOxCyHz matrix under condensation, the organic radicals are not stable at high temperatures and are not compatible with oxygen plasma photoresist strippers (which tend to transform the quasi- inorganic SOG to a purely inorganic SOG by burning the organic bonds and producing volatile species like H 2 0, C ⁇ OyH z , and silanol Si-OH) .
- These two drawbacks limit the use of the quasi-inorganic siloxanes as an alternative to the silicates.
- SOG planarization can take three forms:
- Total etchback and partial etchback processes for planarization of dielectrics over aluminum use photoresist, polyimide, or flexible quasi-inorganic SOGs. In those two cases, cracking of the dielectric sandwich does not occur since most of the planarizing material is removed from the wafer.
- Non-etchback silicate SOG planarization of dielectrics over polysilicon, polycides, refractory metals or silicides has been used for about three years. This technique is not particularly demanding on the dielectric sandwich because the coefficient of thermal expansion of the materials is much lower than for aluminum and aluminum alloys. The dielectric sandwich does not normally crack over those materials.
- Non-etchback SOG planarization of dielectrics over aluminum alloys is an extremely new process in the semiconductor industry.
- purely inorganic SOG form dielectric sandwiches which are prone to very bad cracking. Consequently, more flexible quasi-organic SOGs have been tried, but this approach has proved to be questionable because of a serious field inversion problem due to the effect of the hydrogen contained in the organic bonds of the quasi-inorganic SOGs on the characteristics of CMOS semiconductor devices.
- SOG film properties are of prime importance. Since SQG is generally a more porous material, when compared to LPCVD, APCVD, LACVD, PACVD or PECVD oxides, it is more prone to water absorption. This water absorption reduces the bulk resistivity of the SOG and increases the power consumption of the semiconductor device due to current leakage between adjacent tracks of interconnect. For this reason, among others, SOG must not come into direct contact with the tracks and must be sandwiched between two denser LPCVD, APCVD, LACVD, PACVD or PECVD dielectric films.
- the present invention provides in a method of fabricating a composite insulating film comprising first and second layers with intermediate spin-on glass zones acting as a planarization interlayer for said first layer, at least said first layer being a dielectric layer, the improvement wherein the first layer is formed under compression to prevent cracking in the composite film during subsequent heat treatment.
- the second layer can either be a second dielectric layer, or where, in the case of semiconductor fabrication, an interconnect layer is applied directly over the first and SOG layers, the second layer can be the interconnect layer.
- the method may be applied to the fabrication of a semiconductor device wherein a first dielectric layer is applied over an interconnect layer having tracks defining a conductive pattern and made of material having a high coefficient of expansion, the first dielectric layer forming valleys between the tracks of the interconnect layer, spin-on glass is applied over said first layer to planarize it by forming spin-on glass zones in the valleys defined by the first dielectric layer, and a second layer is applied to the planarized first layer, whereby said first and second layers and said spin-on glass zones form a composite multi-layer film.
- the first layer is formed under compression to prevent cracking in the composite multi ⁇ layer film during subsequent heat treatment.
- Figures la to lh illustrate the steps in the manufacture of a composite insulating film with a SOG interlayer.
- a layer of aluminum interconnect material 1 (Fig. la) is deposited on a substrate and then patterned using photolithography (Fig. lb) .
- a first layer of dielectric 2 is deposited over the etched interconnect tracks (Fig. lc) and a an inorganic (silicate) spin-on glass (SOG) layer 3 is applied (with or without etchback) to fill the valleys and crevices (Fig. Id) .
- the SOG is a proprietary composition and can be obtained from a number of sources such as Allied Signal Inc, Milpitas, California. Being liquid, the SOG is almost absent over the peaks la and provides good planarization for the first dielectric layer 2.
- a second dielectric layer 4 is then applied over the first layer 2 and SOG interlayer 3 (Fig., le) . Contacts holes are then etched away to reach the tracks of the first layer of interconnect material 1 (fig. If) .
- a second level of interconnect material 5 is deposited over the etched second layer 4 (fig If) and is patterned using photolithography to form the desired conductive tracks 5a (Fig. lh) .
- Such dielectric sandwiches containing dense purely inorganic (silicate) SOG crack during the subsequenet heat treatments which are needed to cure and stabilize the SOG and the aluminum alloys.
- Thin film stress can be compressive or tensile.
- a compressive stress when too excessive, results in delamination, formation of waves and ripples.
- a film in compression does not crack. In fact, a film in compression stops the propagation of cracks.
- a tensile stress when too excessive, results in crack formation and propagation.
- a stressed film When a stressed film is deposited on a substrate, it induces a mechanical bow of that substrate.
- the bow direction and its magnitude is related to the stress type (tensile or compressive) , and its intensity. If the film is in tension, the substrate bows in such a way that the film is present on the concave face. Similarly, if the film is under compression the substrate bows in such a way that the film is present on the convex face.
- the stress nature of a given thin film can then be measured by the change of curvature induced in a (100) Si single crystal wafer, due to the deposited film.
- the wafer can be scanned before and after the deposition to obtain the net change or wafer radius of curvature.
- the film stress " ⁇ " is calculated using the following expression:
- M E is the Young's modulus of Si (100) wafer
- rr is its Poisson's ratio
- t is the wafer thickness
- r is the measured net radius of curvature
- r is the film thickness
- the SOG stress obtained is not excessively high but the obtained material is very rigid. Although it was not possible to measure the actual coefficient of thermal expansion of the obtained SOG, the appearance of cracks at high temperature in the dielectric sandwich PSG/SOG/PSG (PSG stands for a 4.0 wt% phosphorus doped LPCVD Si0 film which is under a tensile stress of 0.5 - 3.0 x 10 9 dyne/cm 2 , up to four times higher than SOG), deposited over metal tracks of the first level of interconnect, and the absence of cracks in the dielectric sandwich PSG/PSG deposited over equivalent metal tracks, indicates that the SOG has a much smaller coefficient of thermal expansion than PSG.
- the dielectric sandwich cracking has been substantially eliminated with a special combination of film stresses.
- the first dielectric layer 1 deposited over the aluminum and under the SOG film must be under compressive stress. In this case, the heat treatments that cause expansion of the aluminum will tend to bring the dielectric under tension. But since the dielectric is already in compression, its stress will stabilize at an almost negligible value. A stress of about 5 x 10 8 to 3 x 10 9 dyne/cm 2 is preferred and its exact value depends on the difference of the coefficient of thermal expansion between the aluminum alloy and the dielectrics used in the sandwich.
- the SOG layer has a stress that is slightly tensile at about 6 - 8 x 10 8 dynes/cm 2 .
- the last dielectric layer 4 deposited over the SOG layer 3 and under the second interconnect layer 5 can be under compressive or tensile stress, but a tensile stress is preferred to compensate for the wafer bow generated by the first dielectric.
- a stress of about 5 x 10 8 to 3 x 10 9 dyne/cm 2 is preferred.
- the described method is very important because it permits a non-etchback high quality purely inorganic SOG process to be applied to high coefficient of thermal expansion materials, such as aluminum alloys.
- PECVD Plasma Enhanced Chemical Vapour Deposition
- LACVD Laser Assisted Chemical Vapour Deposition
- the deposited compressive material under the SOG can be:
- the layer 4 over the SOG layer 3 need not be under tension but also can be under compression.
- the SOG can be of many types.
- the crack prevention effect is much more pronounced with low coefficient of thermal expansion inorganic (silicates) SOGs.
- the interconnect material under the SOG can be other than aluminum or aluminum alloy.
- it can be a metal such as W, Mo, Ta, Co, Ti; or a reacted metal such as Ti x Ny, Ti x Wy, Ti x 0 v Z 2 , Ti x W v N 2 .
- It can also be a suicide of W, Mo, Ta, Co, Ti, Pt.
- the upper part of the dielectric sandwich can be omitted and the second metal layer 5 directly deposited over the SOG layer 3 and first dielectric layer 2.
- the described process has many applications. In particular, it can be applied to other steps in the manufacture of integrated circuits, such as:
- the process may be useful in the fabrication of:
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Optics & Photonics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Le procédé décrit, qui sert à la fabrication de dispositifs à semi-conducteurs, consiste à appliquer une première couche diélectrique sur une couche d'interconnexion comportant des sillons définissant une structure conductrice, la première couche diélectrique formant des vallées entre les sillons de la couche d'interconnexion, à appliquer du verre de dépôt par rotation (verre SOG) sur cette première couche pour la rendre plane par la formation de zones en verre SOG dans les vallées définies par la première couche diélectrique, et à appliquer une seconde couche sur la première couche rendue plane, de façon à ce que les première et seconde couches et les zones en verre SOG forment un film multicouche composite. La première couche est conçue de façon à exercer des contraintes de compression à la température ambiante, de façon à empêcher toute apparition de craquelures dans le film multicouche composite lors d'un traitement thermique ultérieur. La seconde couche peut être constituée par une autre couche diélectrique ou par une autre couche d'interconnexion appliquée directement sur la première couche et sur la couche d'aplanissement en verre SOG. Ce procédé peut également s'appliquer dans d'autres domaines, tels que la fabrication de fibres optiques, de diodes électroluminescentes et similaires.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA 2006174 CA2006174A1 (fr) | 1989-12-20 | 1989-12-20 | Methode de fabrication de films isolants sans craquelures au moyen de couches intermediaires de verre de spin |
CA2,006,174 | 1989-12-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1991009422A1 true WO1991009422A1 (fr) | 1991-06-27 |
Family
ID=4143846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CA1990/000448 WO1991009422A1 (fr) | 1989-12-20 | 1990-12-19 | Procede de fabrication de films isolants sans craquelures avec couche intermediaire en verre sog |
Country Status (2)
Country | Link |
---|---|
CA (1) | CA2006174A1 (fr) |
WO (1) | WO1991009422A1 (fr) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1993004501A1 (fr) * | 1991-08-14 | 1993-03-04 | Mitel Corporation | Procede performant de passivation pour dispositifs a semi-conducteur |
US5364818A (en) * | 1990-05-29 | 1994-11-15 | Mitel Corporation | Sog with moisture resistant protective capping layer |
US5371046A (en) * | 1993-07-22 | 1994-12-06 | Taiwan Semiconductor Manufacturing Company | Method to solve sog non-uniformity in the VLSI process |
EP0655776A1 (fr) * | 1993-11-30 | 1995-05-31 | STMicroelectronics S.r.l. | Procédé d'autoplanarisation pour la passivation d'un circuit intégré |
EP0678914A3 (fr) * | 1994-04-18 | 1997-02-19 | Advanced Micro Devices Inc | Procédé de planarization d'un circuit intégré. |
EP0851480A3 (fr) * | 1996-12-25 | 1998-07-29 | Canon Sales Co., Inc. | Procédé de fabrication d'un film isolant à tension réglée, dispositif semiconducteur et son procédé de fabrication |
KR100914443B1 (ko) * | 2007-09-04 | 2009-08-28 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
JP2016061718A (ja) * | 2014-09-19 | 2016-04-25 | 株式会社デンソー | 半導体物理量センサおよびその製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0046059A2 (fr) * | 1980-08-08 | 1982-02-17 | Fujitsu Limited | Procédé de dépôt chimique de films, en phase vapeur, à l'aide d'un plasma |
WO1987002828A1 (fr) * | 1985-11-04 | 1987-05-07 | Motorola, Inc. | Dielectrique intermetallique en verre |
-
1989
- 1989-12-20 CA CA 2006174 patent/CA2006174A1/fr not_active Abandoned
-
1990
- 1990-12-19 WO PCT/CA1990/000448 patent/WO1991009422A1/fr unknown
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0046059A2 (fr) * | 1980-08-08 | 1982-02-17 | Fujitsu Limited | Procédé de dépôt chimique de films, en phase vapeur, à l'aide d'un plasma |
WO1987002828A1 (fr) * | 1985-11-04 | 1987-05-07 | Motorola, Inc. | Dielectrique intermetallique en verre |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5364818A (en) * | 1990-05-29 | 1994-11-15 | Mitel Corporation | Sog with moisture resistant protective capping layer |
WO1993004501A1 (fr) * | 1991-08-14 | 1993-03-04 | Mitel Corporation | Procede performant de passivation pour dispositifs a semi-conducteur |
US5541445A (en) * | 1991-08-14 | 1996-07-30 | Mitel Corporation | High performance passivation for semiconductor devices |
US5371046A (en) * | 1993-07-22 | 1994-12-06 | Taiwan Semiconductor Manufacturing Company | Method to solve sog non-uniformity in the VLSI process |
EP0655776A1 (fr) * | 1993-11-30 | 1995-05-31 | STMicroelectronics S.r.l. | Procédé d'autoplanarisation pour la passivation d'un circuit intégré |
EP0678914A3 (fr) * | 1994-04-18 | 1997-02-19 | Advanced Micro Devices Inc | Procédé de planarization d'un circuit intégré. |
EP0851480A3 (fr) * | 1996-12-25 | 1998-07-29 | Canon Sales Co., Inc. | Procédé de fabrication d'un film isolant à tension réglée, dispositif semiconducteur et son procédé de fabrication |
KR100914443B1 (ko) * | 2007-09-04 | 2009-08-28 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
JP2016061718A (ja) * | 2014-09-19 | 2016-04-25 | 株式会社デンソー | 半導体物理量センサおよびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CA2006174A1 (fr) | 1991-06-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5506177A (en) | Fabrication process for multilevel interconnections in a semiconductor device | |
US5607773A (en) | Method of forming a multilevel dielectric | |
EP1109221B1 (fr) | Structure d'interconnexions de type damascène et son procédé de réalisation | |
US6734562B1 (en) | Integrated circuit device structure including foamed polymeric material | |
KR100358545B1 (ko) | 반도체 장치 및 그 제조 공정 | |
US5753967A (en) | Damascene process for reduced feature size | |
KR900004264B1 (ko) | 스핀-온 그라스를 쎄크리휘셜층으로 사용하는 2중금속층 mos의 평탄화 방법 | |
US6040628A (en) | Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics | |
KR100354649B1 (ko) | 저유전율 층간절연막을 갖는 반도체장치 및 그 제조방법 | |
EP0822586A2 (fr) | Améliorations relatives aux circuits intégrés | |
WO1991012630A1 (fr) | Technique de traitement de verre depose par rotation utile pour fabriquer des dispositifs semi-conducteurs | |
CN1672250A (zh) | 改进的beol互连结构中的双层hdpcvd/pe cvd帽层及其方法 | |
JPH07312368A (ja) | 絶縁膜の平坦化構造を形成するための方法 | |
CN1114943C (zh) | 半导体器件及其制造方法 | |
US20090166817A1 (en) | Extreme low-k dielectric film scheme for advanced interconnects | |
US5898221A (en) | Semiconductor device having upper and lower wiring layers | |
KR20050013492A (ko) | 구리/낮은 k 상호 접속 구조를 위해 개선된 화학적평탄화 성능 | |
US6054769A (en) | Low capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials | |
US5716888A (en) | Stress released VLSI structure by void formation | |
WO1991009422A1 (fr) | Procede de fabrication de films isolants sans craquelures avec couche intermediaire en verre sog | |
JP3054637B2 (ja) | 集積回路のパッシベーション方法 | |
US5930677A (en) | Method for reducing microloading in an etchback of spin-on-glass or polymer | |
US5942801A (en) | Borderless vias with HSQ gap filled metal patterns having high etching resistance | |
JP2000223573A (ja) | 平坦なレベル間誘電体層を有する集積回路素子 | |
US5821162A (en) | Method of forming multi-layer wiring utilizing SOG |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): GB JP KR US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB GR IT LU NL SE |
|
CFP | Corrected version of a pamphlet front page | ||
CR1 | Correction of entry in section i |
Free format text: IN PAT.BUL.14/91,UNDER INID (30) PRIORITY DATA REPLACE "006174" BY "2006174" |