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WO1990011619A1 - Mosfet a une seule tranchee-cellule de condensateur pour le traitement de signaux analogiques - Google Patents

Mosfet a une seule tranchee-cellule de condensateur pour le traitement de signaux analogiques Download PDF

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Publication number
WO1990011619A1
WO1990011619A1 PCT/US1990/000240 US9000240W WO9011619A1 WO 1990011619 A1 WO1990011619 A1 WO 1990011619A1 US 9000240 W US9000240 W US 9000240W WO 9011619 A1 WO9011619 A1 WO 9011619A1
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WO
WIPO (PCT)
Prior art keywords
trench
layer
transistor
doped
recited
Prior art date
Application number
PCT/US1990/000240
Other languages
English (en)
Inventor
Allen L. Solomon
Original Assignee
Grumman Aerospace Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Grumman Aerospace Corporation filed Critical Grumman Aerospace Corporation
Publication of WO1990011619A1 publication Critical patent/WO1990011619A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Definitions

  • the present invention finds application in connection with thin silicon plates or wafers formed to support a multiplicity of monolithically integrated data processor circuits. More particularly, the invention is directed to the production of circuits formed on silicon wafers for interfacing devices such as infrared detector elements to a processing network that amplifies, stores and interprets detected infrared frequency signals.
  • the infrared spectrum covers a range of wavelengths longer than the visible wavelengths, but shorter than microwave wavelengths. Visible wavelengths are generally regarded as between 0.4 and 0.75 micrometers. The infrared wavelengths extend from 0.75 micrometers to 1 millimeter.
  • the function of infrared detectors is to respond to the energy of a wavelength within some particular portion of the infrared region. Heated objects generate radiant energy having characteristic wavelengths within the infrared spectrum.
  • Many current infrared image detection systems incorporate arrays with large numbers of discrete, highly sensitive detector elements, the electrical outputs of which are connected to processing circuitry. By analyzing the pattern and sequence of detector element excitation, the processing circuitry can identify and track sources of infrared radiation.
  • Contemporary arrays of detectors may be sized to include 256 detector elements on a side, or a total of 65,536 detectors, the size of each square detector being approximately 0.009 centimeters on a side, with 0.00116 centimeters spacing between detectors. Such a subarray would therefore be 2.601 centimeters on a side. Interconnection of such a subarray to processing circuitry would require connecting each of the 65,536 detectors to processing circuitry within a square, a little more than one inch on a side. Each subarray may, in turn, be joined to other subarrays to form an array that connects to 25,000,000 detectors or more.
  • 1/f noise A type of noise that is particularly significant where the preamplifier operates at low frequency is commonly called flicker or 1/f noise. Because 1/f noise can be the principal noise component at low frequencies of operation, it is highly desirable that circuits operating within such frequencies be constructed in such a manner as to decrease 1/f noise to an acceptably low level.
  • Reduction of 1/f noise in the preamplifier, where the preamplifier transistor is a field effect device, is conventionally obtained by increasing the area of the channel region under the gate. This large area over the semiconductor substrate surface results in a decrease in circuit component density or decreased circuit component miniaturization.
  • the channel region of a metal-oxide-semiconductor (MOS) field effect transistor is formed in a trench in the semiconductor. The transistor then occupies far less semiconductor substrate surface and so enables a high component density circuit to be obtained.
  • MOS metal-oxide-semiconductor
  • the transistor is formed by forming a first trench in the semiconductor substrate, lining the trench with a layer of insulating material, a layer of conducting material, and filling the trench with a layer of insulator.
  • a doped region is formed adjacent the trench, which serves as a transistor source.
  • a second trench is then formed which extends through and excavates a portion of the first trench.
  • the second trench is lined with a layer of doped material and insulator.
  • the doped material is isolated from the conductive layer lining the first trench.
  • the second trench is then filled with a body of conductive material.
  • the layer of doped material lining the second trench serves as the transistor drain and a capacitor electrode.
  • the conductive trench fill serves as the capicitor counterelectrode.
  • the resulting structure acts as a trench gate MOS transistor having a capacitor output in series with the transistor drain.
  • the first trench is formed to be up to approximately 10 to 20 microns deep, 2 to 3 microns wide and 10 to 20 microns long.
  • Both first and second trenches may be formed by reactive ion etching of the substrate.
  • the insulating layers may be formed by thermally oxidizing the exposed silicon substrate or exposed layer of silicon, or by vapor deposition of an insulator.
  • the doped region may be formed by diffusing dopants into the semicondcutor substrate.
  • the layer of conductive material may be formed by vapor deposition.
  • the body of insulating material preferably fills the first trench completely, and the body of conductive material, preferably fills the second trench completely.
  • the inventive concepts of the invention may be extended by forming a second trench gate complementary MOS transistor within the substrate adjacent the integral transistor/capacitor, and interconnecting the integral transistor/capacitor and the second transistor to form complimentary trench gate MOS transistors having a capacitor in series with the interconnected drain terminals of both the integral transistor/capacitor and the transistor.
  • the second transistor may be constructed by forming a third trench in the semiconductor substrate adjacent the second trench. Second and third doped regions may be formed adjacent the upper surface of the substrate on opposite sides of the third trench. A second layer of doped material may be formed about the third trench, and about the second and third regions, isolating the second and third doped regions from the substrate.
  • a layer of of insulator may be formed within the third trench upon the second layer of doped material, and the trench may then be filled with a body of conductive material upon the second insulating layer.
  • the second and third regions may be viewed as source and drain regions, respectively, of the second transistor, and the body of conductive material forming the second transistor gate.
  • the drain and gate regions of the integral transistor/capacitor and the second transistor may be interconnected to provide complimentary trench gate MOS transistors, having a capacitor in series with the interconnected drain terminals.
  • the third trench may be formed to be between 5 to 25 microns deep, 2 to 5 microns wide and 10 to 20 microns long.
  • Figure 1 is a cross-sectional view of a contemporary MOS transistor structure
  • Figure 2 is a cross-sectional view of a transistor -6- formed in accordance with the present invention.
  • Figure 3 is a top perspective view of the transistor illustrated at Figure 2;
  • Figure 4 is a schematic representation of a contemporary processing circuit element including an MOS transistor and a series capacitor;
  • Figure 5 is a schematic representation of a contemporary processing circuit of CMOS transistors and a series capacitor
  • Figures 6-15 illustrate the construction of a single trench MOSFET capacitor cull for analog signal processing in accordance with the schematic representation of Figure 4;
  • Figures 16 and 17 illustrate the construction of CMOS transistors wherein the single trench MOSFET capacitor cell is supplemented for the formation of an adjacent trench gate transistor to provide a construction equivalent to the schematic representation set forth at Figure 5.
  • CMOS transistors wherein the single trench MOSFET capacitor cell is supplemented for the formation of an adjacent trench gate transistor to provide a construction equivalent to the schematic representation set forth at Figure 5.
  • FIG. 16 The detailed description set forth below in connection with the appended drawings is intended as a description of the presently preferred embodiment of the invention, and is not intended to represent the only form in which the present invention may be constructed or utilized.
  • the description sets forth the functions and sequence of steps for construction of the invention in connection with the illustrated embodiment. It is to be understood, however, that the same or equivalent functions and sequences may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention.
  • integrated circuit processor channels may be used in on-focal-plane signal processors.
  • Each detector element in the detector array may be connected to a preamplifier, such as a CMOS preamplifier, in an analog processor circuit.
  • CMOS preamplifier Low preamplifier noise is essential to prevent degradation of detector sensitivity. Since the preampli iers are operated at low - frequency, a principal source of noise is flicker or 1/f noise. The 1/f noise is inversely proportional to the area of the channel or gate regions of an MOS transistor, as expressed in the following equation:*
  • K a constant
  • C characteristic capacitance of the oxide - - layer
  • W the width of the gate
  • L the length of the gate. *See: R. Gregorian and C .C . Temes, Analog MOS Integrated Circuits For Signal Processing, pp. 98, 99, John Wiley & 20 Sons, N.Y., N.Y. (1986)
  • a large area gate region in a MOS transistor will produce a low 1/f noise component.
  • a structure requires a large amount of semiconductor surface area. This makes it difficult to obtain a high 25 density of such integrated circuit functions.
  • the present invention is directed to a structure and process for enhancing the area of the gate region without enhancing the semiconductor surface area.
  • the MOS transistor gate region may be regarded as a 30 capacitor, which is formed by a metal oxide semiconductor cross section. Large area capacitors that preserve semiconductor surface are obtained in bulk silicon by using the walls of trenches, grooves or holes, which are cut in silicon, for example, by plasma or reactive ion 35 etching. In such a manner, gate region area may be enhanced by using the depth of the trench to enlarge the -8- electrode channel area without the need to use a large amount of the semiconductor surface.
  • the present invention recognizes the capacitive characteristics of the MOS transistor gate region and applies particular trench forming techniques to the construction of the MOS transistor.
  • FIG. 1 illustrates an n-MOS transistor constructed in accordance with conventional techniques.
  • MOS transistor 11 is formed of an n-doped source region 21 and an n-doped drain region 23 formed in p-doped silicon 20.
  • the source and drain regions are bridged by an insulating layer, e.g. insulating layer 25, which may be formed of material such as silicon dioxide (Si0 2 ) or silicon nitride.
  • a conductive gate 27 is disposed on the upper surface of the insulator 25.
  • the gate 27 is typically formed of metal or doped polysilicon.
  • the characteristic 1/f noise is related to the width and length of the gate area intermediate the source and drain.
  • the length of the gate area, labeled L, is shown at Figure 1.
  • the width of the gate area is orthogonal to the plane of the drawing.
  • the present invention is directed to a construction and technique wherein the gate area is enhanced without the need to appropriate greater surface area of the semiconductor wafer.
  • FIG. 2 illustrates one embodiment of the present invention .
  • MOS transistor 13 comprises an n-doped source region 21 , and an n-doped drain region 23 , both formed in p-doped -9- silicon 20.
  • a trench 31 is formed in the silicon substrate.
  • the trench may be formed by any of a variety of techniques, such as reactive ion etching.
  • An insulating layer 33 is disposed on the vertical and bottom surface of the trench 31.
  • the insulating layer 33 is a thin film of silicon dioxide formed by thermal oxidation of the silicon.
  • a conductive film 35 which serves as the gate, is then disposed on the upper surface of insulating layer 33.
  • the gate layer 35 may be formed of conductive material, such as metal or of degenerately doped semiconductor material, e.g. polysilicon.
  • the trench can be filled with an insulator material such as Si0 2 or with a conductive material without the need for a conductive film liner.
  • Electrodes 37, 39 may be formed on the upper exposed surfaces of source 21 and drain 23, respectively. Where the insulating layer 33 extends above the surfaces of source 21 and drain 23, the SiO_ may be etched by any of a number of contemporary techniques to facilitate the formation of the electrodes. An additional electrode (not shown) may be formed to facilitate contact with the gate layer 35.
  • trench 31 is formed to be up to approximately 10 to 20 microns deep and 2 to 3 microns wide.
  • the length of the trench (orthogonal to the plane of Figure 1) is up to the range of 10 to 20 microns.
  • the particular dimensions may be selected in accordance with the desired noise characteristics and speed of the transistor, and the available surface area.
  • a perspective view of a MOS transistor formed in accordance with Figure 2 is illustrated at Figure 3.
  • Figure 3 illustrates the arrangement of source, gate, and drain electrodes on the semiconducter substrate surface. A filled trench is depicted.
  • the gate would be connected to a dedicated detector element and the drain to a storage capacitor which may be selectively interrogated by the further processing circuitry (not shown).
  • the source may be connected to a low level bias circuit, or alternatively may be sustained at a substantially zero level, as may be desired.
  • the construction illustrated at Figures 2 and 3, therefore provides advantages of low 1/f noise without the penalty in terms of semiconductor surface area. Though certain penalties may be inherited in terms of the speed of the MOS transistor, in certain applications the speed limitations are not restrictive. On the contrary, 1/f noise reduction is needed in low speed imaging systems, for example, for highest sensitivity.
  • the present invention further expands beyond the unique aspects of the trench gate MOS transistor by providing for the integration of the series capacitor with a transistor in a single trench region, represented schematically at Figure 4.
  • a portion of the trench may be excavated to permit formation of a capacitor within the excavated region. Consequently, the capacitor is formed integral within the trench region.
  • the integrated MOS transistor/capacitor is connected to a separately formed trench gate complementary MOS transistor. The connections between the trench regions produces a complimentary MOS circuit with a series capacitor, as schematically represented in Figure 5.
  • Figures 6-15 illustrate the construction of an integrated trench gate transistor/capacitor conforming to the schmatic representation of Figure 4. The construction proceeds as follows.
  • trench 31 is formed in substrate 20.
  • the substrate is formed of p-type bulk silicon.
  • An insulating layer 33 is then disposed on the surfaces of trench 31.
  • the insulating layer 33 may, for example, be a layer of silicon dioxide ( Si0 2 ) formed by thermally oxidizing the silicon substrate.
  • a first layer of conductive material 35 e.g. degenerately doped polycrystalline silicon, is disposed upon the insulating layer 33.
  • the first doped layer 35 is formed by chemical vapor deposition of degenerately doped polycrystalline silicon.
  • the trench 31 is filled with a body of insulating material 41.
  • the insulating material may be silicon dioxide, applied by vapor deposition.
  • a source region 21 is formed in the substrate 20, e.g. by diffusing n-type dopant into the upper surface of the substrate 20 adjacent insulating layer 33, as shown at Figure 10.
  • a second trench 32 is then formed in the substrate 20.
  • the trench 32 may be formed by means such as reactive ion etching.
  • Trench 32 as illustrated at Figure 11, slices a portion of trench 31, including insulating body 41, insulating layer 33 and first conductive layer 35.
  • a first doped layer 43 is then formed by diffusion at the silicon surfaces of trench 32, as illustrated at Figure 12.
  • a second insulating layer 45 is then formed within trench 32 over layers 43 and 35 by thermally oxidizing these exposed silicon surfaces.
  • an insulator layer of silicon dioxide or silicon nittride can be chemical vapor deposited over the trench walls and floor.
  • the trench 32 may then be filled with a body of conductive material 47, such as degenerately doped polysilicon, as shown at Figure 14.
  • a body of conductive material 47 such as degenerately doped polysilicon
  • FIG. 15 An optional surface contact to layer 43 is included in Figure 15.
  • the construction of doped layer 43 and insulating body 47, separated by insulating layer 45, may be viewed as a capacitor, disposed in series with the transistor gate. Consequently, an output terminal connected to the body 47 may be viewed as an output from the transistor drain, passing through a series capacitor.
  • the construction illustrated at Figure 15 may be schematically represented by the circuit illustrated at Figure 4.
  • a trench gate MOS transistor is formed integral with a trench capacitor.
  • the advantages of low 1/f noise and high capcitance are achieved while minimizing the surface area needed to provide such a construction.
  • the integral MOS trench transistor/capacitor may further be connected to an adjacent trench gate complementary MOS transistor, similarly constructed in accordance with Figure 2.
  • Figures 16 and 17 illustrate the construction and interconnection of an adjacent trench gate complementary MOS transistor interconnected to the structure illustrated at Figure 15.
  • the second or trench gate complementary MOS transistor 42 can be constructed as illustrated at Figure 16.
  • First a well region 51 of opposite type to the substrate 20 is formed by a deep dopant diffusion.
  • the well 51 is doped to be n-type.
  • the transistor formation in the well then follows the device fabrication procedures in accordance with Figure 2, except the source and drain regions are of opposite type. In the present preferred embodiment, the source and drain regions are p-type.
  • Figure 17 illustrates a construction similar to that set forth at Figure 16, except that the formation of well 51 is avoided by formation of a doped layer 57 by dopant diffusion, e.g., n-type in the presently preferred embodiment, at the trench and substrate surfaces adjacent to the trench. It extends about the remaining portions of the MOS transistor 44. It thus forms the MOS transistor channels and isolates the transistor from the substrate 20.
  • the source 59 and drain 61 are formed of p-doped material and the gate 63 is formed of a conductive material such as degenerately doped polycrystalline silicon.
  • Insulating layer 65 is formed of silicon dioxide, e.g. by thermally oxidizing the surface of doped silicon layer 57.
  • the transistor area is only as great as needed to reduce 1/f noise.
  • the trench areas, and approximatley the linear dimensions, of the two transistors should be the same. Therefore, the trench of the complimentary transistor is made less deep than the transistor integrated with the capacitor, where the gate region is cut off by the extended trench.

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Abstract

L'invention concerne un procédé de formation d'un transistor MOS à une seule tranchée/d'une cellule de condensateur, pour le traitement de signaux analogiques, ainsi que la structure obtenue. Le transistor est formé par aménagement d'une première tranchée (31) dans le substrat à semiconducteur, par revêtement de ladite tranchée à l'aide d'une couche de matière isolante (33), une couche de matière conductrice (35), et à remplir ladite tranchée avec une couche d'isolant (41). On forme une région dopée adjacente à ladite tranchée, servant de source de transistor (21). On forme ensuite une seconde tranchée (32), s'étendant dans une partie de ladite première tranchée, et creusant cette dernière. Ladite seconde tranchée est revêtue d'une couche de matière dopée (43) et d'un isolant (45). Ladite matière dopée (43) est isolée de ladite couche conductrice (35) recouvrant ladite première tranchée (31). On remplit ensuite ladite seconde tranchée (32), d'un corps de matière conductrice (47). La couche de matière dopée (43) recouvant ladite seconde tranchée, sert de drain de transistor, et l'on extrait une sortie de condensateur provenant du corps de matière conductrice (47).
PCT/US1990/000240 1989-03-23 1990-01-09 Mosfet a une seule tranchee-cellule de condensateur pour le traitement de signaux analogiques WO1990011619A1 (fr)

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US32768889A 1989-03-23 1989-03-23
US327,688 1989-03-23

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5275974A (en) * 1992-07-30 1994-01-04 Northern Telecom Limited Method of forming electrodes for trench capacitors
WO1998056020A3 (fr) * 1997-06-06 1999-03-04 Ericsson Telefon Ab L M Procede permettant de disposer un condensateur enterre et condensateur enterre dispose selon ledit procede

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59141262A (ja) * 1983-02-02 1984-08-13 Nec Corp 半導体メモリセル
US4651184A (en) * 1984-08-31 1987-03-17 Texas Instruments Incorporated Dram cell and array
US4672410A (en) * 1984-07-12 1987-06-09 Nippon Telegraph & Telephone Semiconductor memory device with trench surrounding each memory cell
US4673692A (en) * 1984-10-19 1987-06-16 Teikoku Hormone Mfg. Co., Ltd. Diphenylmethylimine derivatives, their compositions and pharmaceutical uses
EP0282716A1 (fr) * 1987-03-16 1988-09-21 Texas Instruments Incorporated Cellule du type DMOS et procédé de fabrication
JPS63227050A (ja) * 1987-03-17 1988-09-21 Toshiba Corp 半導体記憶装置及びその製造方法
JPS6486561A (en) * 1987-06-17 1989-03-31 Nec Corp Vertical mos transistor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59141262A (ja) * 1983-02-02 1984-08-13 Nec Corp 半導体メモリセル
US4672410A (en) * 1984-07-12 1987-06-09 Nippon Telegraph & Telephone Semiconductor memory device with trench surrounding each memory cell
US4651184A (en) * 1984-08-31 1987-03-17 Texas Instruments Incorporated Dram cell and array
US4673692A (en) * 1984-10-19 1987-06-16 Teikoku Hormone Mfg. Co., Ltd. Diphenylmethylimine derivatives, their compositions and pharmaceutical uses
EP0282716A1 (fr) * 1987-03-16 1988-09-21 Texas Instruments Incorporated Cellule du type DMOS et procédé de fabrication
US4830978A (en) * 1987-03-16 1989-05-16 Texas Instruments Incorporated Dram cell and method
JPS63227050A (ja) * 1987-03-17 1988-09-21 Toshiba Corp 半導体記憶装置及びその製造方法
JPS6486561A (en) * 1987-06-17 1989-03-31 Nec Corp Vertical mos transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5275974A (en) * 1992-07-30 1994-01-04 Northern Telecom Limited Method of forming electrodes for trench capacitors
WO1998056020A3 (fr) * 1997-06-06 1999-03-04 Ericsson Telefon Ab L M Procede permettant de disposer un condensateur enterre et condensateur enterre dispose selon ledit procede
US6140199A (en) * 1997-06-06 2000-10-31 Telefonaktiebolaget Im Ericsson Method and arrangement of a buried capacitor, and a buried capacitor arranged according to said method

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