WO1990011616A1

WO1990011616A1 - Trench gate complimentary metal oxide semiconductor transistor

Info

Publication number: WO1990011616A1
Application number: PCT/US1990/000238
Authority: WO
Inventors: Allen L. Solomon
Original assignee: Grumman Aerospace Corporation
Priority date: 1989-03-21
Filing date: 1990-01-09
Publication date: 1990-10-04
Also published as: CA2009067C; CA2009067A1

Abstract

A complimentary trench gate metal-oxide semiconductor transistor is disclosed along with a resulting product. The process for forming the transistor comprises forming a trench within the semiconductor substrate (59), wherein the semiconductor substrate is doped to a first conductivity type. A layer doped to a second conductivity type is applied about the surface of the trench. An insulating layer (61) is then formed within the trench upon said first layer. A region of gate material (57) is formed within the trench upon said insulating layer (61). Source and drain regions (53, 55) are formed by doping first and second regions adjacent the trench to the first conductivity type.

Description

-1-

TRENCH GATE COMPLIMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR Background of the Invention The present invention finds application in connection with thin silicon lates or wafers formed to support a multiplicity of monolithically integrated data processor circuits. More particularly, the invention is directed to the production of circuits formed on silicon wafers for interfacing devices such as infrared detector elements to a processing network that amplifies, stores and interprets detected infrared frequency signals.

The infrared spectrum covers a range of wavelengths longer than the visible wavelengths, but shorter than microwave wavelengths. Visible wavelengths are generally regarded as between 0.4 and 0.75 micrometers. The infrared wavelengths extend from 0.75 micrometers to 1 millimeter. The function of infrared detectors is to respond to the energy of a wavelength within some particular portion of the infrared region. Heated objects generate radiant energy having characteristic wavelengths within the infrared spectrum. Many current infrared image detection systems incorporate arrays with large numbers of discrete, highly sensitive detector elements, the electrical outputs of which are connected to processing circuitry. By analyzing the pattern and sequence of detector element excitation, the processing circuitry can identify and track sources of infrared radiation. Though the theoretical performance of such contemporary systems is satisfactory for many applications, it is difficult to construct structures tha adequately interface large numbers of detector element with associated circuitry in a practical and reliabl manner. Consequently, practical applications fo contemporary infrared image detector systems hav necessitated further advances in the areas o miniaturization of the detector array and accompanying circuitry, of minimization of circuit generated noise and of improvements in the reliability and economical production of detector arrays and the accompanying circuitry.

Contemporary arrays of detectors, useful for some applications , may be sized to include 256 detector elements on a side, or a total of 65, 536 detectors , the size of each square detector being approximately 0.009 centimeters on a side, with 0.00116 centimeters spacing between detectors . Such a subarray would therefore be 2.601 centimeters on a side . Interconnection of such a subarray to processing circuitry would require connecting each of the 65, 536 detectors to processing circuitry within a square, a l it tle more than one inch on a side . Each subarray may, in turn , be joined to other subarrays to form an array that connects to 25, 000 , 000 detectors or more. As would be expected considerable difficulties are presented in electrical ly connecting the detector elements to associated circuitry, and laying out the circuitry in a minimal area . The problems of forming processing circuitry in such a dense environment require minimization of the surface area used for the circuitry .

The outputs of the detector elements typical ly undergo a series of processing steps in order to permit derivation of the informational content of the detector output signal . The more fundamental processing steps , such as preamplification, tuned band pass filtering , clutter and background rej ection, multiplexing and fixed noise pattern suppression, are preferably done at a location adjacent the detector array focal plane . As a consequence of such on-focal plane, or up-front signal processing , reductions in size , power and cost of the main processor may be achieved. Moreover, on-focal plane signal processing helps alleviate performance, reliability and economic problems associated with the construction of millions of closely spaced conductors connecting each detector element to the signal processing network.

Aside from the aforementioned physical limitations on the size of the detector module, limitations on the performance of contemporary detection systems can arise due to the presence of electronic circuit generated noise, in particular, from the preamplifier. Such noise components can degrade the minimal level of detectivity available from the detector. A type of noise that is particularly significant where the preamplifier operates at low frequency is commonly called flicker or 1/f noise. Because 1/f noise can be the principal noise component at low frequencies of operation, it is highly desirable that circuits operating within such frequencies be constructed in such a manner as to decrease 1/f noise to an acceptably low level.

U.S. Patent No. 4,633,086, to Parrish, for Input Circuit For infrared Detector, assigned to the common assignee, describes one technique for biasing the on-focal plane processing circuit to maintain the associated detector in a zero bias condition, thus reducing 1/f noise and enhancing the signal to noise ratio of the circuit.

Reduction of 1/f noise in the preamplifier, where the preamplifier transistor is a field effect device, is conventionally obtained by increasing the area of the channel region under the gate. This large area over the semiconductor substrate surface results in a decrease in circuit component density or decreased circuit component miniaturization. In the present invention, the channel region of a metal-oxide-semiconductor (MOS) field effect transistor is formed in a trench in the semiconductor. The transistor then occupies far less semiconductor substrate surface and so enables a high component density circuit to be obtained. The present invention expands upon my copending invention, TRENCH GATE METAL-OXIDE-SEMICONDUCTOR -4-

TRANSISTOR, to provide a complimentary trench gate transistor, i.e., a trench gate p-type transistor and a trench gate n-type transistor formed in a common semiconductor substrate. This enables a preamplifier circuit to be made that dissipates less power than a single type transistor circuit. Low power dissipation is needed especially for high component density integrated signal processor circuits which are a part of an image detecting focal plane assembly that is operated at a cryogenic temperature. The conventional complimentary MOS transistor is formed lateral to the substrate surface and is electrically isolated from the substrate by constructing it in a well of an impurity type opposite to the substrate. The trench gate complimentary transistor can alternatively employ a more readily formed, relatively shallow dopant diffused region around the trench to obtain this isolation.

Summary of the Invention A trench gate complimentary metal oxide semiconductor transistor is disclosed along with a resulting product. The process for forming the transistor comprises forming a trench within the semiconductor substrate, wherein the semiconductor substrate is doped to a first relative type opposite to the substrate type. A second region doped to the same relative type is applied about the surface of the trench. An insulating layer is then formed within the trench upon said first layer. A region of conductive gate material is formed within the trench upon said insulating layer. Source and drain regions are formed by doping first and second regions adjacent the trench and within the initially doped region around the trench to the same relative type of the substrate. These source and drain regions are then isolated from the substrate by remaining portions of the first and second doped regions. The first layer therefore extends between said source and drain about said trench , and wherein the gate region is isolated from the first layer by the insulating layer .

In the presently preferred embodiment the substrate is formed of p-doped silicon and the trench is formed by reacti ve ion etching of the substrate. The first and second doped regions are formed by diffusing an n-type dopant into the trench and about the surface of the trench. The insulating layer is formed by oxidizing the trench surfaces to form a thin silicon dioxide insulating layer .

In the presently preferred embodiment the source and drain regions are formed by doping the substrate surface adjacent the trench to form n-doped regions, and then counter-doping the n-doped regions to form first and second p-type segments within said n-doped regions . Said p-doped segments b eing isolated from the substrate . The gate may be formed by completely filling the trench , adjacent the insulating layer, with a body of degenerately doped polysilicon . Brief Description of the Drawings

Figure 1 is a cros s-s ectional view of a contemporary MOS transistor structure;

Figure 2 is a cross-sectional view of a transistor formed in accordance with the present invention ; Figure 3 is a top perspective view of the transistor ill ustrated at Figure 2 ;

Figure 4 illustrates a construction of a complimentary trench gate MOS transistor utilizing the formation of a wel l ; Figure 5 illustrates the construction of a compl imentary MOS transistor without the formation of a wel l ;

Figures 6-9 i llustrate the process of forming a complimentary MOS transistor such as illustrated at Figure 5. Detailed Description of the Presently Preferred Embodiment The detailed description set forth below in connection with the appended drawings is intended as a description of the presently preferred embodiment of the invention, and is not intended to represent the only form in which the present invention may be constructed or utilized. The description sets forth the functions and sequence of steps for construction of the invention in connection with the illustrated embodiment. It is to be understood, however, that the same or equivalent functions and sequences may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention. Furthermore, a similar trench gate embodiment can be used to form complimentary junction field effect transistors as well as the MOS field effect transitors described here.

As previously noted large numbers of closely spaced, high component density integrated circuit processor channels may be used in on-focal plane signal processors. Each detector element in the detector array may be connected to a preamplifier, such as a CMOS preamplifier, in an analog processor circuit. Low preamplifier noise is essential to prevent degradation of detector sensitivity. Since the preamplifiers are operated at low frequency, a principal source of noise s flicker or 1/f noise. The 1/f noise is inversely proportional to the area of the channel or gate regions of an MOS transistor, as expressed in the following equation:

v² = f

C_oχWLf , where v = the characteristic noise in microvolts;

K = a constant;

Δf = bandwidth f = the frequency of operation; cox = characteristic capacitance of the oxide layer; W = the width of the gate; and L = the length of the gate. See: R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits In Signal Processing, John Wiley & Sons, N.Y., N.Y. (1986).

A large area gate region in a MOS transistor will produce a low 1/f noise component. However, such a structure requires a large amount of semiconductor surface area. This makes it difficult to obtain a high density of such integrated circuit functions. The present invention is directed to a structure and process for enhancing the area of the gate region without enhancing the semiconductor surface area.

The MOS transistor gate region may be regarded as a capacitor, which is formed by a metal oxide semiconductor cross section. Large area capacitors that preserve semiconductor surface are obtained in bulk silicon by using the walls of trenches, grooves or holes, which are cut in silicon, for example, by plasma or reactive ion etching. In such a manner, gate region area may be enhanced by using the depth of the trench to enlarge the electrode channel area without the need to use a large amount of the semiconductor surface. The present invention recognizes the capacitive characteristics of the MOS transistor gate region and applies particular trench forming techniques to the construction of the MOS transistor. In such a manner the MOS transistor gate channel area or gate channel region, is enhanced, mitigating 1/f noise, without the need to use large amounts of the semiconductor surface.

Figure 1 illustrates an n-MOS transistor constructed in accordance with conventional techniques. As shown therein MOS transistor 11 is formed of an n-doped source region 21 and an n-doped drain region 23 formed in p-doped silicon 20. The source and drain regions are bridged by -8- an insulating layer, e.g. insulating layer 25, which may be formed of material such as silicon dioxide ( Si0₂ ) or silicon nitride. A conductive gate area 27 is disposed on the upper surface of the insulator 25. The gate 27 is typically formed of metal or doped polysilicon.

In relation to Figure 1 the characteristic 1/f noise is related to the width and length of the gate area intermediate to the source and drain. The length of the gate area, labeled L, is shown at Figure 1. The width of the gate area is orthogonal to the plane of the drawing. By increasing the length of the gate L, 1/f noise is reduced, though the maximum speed at which the circuit will efficiently operate is reduced. The present invention is directed to a construction and technique wherein the gate area is enhanced without the need to appropriate greater surface area of the semiconductor wafer.

Figure 2 illustrates one embodiment of the present invention. As with MOS transistor 11 shown at Figure 1, MOS transistor 13 comprises an n-doped source region 21, and an n-doped drain region 23, both formed in p-doped silicon 20. Unlike the construction shown at Figure 1, a trench 31 is formed in the silicon substrate. The trench may be formed by any of a variety of techniques, such as reactive ion etching. An insulating layer 33 iβ disposed on the vertical and bottom surface of the trench 31. In the presently preferred embodiment the insulating layer 33 is a thin film of silicon dioxide formed by thermal oxidation of the silicon. A conductive film 35, which serves as the gate, is then disposed on the upper surface of insulating layer 33. The gate layer 35 may be formed of conductive material, such as metal or of degenerately doped semiconductor material, e.g. polysilicon. In an alternative structure the trench can be filled with an insulator material such as SiO_ or with a conductive material without the need for a conductive film liner. Electrodes 37, 39 may be formed on the upper exposed surfaces of source 21 and drain 23, respectively. Where the insulating layer 33 extends above the surfaces of source 21 and drain 23, the Si0₂ may be etched by any of a number of contemporary techniques to facilitate the formation of the electrodes. An additional electrode (not shown) may be formed to facilitate contact with the gate layer 35.

In accordance with the construction shown at Figure 2 the gate region intermediate to the source 21 and drain 23 is enlarged by means of a formation of trench 31. In the presently preferred embodiment trench 31 is formed to be up to approximately 10 to 20 microns deep and 2 to 3 microns wide. The length of the trench (orthogonal to the plane of Figure 1) is in the range of 10 to 20 microns. The particular dimensions may be selected in accordance with the desired noise characteristics and speed of the transistor, and the available surface area.

A perspective view of a MOS transistor formed in accordance with Figure 2 is illustrated at Figure 3. Figure 3 illustrates the arrangement of source, gate, and drain electrodes on the semiconductor substrate surface. A filled trench is depicted.

It is anticipated that the gate would be connected to a dedicated detector element and the drain to a storage capacitor which may be selectively interrogated by the further processing circuitry (not shown). The source may be connected to a low level bias circuit, or alternatively may be sustained at a substantially zero level, as may be desired.

The construction illustrated at Figures 2 and 3, therefore provides advantages of low 1/f noise without the penalty in terms of semiconductor surface area. Though certain penalties may be inherited in terms of the speed 5 of the MOS transistor, though in certain applications the speed limitations are not restrictive. On the contrary, -10-

1/f noise reduction is needed in low speed imaging system, for example, for highest sensitivity.

Figures 4 and 5 illustrate the construction of a complimentary MOS transistor. Figure 4 illustrates a well region of opposite type to the substrate. Figure 5 illustrates a diffused region opposite type to the substrate which is an alternative structure to the well. The source and drain regions for both transistors are doped to the same type as the substrate. Both source and drain are p-doped, as is the substrate. Consequently, the complimentary MOS transistor must be constructed in such a way that the source and drain are not only insulated from the gate region, but also from the substrate. Figures 4 and 5 illustrate a complimentary MOS transistor construction, using the trench forming techniques of the present invention.

Figures 6-11 illustrate an exemplary manner of construction to form the complimentary MOS transistor illustrated at Figure 5. Referring to Figure 4 complimentary MOS transistor 51 is illustrated. The MOS transistor includes source 53, drain 55 and gate 57. Substrate 59, as with the embodiment illustrated at Figure 2, can be formed of p-doped silicon. The source region 53 and drain region 55 are also formed of p-doped material, such as p-doped silicon. Gate 57 is formed of conductive material, such as metal or degenerately doped polysilicon. Gate insulator layer 61 extends about the gate region 57 and serves as an insulating layer about the gate 57. Because the substrate 59 is of the same dopant type as the source and drain, it is necessary to isolate the source and drain from the substrate in order to insure proper operation of the MOS transistor. In the embodiment illustrated at Figure 4, this is effected by first forming well within the substrate 59. The n-doped layer extends beyond the source 53 and the drain 55 to permit proper -11- ope ration of the MOS transistor within the p-doped substrate 59.

Figure 5 illustrates an alternate construction of the complimentary MOS transistor illustrated at Figure 4, wherein the need to form a well of n-doped material is eliminated and replaced with narrow regions of doped substrate around the trench and the source and drain. In such a manner the fabrication is simplified by eliminating the need for a very deep diffusion. In the embodiment illustrated at Figure 5 the MOS transistor 71 includes source region 53, drain region 55 and gate region 57. Insulating layer 61 surrounds the gate region 57. Unlike the complimentary MOS transistor 51, illustrated at Figure 4, the MOS transistor 71 does 5 not include a well area 63. Instead, a layer 73 is formed about the gate area after the trench is formed. The layer 73 is formed by an n-type diffusion in the substrate. The layer 73 extends between the source 53 and drain 55, and continues to encompass source 53 and drain 55 on the upper 0 surface of MOS 71. In practice regions 72 and 74 about source 53 and drain 55 may be formed separately from the remaining portion of layer 73 extending about the trench gate region, e.g., by diffusion at the surface. Further details of the construction of the MOS transistor 71 are 5 set forth in connection with Figures 6-11.

Construction of a trench gate complimentary MOS transistor in accordance with the present invention proceeds as follows. Trench 70 is first cut in the surface of the substrate 72. A layer region of material 30 73 is formed on the sides and bottom of the trench 70. This layer 73 may be formed by diffusing doped material into the trench walls and floor. In the illustrated embodiment the layer 73 is n-type to form an n-channel region within the p-doped silicon substrate. An

35 insulating layer 61 is then applied to the n-doped layer 73. The insulating layer 61 may be formed by oxidizing the surface of n-doped silicon layer 73 . In the presently preferred embodiment insulating layer 61 is formed of silicon dioxide. The source and drain segments 53 , 55 are then formed by counter doping f rom the surface of the sil icon substrate to form p-doped regions . Before formation of such segments , the surface may have been , as described, doped to form n-doped regions to insure that an n-doped region surrounds the source and drain . The p-doped segmments 53 , 55 are therefore disposed within the n-doped segments 72 , 74 . The p-doped segments 72 , 74 can be viewed as extensions of the layer 73 . Thus , the layer 73 can be viewed as extending about and isolating the source region 53 and drain region 55.

Next, the trench is filled with conductive material . in the presently preferred embodiment gate region 57 is formed by filling the trench with degenerately doped poly silicon. It is to be understood that the gate region 57 may alternatively be formed by depositing a conductive layer over insulati ng layer 61 rather than filling the channel, as illustrated at Figure 2. Final ly , electrodes are applied at the source , gate and drain regions to facil itate interconnection to external circuitry . As will be understood by one of ordinary skill in the art, the electrodes and connections are made as they are conventional ly for CMOS transistor circuits.

In the presently preferred embodiment , the MOS transistor may be formed such that the transistor gate region , as defined by the gate 57 and adj acent insulating layer, has a width of 2 to 3 microns , a height up to 10 to 20 mi crons and a width up to 10 to 20 mi crons . It is to be understood , however, that the MOS transistor may be constructed to be of a dif ferent size in accordance with the desired performance characteristics . -13-

As discussed above various modifications and substitutions may be effected to impliment the structure and function of the invention, without departing from the spirit and scope of the invention.

5

Claims

What is Claimed is:

1. A method of forming a trench gate complimentary metal oxide semiconductor transistor comprising: forming a trench within a semiconductor substrate, the semiconductor substrate being doped to a first relative type; applying a layer doped to a second relative type opposite to the substrate about the surfaces of the trench and upper surfaces of the trench; applying an insulating layer about the surfaces of the trench and upon said first layer; doping the first and second regions adjacent the trench to the opposite relative type of the substrate; doping upper segments of said first and second regions to the same relative type as the substrate, said segments being isolated from the substrate by the remaining portions of said first and second regions; and applying a layer of conductive gate material within said trench upon said insulating layer; wherein said first and second segments form the source and drain, respectively, of the transistor, and said first layer extends between said source and drain about said trench, and wherein said gate material is isolated from said first layer by said insulating layer.

2. The process as recited in Claim 1 wherein said step of forming a trench comprises reactive ion etching of the substrate.

3. The process as recited in Claim 1 wherein said substrate is formed of p-doped silicon.

4. The process as recited in Claim 2 wherein sai first layer is formed of n-doped silicon diffused into th trench to form an n-region channel. -15-

5. The process as recited in Claim 4 wherein said insulating layer is formed by oxidizing the surface of said n-doped silicon first layer to form a silicon dioxide insulating layer.

6. The process as recited in Claim 5 wherein said first and second regions are formed by doping the substrate surface adjacent the trench to form n-doped regions, and then counter-doping the n-doped regions to form first and second, p-type segments within said n-doped regions, said p-doped segments being isolated from the substrate.

7. The process as recited in Claim 6 wherein the step of applying a layer of gate material comprises filling the trench with degenerately doped polysilicon.

8. The process as recited in Claim 6 wherein the step of applying a layer of gate material comprises filling the trench with metal.

9. A trench gate complimentary metal-oxide semiconductor transistor comprising: substrate; a trench formed in the substrate; a first layer applied to the trench surface, said first layer being doped opposite relative typ to the substrate; an insulating layer applied to said first laye and extending about the trench; first and second doped regions formed adjacen the substrate surface on opposite sides of th trench, said first and second regions being of th same relative type as said first layer and being i substantial contact therewith; first and second doped segments formed in sai first and second doped regions respectively, sai first and second doped segments being doped to th same relative type as said substrate, said first an second segments being isolated from said substrate b said first and second regions; and a region of conductive gate material formed upon said insulating layer and extending about said trench, said region of gate material being formed of material doped to the opposite relative type as said substrate.

10. The transistor as recited in Claim 9 wherein said substrate is formed of p-doped silicon.

11. The transistor as recited in Claim 10 wherein said f irst layer is formed of n-doped silicon .

12. The transistor as recited in Claim 11 wherein said in sulating layer comprises a layer of silicon di oxide.

13. The process as recited in Claim 12 wherein said first and second regions are formed of n-doped material .

14 . The transistor as recited in Claim 13 wherein said f irst and second segments are formed of p-doped material .

15. The transistor as recited in Claim 14 wherein said gate region comprises a region of degenerately doped polysilicon.

16. The transistor as recited in Claim 15 wherein said gate material substantially fills the trench adj acent said insulating layer.