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US9991379B1 - Semiconductor device with a gate insulating film formed on an inner wall of a trench, and method of manufacturing the same - Google Patents

Semiconductor device with a gate insulating film formed on an inner wall of a trench, and method of manufacturing the same Download PDF

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Publication number
US9991379B1
US9991379B1 US15/354,976 US201615354976A US9991379B1 US 9991379 B1 US9991379 B1 US 9991379B1 US 201615354976 A US201615354976 A US 201615354976A US 9991379 B1 US9991379 B1 US 9991379B1
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semiconductor substrate
semiconductor device
trench
region
nitride film
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US20180138310A1 (en
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Ryohei BABA
Tomonori Hotate
Satoru Washiya
Hiroshi Shikauchi
Youhei Ohno
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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    • H01L29/7813—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L29/0623—
    • H01L29/1095—
    • H01L29/66734—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps

Definitions

  • This disclosure relates to a semiconductor device and a method of manufacturing the same.
  • MOSFET power metal-oxide-semiconductor field-effect transistor
  • IGBT insulated gate bipolar transistor
  • US 2015/0021623 discloses a MOSFET in which a gate insulating film including an oxide film, a nitride film, or a laminate structure of the oxide film and the nitride film is formed on an inner wall of a trench.
  • JP-A 2001-210821 discloses a transistor in which a gate insulating film having a laminate structure of an oxide film, a nitride film, and an oxide film is formed on a bottom of a trench and a gate insulating film including an oxide film is formed on sidewalls of the trench.
  • the gate insulating film formed on sidewalls of the trench includes the nitride film, and thus charge mobility is decreased.
  • the gate insulating film including the oxide film may be formed by, for example, a chemical vapor deposition (CVD), other than the thermal oxidation.
  • CVD chemical vapor deposition
  • the oxide film is also formed on the front surface of the semiconductor substrate, and an interlayer insulating film such as a BPSG (Boron Phosphorus Silicon Glass) film is formed on the oxide film.
  • BPSG Bipolar Phosphorus Silicon Glass
  • the insulating film formed on the front surface of the semiconductor substrate includes the oxide film, there is a possibility that penetration of moisture or ions into the semiconductor substrate from the outside cannot be suppressed, thereby causing characteristic deterioration of the transistor.
  • This disclosure is to provide a semiconductor device capable of suppressing penetration of moisture or ions into the semiconductor substrate and ensuring sufficiently charge mobility to improve reliability and a method of manufacturing the same.
  • a semiconductor device of this disclosure a semiconductor substrate, which includes: a drift region that has a first conductivity type; a body region that has a second conductivity type and is formed on the drift region, the second conductivity type being opposite to the first conductivity type; and an impurity region that has the first conductivity type and is formed inward from a surface of the body region; a trench, which is formed on a front surface of the semiconductor substrate and reaches the drift region; a control electrode, which is formed in the trench; an oxide film, which is formed between an inner wall of the trench and the control electrode; an electrode, which is connected to the impurity region; and a transistor, which includes a nitride film formed on the front surface of the semiconductor substrate excluding an upper side of the control electrode and a formation position of the electrode, in the semiconductor substrate.
  • a method of manufacturing a semiconductor device having a transistor of this disclosure includes: forming a semiconductor substrate that includes a drift region that has a first conductivity type; a body region that has a second conductivity type and is formed on the drift region, the second conductivity type being opposite to the first conductivity type; and an impurity region that has the first conductivity type and is formed inward from a surface of the body region; forming a nitride film on a front surface of the semiconductor substrate; patterning the nitride film and the semiconductor substrate and forming a trench on the front surface of the semiconductor substrate to reach the drift region; forming an oxide film on an inner wall of the trench; forming a control electrode in the trench, on which the oxide film is formed; exposing a portion of the impurity region; and forming an electrode to be connected to the portion of the impurity region.
  • FIG. 1 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device 100 according to an embodiment of this disclosure
  • FIG. 2A is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1 ;
  • FIG. 2B is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1 ;
  • FIG. 2C is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1 ;
  • FIG. 2D is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1 ;
  • FIG. 2E is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1 ;
  • FIG. 2F is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1 ;
  • FIG. 2G is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1 ;
  • FIG. 3 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device 200 according to a modified example of the semiconductor device 100 illustrated in FIG. 1 ;
  • FIG. 4A is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 200 illustrated in FIG. 3 ;
  • FIG. 4B is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 200 illustrated in FIG. 3 ;
  • FIG. 4C is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 200 illustrated in FIG. 3 ;
  • FIG. 4D is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 200 illustrated in FIG. 3 .
  • FIG. 1 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device 100 according to an embodiment of this disclosure.
  • the semiconductor device 100 includes at least a transistor such as a MOSFET or an IGBT having a trench gate structure.
  • the semiconductor device 100 includes a MOSFET 1 and a guard ring 2 to ensure a withstand voltage of the semiconductor device 100 , and these components are provided with a semiconductor substrate S made of a semiconductor such as silicon carbide (SiC).
  • the semiconductor device 100 may be configured to include a plurality of MOSFETs 1 .
  • the semiconductor substrate S includes a front surface serving as an upper surface in FIG. 1 and a back surface serving as a lower surface in FIG. 1 .
  • a direction toward the front surface from the back surface is defined as an upward direction
  • a direction toward the back surface from the front surface is defined as a downward direction.
  • the semiconductor substrate S included in the MOSFET 1 is configured with an n-type substrate 10 made of a semiconductor such as silicon or silicon carbide (SiC), an n-type drift region 11 that is formed on the substrate 10 and has a lower impurity concentration than the substrate 10 , a p-type body region 12 that is formed on the drift region 11 , and a pair of n-type impurity regions 14 that is formed toward the inside from the surface of the body region 12 and has a higher impurity concentration than the drift region 11 .
  • a semiconductor such as silicon or silicon carbide (SiC)
  • SiC silicon or silicon carbide
  • Each of the drift region 11 and the body region 12 may be configured to have a structure in which a plurality of layers having different impurity concentrations are laminated.
  • the impurity region 14 constitutes a source region of the MOSFET 1 .
  • the substrate 10 constitutes a drain region of the MOSFET 1 .
  • a drain electrode made of a metal material such as aluminum or titanium is formed on the back surface of the semiconductor substrate S.
  • the semiconductor substrate S included in the guard ring 2 is configured with the substrate 10 , the drift region 11 that is formed on the substrate 10 , and a plurality of p-type impurity regions 13 that are formed toward the inside from the surface of the drift region 11 .
  • Each of the p-type impurity regions 13 is a ring-shaped region that is formed to surround the MOSFET 1 .
  • the MOSFET 1 includes a trench 15 that is formed on the front surface of the semiconductor substrate S and reaches the drift region 11 , a gate electrode 23 that is partially or totally formed in the trench 15 , an oxide film 20 that is formed between an inner wall of the trench 15 and the gate electrode 23 and functions as a gate insulating film, a source electrode 24 that is made of a conductive material such as aluminum or titanium and is connected to each of the pair of impurity regions 14 , and a nitride film 21 that is formed on the front surface of the semiconductor substrate S and has openings formed between the upper side of the gate electrode 23 and a formation position of the source electrode 24 in the semiconductor substrate S.
  • the gate electrode 23 is a control electrode used to control an applied voltage, and is made of a conductive material such as polysilicon. By the control of the voltage to be applied to the gate electrode 23 , a channel is formed in the body region 12 adjacent to the trench 15 , and charges can be transferred to the substrate 10 , which is a drain region, from the impurity region 14 through the drift region 11 .
  • An interlayer insulating film 22 including a BPSG film, a PSG film, or the like is formed on the gate electrode 23 and the nitride film 21 .
  • the gate electrode 23 is insulated from the source electrode 24 by the interlayer insulating film 22 and the nitride film 21 .
  • the gate electrode 23 is formed beyond the front surface of the semiconductor substrate S in FIG. 1 , but may be buried in the semiconductor substrate S. In this configuration, the interlayer insulating film 22 is filled up to an upper surface of the gate electrode 23 in the semiconductor substrate S.
  • the oxide film 20 is an insulating film made of, for example, silicon dioxide (SiO 2 ).
  • the oxide film 20 is formed by thermal oxidation of the inner wall of the trench formed in the semiconductor substrate S.
  • a thickness of the oxide film 20 is set to, for example, a value in the range from 50 nm to 100 nm according to characteristics of the transistor.
  • the nitride film 21 is an insulating film made of silicon nitride (SiN), for example, and having high moisture or ion blocking performance.
  • the SiN means a material having a composition Si x N y represented by Si 3 N 4 .
  • the nitride film 21 is formed to the front surface of the semiconductor substrate S included in the guard ring 2 . In this way, the nitride film 21 is formed on the front surface of the semiconductor substrate S excluding the upper side of the gate electrode 23 and the formation position of the source electrode 24 in the semiconductor substrate S.
  • a method of manufacturing the semiconductor device 100 configured as above will be described below.
  • FIGS. 2A to 2G are schematic cross-sectional views illustrating manufacturing processes of the semiconductor device 100 illustrated in FIG. 1 .
  • the drift region 11 is formed on the substrate 10 by, for example, epitaxial growth or ion implantation, the body region 12 and the plurality of impurity regions 13 are formed on the surface of the drift region 11 by ion implantation or the like, and an n-type impurity region 14 a is formed on the surface of the body region 12 by ion implantation or the like, thereby forming the semiconductor substrate S.
  • the process of forming the semiconductor substrate S is not limited thereto, and may employ a known method.
  • SiN is deposited on the front surface of the semiconductor substrate S by, for example, a plasma CVD method or a sputtering method, and the nitride film 21 is formed. At this time, the nitride film 21 is formed up to the front surface of the semiconductor substrate S in the guard ring 2 .
  • a mask pattern is formed on the nitride film 21 by, for example, a photolithography method.
  • the mask pattern is a pattern having the opening at a position at which the impurity region 14 a is divided into two parts in a plan view.
  • the nitride film 21 and the semiconductor substrate S are etched by using the mask pattern and thus are subjected to patterning, and the trench 15 is formed to reach the drift region 11 from the front surface of the semiconductor substrate S, as illustrated in FIG. 2C .
  • the impurity region 14 a is divided into two parts by the trench 15 , and thus the pair of impurity regions 14 are formed as illustrated in FIG. 1 .
  • the semiconductor substrate S in which the trench 15 is formed, is subjected to thermal oxidation, and thus the oxide film 20 is formed on the inner wall (side surface and bottom surface) of the trench 15 as illustrated in FIG. 2D .
  • a silicon-based conductive material such as polysilicon is deposited in the interior of the trench 15 on which the oxide film 20 is formed and in the opening of the nitride film 21 located above the interior, by using a plasma CVD method or a sputtering method, thereby forming the gate electrode 23 .
  • the interlayer insulating film 22 including a BPSG film or a PSG film is formed on the nitride film 21 and the gate electrode 23 by using a CVD method, for example.
  • a mask pattern is formed on the interlayer insulating film 22 by using a photolithography method, for example.
  • This mask pattern is a pattern having openings located above at least two impurity regions 14 and the body region 12 .
  • openings 24 a are formed in the nitride film 21 and the interlayer insulating film 22 located above the impurity region 14 and the body region 12 , by using the mask pattern, and thus a portion of each impurity region 14 and a portion of the body region 12 are exposed.
  • the openings 24 a are filled with a metal material such as aluminum or titanium, by using a sputtering method or a CVD method, and thus the source electrode 24 is formed to be connected to the exposed portion of the impurity region 14 and the exposed portion of the body region 12 .
  • the nitride film 21 is formed on the front surface of the semiconductor substrate S, and thus there is no region where the oxide film is directly formed on the front surface of the semiconductor substrate S. Accordingly, it is possible to suppress penetration of moisture or ions from the interlayer insulating film 22 and to improve reliability of the device.
  • the gate insulating film is configured with only the oxide film 20 . Accordingly, it is possible to sufficiently ensure charge mobility and form the gate insulating film with high reliability.
  • the semiconductor device 100 As illustrated in FIG. 2D , it is possible to form the oxide film 20 by oxidizing the inner wall of the trench 15 in a state where the surface of the impurity region 14 is covered with the nitride film 21 .
  • the impurity region 14 can be suppressed from being oxidized and shrunk. Consequently, it is possible to simplify the ion implantation process used to form the impurity region 14 a illustrated in FIG. 2A and to reduce manufacturing costs.
  • FIG. 3 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device 200 according to a modified example of the semiconductor device 100 illustrated in FIG. 1 .
  • the semiconductor device 200 has the same configuration as that of the semiconductor device 100 except that the gate insulating film of the MOSFET 1 is formed by the oxide film 30 , and the oxide film 30 is formed to cover the surface of the nitride film 21 outside the trench 15 .
  • the oxide film 30 is an insulating film made of, for example, silicon dioxide (SiO 2 ).
  • a material is deposited on the inner wall of the trench formed on the semiconductor substrate S by using a CVD method, and thus the oxide film 30 is formed.
  • a thickness of the oxide film 30 is set to, for example, a value in the range from 50 nm to 100 nm according to characteristics of the transistor.
  • a method of manufacturing the semiconductor device 200 configured as above will be described below.
  • FIGS. 4A to 4G are schematic cross-sectional views illustrating manufacturing processes of the semiconductor device 200 illustrated in FIG. 3 .
  • the processes until the trench 15 is formed on the semiconductor substrate S are similar to those of the semiconductor device 100 , and thus the description thereof is not presented.
  • silicon dioxide is deposited on the front surface of the semiconductor substrate S, in which the trench 15 is formed, by using a CVD method, thereby forming the oxide film 30 .
  • a silicon-based conductive material such as polysilicon is deposited in the interior of the trench 15 formed with the oxide film 30 and also above the interior by using a plasma CVD method, a sputtering method, or the like, thereby forming a gate electrode 23 .
  • an interlayer insulating film 22 including a BPSG film or a PSG film is formed on the oxide film 30 and the gate electrode 23 by using a CVD method, for example.
  • a mask pattern is formed on the interlayer insulating film 22 by using a photolithography method, for example.
  • the mask pattern is a pattern having openings located above at least two impurity regions 14 and a body region 12 .
  • opening 24 b are formed in a nitride film 21 , the oxide film 30 , and the interlayer insulating film 22 which are located above the impurity region 14 and the body region 12 , by using the mask pattern, and thus a portion of the respective impurity regions 14 and a portion of the body region 12 are exposed.
  • the opening 24 b are filled with a metal material such as aluminum or titanium by using a sputtering method or a CVD method, and thus a source electrode 24 is formed to be connected to the exposed portion of the impurity region 14 and the exposed portion of the body region 12 .
  • a metal material such as aluminum or titanium
  • the nitride film 21 is formed on the front surface of the semiconductor substrate S, and thus there is no region where the oxide film is directly formed on the front surface of the semiconductor substrate S. Accordingly, it is possible to suppress penetration of moisture or ions from the interlayer insulating film 22 and to improve reliability of the device.
  • the gate insulating film is configured with only the oxide film 30 . Accordingly, it is possible to sufficiently ensure charge mobility and form the gate insulating film with high reliability.
  • the oxide film 30 is formed by using the CVD method. Therefore, it is possible to suppress shrinkage of the impurity region in the semiconductor substrate S, and to simplify the manufacturing processes.
  • the thickness of the nitride film 21 be larger than that of the oxide film 20 or oxide film 30 .
  • the thickness of the nitride film 21 is preferably set to a value larger than 100 nm.
  • the upper limit value of the thickness of the nitride film 21 is preferably set to be about 500 nm.
  • the nitride film 21 is formed over the entire surface of the semiconductor substrate S excluding the upper side of the region where the gate electrode 23 is buried in the semiconductor substrate S and the location at which the source electrode 24 is formed, and an area ratio of the nitride film 21 to a chip area of the semiconductor device 100 is large.
  • the nitride film 21 Since the nitride film has high permittivity, a too large thickness thereof causes an increase in capacity. In the viewpoint of suppressing the increase in capacity and thus suppressing deterioration of characteristics of the semiconductor device 100 or the semiconductor device 200 , it is preferable that the thickness of the nitride film 21 be set to be smaller than that of the oxide film 20 or the oxide film 30 . Specifically, the thickness of the nitride film 21 is preferably set to be less than 100 nm, and more preferably set to be less than 50 nm.
  • the MOSFET As the transistor included in the semiconductor device 100 or 200 , the MOSFET is exemplified in the above description. However, even when the transistor is an IGBT, the similar effects can be obtained with the similar configuration.
  • the semiconductor device 100 or 200 is configured such that the p-type and the n-type of the regions and the substrate 10 in the semiconductor substrate S are reversed, the similar effects can be obtained.

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Abstract

A semiconductor device includes a semiconductor substrate, which includes: a drift region that has a first conductivity type; a body region that has a second conductivity type and is formed on the drift region; and an impurity region that has the first conductivity type and is formed inward from a surface of the body region. The semiconductor device further includes a trench, which is formed on a front surface of the semiconductor substrate and reaches the drift region; a control electrode, which is formed in the trench; an oxide film, which is formed between an inner wall of the trench and the control electrode; an electrode, which is connected to the impurity region; and a transistor, which includes a nitride film formed on the front surface of the semiconductor substrate excluding an upper side of the control electrode and a formation position of the electrode, in the semiconductor substrate.

Description

TECHNICAL FIELD
This disclosure relates to a semiconductor device and a method of manufacturing the same.
BACKGROUND
There is a semiconductor device which has a transistor such as a power metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) in which a gate insulating film is formed on an inner wall of a trench formed in a front surface of a semiconductor substrate.
US 2015/0021623 discloses a MOSFET in which a gate insulating film including an oxide film, a nitride film, or a laminate structure of the oxide film and the nitride film is formed on an inner wall of a trench.
JP-A 2001-210821 discloses a transistor in which a gate insulating film having a laminate structure of an oxide film, a nitride film, and an oxide film is formed on a bottom of a trench and a gate insulating film including an oxide film is formed on sidewalls of the trench.
SUMMARY
In the configuration disclosed in US 2015/0021623, the gate insulating film formed on sidewalls of the trench includes the nitride film, and thus charge mobility is decreased.
As disclosed in JP-A 2001-210821, when the gate insulating film including the oxide film is formed on the sidewalls of the trench by thermal oxidation, a source region of the transistor is oxidized and shrunk at the time of formation of the gate insulating film. In consideration of the shrinkage, it is necessary to form the source region from the front surface to a deep position of the semiconductor substrate, thereby increasing manufacturing costs.
It is also considered that the gate insulating film including the oxide film may be formed by, for example, a chemical vapor deposition (CVD), other than the thermal oxidation.
In this case, the oxide film is also formed on the front surface of the semiconductor substrate, and an interlayer insulating film such as a BPSG (Boron Phosphorus Silicon Glass) film is formed on the oxide film.
As described above, in the configuration where the insulating film formed on the front surface of the semiconductor substrate includes the oxide film, there is a possibility that penetration of moisture or ions into the semiconductor substrate from the outside cannot be suppressed, thereby causing characteristic deterioration of the transistor.
This disclosure is to provide a semiconductor device capable of suppressing penetration of moisture or ions into the semiconductor substrate and ensuring sufficiently charge mobility to improve reliability and a method of manufacturing the same.
A semiconductor device of this disclosure: a semiconductor substrate, which includes: a drift region that has a first conductivity type; a body region that has a second conductivity type and is formed on the drift region, the second conductivity type being opposite to the first conductivity type; and an impurity region that has the first conductivity type and is formed inward from a surface of the body region; a trench, which is formed on a front surface of the semiconductor substrate and reaches the drift region; a control electrode, which is formed in the trench; an oxide film, which is formed between an inner wall of the trench and the control electrode; an electrode, which is connected to the impurity region; and a transistor, which includes a nitride film formed on the front surface of the semiconductor substrate excluding an upper side of the control electrode and a formation position of the electrode, in the semiconductor substrate.
A method of manufacturing a semiconductor device having a transistor of this disclosure includes: forming a semiconductor substrate that includes a drift region that has a first conductivity type; a body region that has a second conductivity type and is formed on the drift region, the second conductivity type being opposite to the first conductivity type; and an impurity region that has the first conductivity type and is formed inward from a surface of the body region; forming a nitride film on a front surface of the semiconductor substrate; patterning the nitride film and the semiconductor substrate and forming a trench on the front surface of the semiconductor substrate to reach the drift region; forming an oxide film on an inner wall of the trench; forming a control electrode in the trench, on which the oxide film is formed; exposing a portion of the impurity region; and forming an electrode to be connected to the portion of the impurity region.
According to this disclosure, it is possible to provide a semiconductor device capable of suppressing penetration of moisture or ions into the semiconductor substrate and ensuring sufficiently charge mobility to improve reliability and a method of manufacturing the same.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and additional features and characteristics of this disclosure will become more apparent from the following detailed descriptions considered with the reference to the accompanying drawings, wherein:
FIG. 1 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device 100 according to an embodiment of this disclosure;
FIG. 2A is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1;
FIG. 2B is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1;
FIG. 2C is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1;
FIG. 2D is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1;
FIG. 2E is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1;
FIG. 2F is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1;
FIG. 2G is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 100 illustrated in FIG. 1;
FIG. 3 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device 200 according to a modified example of the semiconductor device 100 illustrated in FIG. 1;
FIG. 4A is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 200 illustrated in FIG. 3;
FIG. 4B is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 200 illustrated in FIG. 3;
FIG. 4C is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 200 illustrated in FIG. 3; and
FIG. 4D is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device 200 illustrated in FIG. 3.
 DETAILED DESCRIPTION
Embodiments of this disclosure will be described below with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device 100 according to an embodiment of this disclosure. The semiconductor device 100 includes at least a transistor such as a MOSFET or an IGBT having a trench gate structure.
The semiconductor device 100 includes a MOSFET 1 and a guard ring 2 to ensure a withstand voltage of the semiconductor device 100, and these components are provided with a semiconductor substrate S made of a semiconductor such as silicon carbide (SiC). The semiconductor device 100 may be configured to include a plurality of MOSFETs 1.
The semiconductor substrate S includes a front surface serving as an upper surface in FIG. 1 and a back surface serving as a lower surface in FIG. 1. In the following description, out of a thickness direction being an aligned direction of the back surface and the front surface of the semiconductor substrate S, a direction toward the front surface from the back surface is defined as an upward direction, and a direction toward the back surface from the front surface is defined as a downward direction.
The semiconductor substrate S included in the MOSFET 1 is configured with an n-type substrate 10 made of a semiconductor such as silicon or silicon carbide (SiC), an n-type drift region 11 that is formed on the substrate 10 and has a lower impurity concentration than the substrate 10, a p-type body region 12 that is formed on the drift region 11, and a pair of n-type impurity regions 14 that is formed toward the inside from the surface of the body region 12 and has a higher impurity concentration than the drift region 11.
Each of the drift region 11 and the body region 12 may be configured to have a structure in which a plurality of layers having different impurity concentrations are laminated.
The impurity region 14 constitutes a source region of the MOSFET 1. In the MOSFET 1, the substrate 10 constitutes a drain region of the MOSFET 1. Although not being illustrated in the drawings, a drain electrode made of a metal material such as aluminum or titanium is formed on the back surface of the semiconductor substrate S.
The semiconductor substrate S included in the guard ring 2 is configured with the substrate 10, the drift region 11 that is formed on the substrate 10, and a plurality of p-type impurity regions 13 that are formed toward the inside from the surface of the drift region 11. Each of the p-type impurity regions 13 is a ring-shaped region that is formed to surround the MOSFET 1.
The MOSFET 1 includes a trench 15 that is formed on the front surface of the semiconductor substrate S and reaches the drift region 11, a gate electrode 23 that is partially or totally formed in the trench 15, an oxide film 20 that is formed between an inner wall of the trench 15 and the gate electrode 23 and functions as a gate insulating film, a source electrode 24 that is made of a conductive material such as aluminum or titanium and is connected to each of the pair of impurity regions 14, and a nitride film 21 that is formed on the front surface of the semiconductor substrate S and has openings formed between the upper side of the gate electrode 23 and a formation position of the source electrode 24 in the semiconductor substrate S.
The gate electrode 23 is a control electrode used to control an applied voltage, and is made of a conductive material such as polysilicon. By the control of the voltage to be applied to the gate electrode 23, a channel is formed in the body region 12 adjacent to the trench 15, and charges can be transferred to the substrate 10, which is a drain region, from the impurity region 14 through the drift region 11.
An interlayer insulating film 22 including a BPSG film, a PSG film, or the like is formed on the gate electrode 23 and the nitride film 21. The gate electrode 23 is insulated from the source electrode 24 by the interlayer insulating film 22 and the nitride film 21.
The gate electrode 23 is formed beyond the front surface of the semiconductor substrate S in FIG. 1, but may be buried in the semiconductor substrate S. In this configuration, the interlayer insulating film 22 is filled up to an upper surface of the gate electrode 23 in the semiconductor substrate S.
The oxide film 20 is an insulating film made of, for example, silicon dioxide (SiO2). The oxide film 20 is formed by thermal oxidation of the inner wall of the trench formed in the semiconductor substrate S. A thickness of the oxide film 20 is set to, for example, a value in the range from 50 nm to 100 nm according to characteristics of the transistor.
The nitride film 21 is an insulating film made of silicon nitride (SiN), for example, and having high moisture or ion blocking performance. The SiN means a material having a composition SixNy represented by Si3N4.
The nitride film 21 is formed to the front surface of the semiconductor substrate S included in the guard ring 2. In this way, the nitride film 21 is formed on the front surface of the semiconductor substrate S excluding the upper side of the gate electrode 23 and the formation position of the source electrode 24 in the semiconductor substrate S.
A method of manufacturing the semiconductor device 100 configured as above will be described below.
FIGS. 2A to 2G are schematic cross-sectional views illustrating manufacturing processes of the semiconductor device 100 illustrated in FIG. 1.
As illustrated in FIG. 2A, the drift region 11 is formed on the substrate 10 by, for example, epitaxial growth or ion implantation, the body region 12 and the plurality of impurity regions 13 are formed on the surface of the drift region 11 by ion implantation or the like, and an n-type impurity region 14 a is formed on the surface of the body region 12 by ion implantation or the like, thereby forming the semiconductor substrate S. The process of forming the semiconductor substrate S is not limited thereto, and may employ a known method.
Subsequently, as illustrated in FIG. 2B, SiN is deposited on the front surface of the semiconductor substrate S by, for example, a plasma CVD method or a sputtering method, and the nitride film 21 is formed. At this time, the nitride film 21 is formed up to the front surface of the semiconductor substrate S in the guard ring 2.
Next, a mask pattern is formed on the nitride film 21 by, for example, a photolithography method. The mask pattern is a pattern having the opening at a position at which the impurity region 14 a is divided into two parts in a plan view.
Then, the nitride film 21 and the semiconductor substrate S are etched by using the mask pattern and thus are subjected to patterning, and the trench 15 is formed to reach the drift region 11 from the front surface of the semiconductor substrate S, as illustrated in FIG. 2C.
The impurity region 14 a is divided into two parts by the trench 15, and thus the pair of impurity regions 14 are formed as illustrated in FIG. 1.
Subsequently, the semiconductor substrate S, in which the trench 15 is formed, is subjected to thermal oxidation, and thus the oxide film 20 is formed on the inner wall (side surface and bottom surface) of the trench 15 as illustrated in FIG. 2D.
Subsequently, as illustrated in FIG. 2E, for example, a silicon-based conductive material such as polysilicon is deposited in the interior of the trench 15 on which the oxide film 20 is formed and in the opening of the nitride film 21 located above the interior, by using a plasma CVD method or a sputtering method, thereby forming the gate electrode 23. After formation of the gate electrode 23, the interlayer insulating film 22 including a BPSG film or a PSG film is formed on the nitride film 21 and the gate electrode 23 by using a CVD method, for example.
Next, a mask pattern is formed on the interlayer insulating film 22 by using a photolithography method, for example. This mask pattern is a pattern having openings located above at least two impurity regions 14 and the body region 12.
Subsequently, as illustrated in FIG. 2F, openings 24 a are formed in the nitride film 21 and the interlayer insulating film 22 located above the impurity region 14 and the body region 12, by using the mask pattern, and thus a portion of each impurity region 14 and a portion of the body region 12 are exposed.
Next, as illustrated in FIG. 2G, the openings 24 a are filled with a metal material such as aluminum or titanium, by using a sputtering method or a CVD method, and thus the source electrode 24 is formed to be connected to the exposed portion of the impurity region 14 and the exposed portion of the body region 12.
As described above, according to the semiconductor device 100, the nitride film 21 is formed on the front surface of the semiconductor substrate S, and thus there is no region where the oxide film is directly formed on the front surface of the semiconductor substrate S. Accordingly, it is possible to suppress penetration of moisture or ions from the interlayer insulating film 22 and to improve reliability of the device.
Further, according to the semiconductor device 100, the gate insulating film is configured with only the oxide film 20. Accordingly, it is possible to sufficiently ensure charge mobility and form the gate insulating film with high reliability.
According to the semiconductor device 100, as illustrated in FIG. 2D, it is possible to form the oxide film 20 by oxidizing the inner wall of the trench 15 in a state where the surface of the impurity region 14 is covered with the nitride film 21.
Thus, during the formation of the oxide film 20, the impurity region 14 can be suppressed from being oxidized and shrunk. Consequently, it is possible to simplify the ion implantation process used to form the impurity region 14 a illustrated in FIG. 2A and to reduce manufacturing costs.
FIG. 3 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device 200 according to a modified example of the semiconductor device 100 illustrated in FIG. 1.
The semiconductor device 200 has the same configuration as that of the semiconductor device 100 except that the gate insulating film of the MOSFET 1 is formed by the oxide film 30, and the oxide film 30 is formed to cover the surface of the nitride film 21 outside the trench 15.
The oxide film 30 is an insulating film made of, for example, silicon dioxide (SiO2). A material is deposited on the inner wall of the trench formed on the semiconductor substrate S by using a CVD method, and thus the oxide film 30 is formed. A thickness of the oxide film 30 is set to, for example, a value in the range from 50 nm to 100 nm according to characteristics of the transistor.
A method of manufacturing the semiconductor device 200 configured as above will be described below.
FIGS. 4A to 4G are schematic cross-sectional views illustrating manufacturing processes of the semiconductor device 200 illustrated in FIG. 3. The processes until the trench 15 is formed on the semiconductor substrate S are similar to those of the semiconductor device 100, and thus the description thereof is not presented.
After the trench 15 is formed, as illustrated in FIG. 4A, silicon dioxide is deposited on the front surface of the semiconductor substrate S, in which the trench 15 is formed, by using a CVD method, thereby forming the oxide film 30.
Subsequently, as illustrated in FIG. 4B, a silicon-based conductive material such as polysilicon is deposited in the interior of the trench 15 formed with the oxide film 30 and also above the interior by using a plasma CVD method, a sputtering method, or the like, thereby forming a gate electrode 23.
Next, as illustrated in FIG. 4C, an interlayer insulating film 22 including a BPSG film or a PSG film is formed on the oxide film 30 and the gate electrode 23 by using a CVD method, for example.
Subsequently, a mask pattern is formed on the interlayer insulating film 22 by using a photolithography method, for example. The mask pattern is a pattern having openings located above at least two impurity regions 14 and a body region 12.
Next, as illustrated in FIG. 4D, opening 24 b are formed in a nitride film 21, the oxide film 30, and the interlayer insulating film 22 which are located above the impurity region 14 and the body region 12, by using the mask pattern, and thus a portion of the respective impurity regions 14 and a portion of the body region 12 are exposed.
Subsequently, the opening 24 b are filled with a metal material such as aluminum or titanium by using a sputtering method or a CVD method, and thus a source electrode 24 is formed to be connected to the exposed portion of the impurity region 14 and the exposed portion of the body region 12. By these processes, the semiconductor device 200 illustrated in FIG. 3 is formed.
As described above, according to the semiconductor device 200, the nitride film 21 is formed on the front surface of the semiconductor substrate S, and thus there is no region where the oxide film is directly formed on the front surface of the semiconductor substrate S. Accordingly, it is possible to suppress penetration of moisture or ions from the interlayer insulating film 22 and to improve reliability of the device.
Further, according to the semiconductor device 200, the gate insulating film is configured with only the oxide film 30. Accordingly, it is possible to sufficiently ensure charge mobility and form the gate insulating film with high reliability.
Moreover, according to the semiconductor device 200, the oxide film 30 is formed by using the CVD method. Therefore, it is possible to suppress shrinkage of the impurity region in the semiconductor substrate S, and to simplify the manufacturing processes.
In the semiconductor device 100 or the semiconductor device 200, it is preferable, from the viewpoint of ensuring moisture or ion blocking performance, that the thickness of the nitride film 21 be larger than that of the oxide film 20 or oxide film 30. Specifically, the thickness of the nitride film 21 is preferably set to a value larger than 100 nm.
When the thickness of the nitride film 21 is too large, cracks occurs in the film, and thus moisture or ion blocking performance may be deteriorated. Therefore, the upper limit value of the thickness of the nitride film 21 is preferably set to be about 500 nm.
In the semiconductor device 100 or the semiconductor device 200, the nitride film 21 is formed over the entire surface of the semiconductor substrate S excluding the upper side of the region where the gate electrode 23 is buried in the semiconductor substrate S and the location at which the source electrode 24 is formed, and an area ratio of the nitride film 21 to a chip area of the semiconductor device 100 is large.
Since the nitride film has high permittivity, a too large thickness thereof causes an increase in capacity. In the viewpoint of suppressing the increase in capacity and thus suppressing deterioration of characteristics of the semiconductor device 100 or the semiconductor device 200, it is preferable that the thickness of the nitride film 21 be set to be smaller than that of the oxide film 20 or the oxide film 30. Specifically, the thickness of the nitride film 21 is preferably set to be less than 100 nm, and more preferably set to be less than 50 nm.
As the transistor included in the semiconductor device 100 or 200, the MOSFET is exemplified in the above description. However, even when the transistor is an IGBT, the similar effects can be obtained with the similar configuration.
In addition, even when the semiconductor device 100 or 200 is configured such that the p-type and the n-type of the regions and the substrate 10 in the semiconductor substrate S are reversed, the similar effects can be obtained.

Claims (8)

What is claimed is:
1. A semiconductor device comprising:
a semiconductor substrate, which includes:
a drift region that has a first conductivity type;
a body region that has a second conductivity type and is formed on the drift region, the second conductivity type being opposite to the first conductivity type; and
an impurity region that has the first conductivity type and is formed inward from a surface of the body region;
a trench, which is formed on a front surface of the semiconductor substrate and reaches the drift region;
a control electrode, which is formed in the trench;
an oxide film, which is formed between an inner wall of the trench and the control electrode;
an electrode, which is connected to the impurity region;
a transistor, which includes a nitride film formed on the front surface of the semiconductor substrate excluding an upper side of the control electrode and a formation position of the electrode, in the semiconductor substrate; and
a guard ring, which is formed in the semiconductor substrate to surround the transistor and includes an impurity region having the second conductivity type,
wherein the nitride film is formed on the front surface of the semiconductor substrate, in which the guard ring has formed.
2. The semiconductor device according to claim 1, wherein a thickness of the nitride film is smaller than a thickness of the oxide film.
3. The semiconductor device according to claim 2, wherein the thickness of the nitride film is less than 100 nm.
4. The semiconductor device according to claim 1, wherein a thickness of the nitride film is larger than a thickness of the oxide film.
5. The semiconductor device according to claim 4, wherein the thickness of the nitride film is larger than 100 nm.
6. The semiconductor device according to claim 1, wherein, in an outside of the trench, the nitride film covers a surface of the oxide film.
7. A method of manufacturing a semiconductor device having a transistor, comprising:
forming a semiconductor substrate that includes a drift region that has a first conductivity type; a body region that has a second conductivity type and is formed on the drift region, the second conductivity type being opposite to the first conductivity type; and an impurity region that has the first conductivity type and is formed inward from a surface of the body region;
forming a nitride film on a front surface of the semiconductor substrate;
patterning the nitride film and the semiconductor substrate and forming a trench on the front surface of the semiconductor substrate to reach the drift region;
forming an oxide film on an inner wall of the trench;
forming a control electrode in the trench, on which the oxide film is formed;
exposing a portion of the impurity region;
forming an electrode to be connected to the portion of the impurity region; and
forming, in the semiconductor substrate, a guard ring including an impurity region having the second conductivity type to surround a region where the transistor of the semiconductor substrate is formed,
wherein, in the forming the nitride film, the nitride film is formed on the front surface of the semiconductor substrate, in which the guard ring has formed.
8. The method according to claim 7, wherein, in the forming the oxide film, the oxide film is formed by thermal oxidation.
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