US8872335B2 - Electronic device and method of manufacturing same - Google Patents
Electronic device and method of manufacturing same Download PDFInfo
- Publication number
- US8872335B2 US8872335B2 US11/781,282 US78128207A US8872335B2 US 8872335 B2 US8872335 B2 US 8872335B2 US 78128207 A US78128207 A US 78128207A US 8872335 B2 US8872335 B2 US 8872335B2
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- substrate
- polymer layer
- connection elements
- electronic system
- semiconductor chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
- H05K2203/0783—Using solvent, e.g. for cleaning; Regulating solvent content of pastes or coatings for adjusting the viscosity
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
- H05K2203/306—Lifting the component during or after mounting; Increasing the gap between component and PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to an electronic system, and a method of manufacturing the electronic device.
- bonding wires have often been replaced by bumps placed on the chip surface.
- bumps helps increasing the number of input/output channels for a given integrated circuit area.
- stacking of integrated circuits one atop the other, before molding the stack has been introduced.
- Bump bonding as well as stacking chips or substrates, pose several challenges. For this and other reasons, there is a need for the invention disclosed below.
- first substrate comprising first connection elements on a first surface of the first substrate
- second substrate comprising second connection elements on a first surface of the second substrate
- applying a polymer layer to at least one of the two first surfaces; attaching the first connection elements to the second connection elements; and causing the polymer to swell during or after the attachment.
- FIGS. 1 a - 1 e disclose a first method wherein, before swelling, the polymer layer is applied to only one substrate.
- FIGS. 2 a - 2 e disclose a further method wherein, before swelling, the polymer layer is applied to a first and a second substrate.
- FIGS. 3 a - 3 c disclose a further method wherein, before swelling, the polymer layer is structured by a photolithographic process on both a first and a second substrate.
- FIG. 4 discloses an embodiment wherein a swollen polymer layer adheres to a first wafer and a second wafer.
- FIG. 5 discloses an embodiment wherein a swollen polymer layer adheres to a semiconductor chip and a printed circuit board.
- FIG. 6 discloses an embodiment wherein a swollen polymer layer adheres to a semiconductor chip and an interposer.
- FIG. 7 discloses an embodiment wherein a non-swollen polymer layer adheres to a semiconductor chip.
- FIGS. 1 a - 1 e disclose five steps according to a first method of manufacturing an electronic system that facilitates an attachment of a first substrate 1 to a second substrate 4 .
- the method is applicable to a large variety of substrates.
- first substrate 1 may be a semiconductor chip or semiconductor device that is to be attached to a second substrate 4 , e.g. an interposer, ceramic substrate, laminate substrate, glass substrate, a leadframe, a semiconductor substrate (chip or wafer), an encapsulated integrated circuit, an epoxy laminate (FR4), or a printed circuit board.
- first substrate 1 may be any of the substrates that the second substrates 4 can be.
- FIGS. 1 a - 1 e will be described as representing the mounting of a semiconductor chip to a printed circuit board.
- First substrate 1 (semiconductor chip) comprises first connection elements 13 on a first surface 11 of the semiconductor chip 1 .
- the connection elements may be an array of metal elements protruding from the first surface and having the shape of balls, pillars, pads, bumps or, in particular, solder balls or solder bumps.
- the connection elements 13 are rigidly attached to the semiconductor chip 1 .
- the application of the connection elements 13 onto the semiconductor chip 1 may be conducted using conventional methods, like plating, solder paste printing, sputtering, or lift-off.
- connection elements 13 may well vary between some micrometers, e.g. 5 micrometers, and 1000 micrometers, depending on the application.
- the connection elements 13 are usually solder bumps having diameters of typically 400 micrometers.
- the producing of the solder bumps is preferably done on the wafer level, i.e. the wafer is cut into individual chips only after the production of the solder bumps.
- the connection elements 13 serve as input/output terminals that are connected to some electronic circuit, conducting lines, etc., integrated in semiconductor chip 1 .
- FIG. 1 b illustrates a further step wherein a polymer layer 15 has been deposited onto the first surface 11 of the semiconductor chip 1 .
- the deposition of the polymer layer is done on the wafer level to have multiple chips on the wafer covered with the polymer layer 15 in parallel.
- the polymer layer 15 covers the connection elements 13 only partially, or not at all. This is to make sure that the connection elements 13 are exposed to make an electrically conducting connection when placing the chip 1 onto second substrate 4 .
- the polymer layer 15 may cover the connection elements 13 completely if, during the attachment of the first connection elements 13 to the second connection elements 43 , the polymer layer 15 is removed in the contact region.
- the polymer layer 15 in the contact regions of the first connection elements 13 and the respective second connection elements 43 may be removed by, e.g., pressure or friction exerted by the first connection elements 13 and the second connection elements 43 on the polymer layer.
- FIG. 1 c discloses schematically the step wherein the semiconductor chip 1 is turned upside down and moved towards the first surface 41 of the second substrate 4 (printed circuit board (PCB)) to connect first connection elements 13 with second connection elements 43 .
- the second connection elements 43 may be, for example, copper pads printed onto the printed circuit board. As shown in FIG. 1 c , the positions of the copper pads 43 are matched to the positions of the solder bumps 13 to make sure that each second copper pad 43 makes electronic contact with a respective solder bump 13 when placing the semiconductor chip 1 onto the PCB 4 .
- FIG. 1 d schematically illustrates the situation wherein the solder bumps 13 are rigidly connected with copper pads 43 .
- the two may be attached to each other by placing the two substrates on top of each other and introducing the two into an oven.
- the oven temperature needs to be high enough to make sure that the solder bumps 13 begin to melt such that the solder bumps 13 rigidly connect with the copper pads 43 .
- typical soldering temperatures are in a region between 100° C. and 400° C.
- gap 19 between chip 1 and PCB 4 makes sure that the surface of polymer layer 15 is accessible for a fluid or gaseous solvent. This may be important for the subsequent step that causes the polymer layer to swell.
- the attachment of the first connection elements 13 with the second connection elements 43 can also be carried out with other conventional methods depending on the type of substrate and the type of connection elements.
- Such attachment processes may be, for example, diffusion soldering, welding, gluing, and the like.
- FIG. 1 e discloses the result of a further step of the method wherein polymer layer 15 has been caused to swell to become a swollen polymer layer 16 .
- the polymer expands to fill the gap 19 and reach the first surface 41 of PCB 4 .
- the polymer layer 15 also bonds to the first surface 41 of the PCB 4 .
- the swollen polymer layer 16 prevently polymer layer 15
- the swollen polymer layer 16 can support the connection elements 13 , 43 holding the first substrate 1 to the second substrate 4 .
- the swelling of polymer layer 15 eliminates gap 19 between the first substrate 1 and the second substrate 4 , corrosion of the connection elements 13 , 43 , delamination and other reliability problems of electronic devices can be eliminated.
- the swelling of the polymer layer may also help reducing the thermo-mechanical stress resting on the connection elements during thermal cycling caused in the process of device manufacturing or device operation.
- Thermo-mechanical stress arises when the materials of the two substrates 1 , 4 have deviating coefficients of thermal expansion (CTE). In this case, during thermal cycling, the substrates 1 , 4 expand or shrink at different rates. Due to the rigidity of the connections between the first and second connection elements 13 , 43 , the thermo-mechanical stress may lead to shear forces on the connection elements 13 , 43 that can break the connections.
- a swollen polymer layer 16 between the first and second substrates 1 , 4 can absorb some of the shear forces and, therefore, lower the destructive forces on the connection elements.
- the swelling of the polymer layer 15 may be caused by applying a fluid or gaseous agent to the polymer layer.
- a fluid or gaseous agent By choosing an agent that weakens the bonding of the polymer molecule chains, the volume of the polymer increases if exposed to the agent. Further, as it turns out, the broken molecule chains of the expanding polymer can be sufficient reactive to bond well with other surfaces. This may be seen as a reason for the polymer layers to bond well with the first surfaces of the substrates when swelling. This effect is also known as “solvent welding”.
- the “solvent welding” may be the basis for the observation that the shear forces between the first and second connection elements 13 , 43 decrease when swelling the polymer layer 15 between the first and second substrates 1 , 4 .
- the gap 19 between the first substrate 1 and the second substrate 2 that provides an easy access for the fluid or gaseous agents to reach and diffuse into the polymer layer 15 efficiently.
- the swelling process is also a self-limiting process since, after the gap 19 has been filled with the swollen polymer; the agents that cause the swelling cannot reach the surface of the polymer layer anymore.
- the self-limiting process prevents that the swelling polymer layer 15 can break the connection elements when expanding against the first and the second substrates.
- the first connection elements 13 extend through the polymer layer 15 when placing the first substrate 1 onto the second substrate 4 .
- polymethyl methacrylate PMMA
- poly (methyl 2-methylpropenoate) is used as polymer for the polymer layer.
- the PMMA may be exposed, for example, to benzene, methyl chloride, acetone, or ethyl acetate, to swell.
- exposing PMMA to acetone can make the volume of the polymer increase by 10 Vol. %.
- polyvinyl chloride may be used as polymer for the polymer layer. After attaching the first and second substrates with each other, the PVC may be exposed, for example, to acetone to swell. In this case, the PVC may swell by 50 Vol %.
- polycarbonate may be used as polymer for the polymer layer. After attaching the first and second substrates with each other, the PC may be exposed, for example, to methyl chloride to cause the polycarbonate to swell.
- polyimide may be used as polymer for the polymer layer. After attaching the first and second substrates with each other, the polyimide may be exposed, for example, to hydrazine to cause the polyimide to swell.
- polyurethane may be used as polymer for the polymer layer. After attaching the first and second substrates with each other, the PUR may be exposed, for example, to methyl chloride, acetone, ethyl acetate, or tetrahydrofurane, to cause the polyurethane (PUR) to swell.
- the exposure time of the polymer layers to the respective agents depends on the time it takes for the solvent to diffuse through the full volume of the polymer layer, e.g. on the thickness of the polymer layer, and on the concentration for the solvent. Also, the exposure time may be chosen to meet a certain swelling percentage. Generally, the swelling should increase the polymer volume by more than 5 Vol. %. On the other hand, if the polymer layer is exposed to a solvent too long, the polymer may dissolve completely and disappear from the substrates. Generally, choosing the right exposure time and concentration of the solvents depends on the details of the set-up and is within the scope of what a skilled person does routineously.
- the two may further be exposed to a drying process that drives the solvent out of the polymer layer 15 .
- the drying can be accelerated by exposing the swollen polymer layer to a heightened temperature, e.g. above room temperature, and/or a reduced pressure.
- the drying of the polymer leads to a shrinkage of the polymer layer volume that, due to the good adhesion of the polymer to the substrate surfaces, pulls the two substrates to each other. This further reduces the forces resting on the connection elements 13 , 43 .
- FIGS. 2 a - 2 e disclose five steps according to a further method for attaching a first substrate 1 to a second substrate 4 .
- first substrate 1 may be a semiconductor chip or semiconductor device that is to be attached to a second substrate 4 , e.g. an interposer, ceramic substrate, laminate substrate, glass substrate, a leadframe, a semiconductor substrate (chip or wafer), an encapsulated integrated circuit, an epoxy laminate (FR4), or a printed circuit board.
- first substrate 1 may be any of the substrates that the second substrates 4 can be.
- FIGS. 2 a - 2 e will be described as representing a mounting of a semiconductor chip to a printed circuit board.
- FIGS. 2 a - 2 e illustrate a method that is essentially the same as the one shown in FIGS. 1 a - 1 e .
- FIGS. 2 a - 2 e differ from FIGS. 1 a - 1 e in that, in addition to a first polymer layer 15 applied to a semiconductor chip 1 , there is also a second polymer layer 45 applied to the PCB 4 .
- the second polymer layer 45 swells towards the first surface 11 of semiconductor chip 1 .
- the two polymer layers 15 , 45 unite to form a single swollen polymer layer 16 .
- FIG. 2 a discloses exemplary a first step according this method wherein, after application of a photo-sensitive first polymer layer 45 to second substrate 4 (PCB), a photolithographic step is conducted to structure the photo-sensitive second polymer layer 45 .
- the structuring of the photo-sensitive polymer layer 45 is to remove the polymer 45 from the connection elements 43 .
- the photo-sensitive second polymer layer 45 may be, for example, polymethyl methacrylate (PMMA) or poly (methyl 2-methylpropenoate).
- PMMA is a positive photo-sensitive material that becomes soluble once it has been exposed to radiation with a wave length smaller than 250 nm.
- the PMMA can be made soluble selectively in regions that cover the connection elements 43 . This way, after washing the PCB 4 and the illuminated PMMA layer in a developer, the connection elements 43 are opened again ( FIG. 2 b ).
- FIG. 2 c discloses the step of placing a first substrate 1 onto the PCB 4 .
- first substrate 1 may be a semiconductor chip, wafer, or semiconductor device that is to be attached to the PCB. It may also be an interposer, ceramic substrate, laminate substrate, glass substrate, a leadframe, an encapsulated integrated circuit, an epoxy laminate (FR4), or a printed circuit board.
- a first polymer layer 15 has been applied to the first surface 11 of the semiconductor chip 1 in the same way as described in FIG. 1 b .
- first substrate 1 is a semiconductor chip 1 as described in FIGS. 1 a - 1 e .
- the first polymer layer 15 is the same material as the second polymer layer 45 , i.e. PMMA.
- FIG. 2 d discloses a situation after having soldered the semiconductor chip 1 to the PCB in the same way as described in FIG. 1 d .
- a gap 19 between the first polymer layer 15 (first PMMA layer) and the second polymer layer 45 (second PMMA layer) has been formed. This is due to the fact that in most regions, the sum of the layer thicknesses of the first PMMA layer 15 and the second PMMA layer 45 is smaller than the sum of the height of the solder bumps 13 protruding from the first surface 11 and the thickness of the copper pads 43 .
- the height of the solder bumps 13 may be 200 micrometers, and the height of the first PMMA layer 15 between the solder bumps 13 may be only 180 micrometer in some regions.
- the thickness of the second polymer layer 45 may be 180 micrometer while the thickness of the pads 43 may be 200 micrometers.
- FIG. 2 e discloses a further step after the polymer layers 15 , 45 have been swollen to reunite to a single swollen polymer layer 16 adhering to the semiconductor chip 1 and the PCB 4 .
- the polymer layer 15 As was described earlier, it is now possible to dry the polymer layer 15 . As mention before, this can be done by a temperature step, e.g. inserting the substrates 1 , 4 with the swollen polymer layer 16 in an oven at a temperature of, say, above room temperature. When drying the swollen polymer layer 16 , the polymer layer may shrink and, as a consequence, pull the first substrate 1 towards the second substrate 4 . This force may help absorbing some of the shear forces that otherwise would rest on the connection elements 13 , 43 alone.
- a temperature step e.g. inserting the substrates 1 , 4 with the swollen polymer layer 16 in an oven at a temperature of, say, above room temperature.
- the polymer layer may shrink and, as a consequence, pull the first substrate 1 towards the second substrate 4 . This force may help absorbing some of the shear forces that otherwise would rest on the connection elements 13 , 43 alone.
- FIGS. 3 a - 3 b disclose a further method of attaching a first substrate 1 to a second substrate 4 .
- first substrate 1 may be a semiconductor chip or semiconductor device that is to be attached to a second substrate 4 , e.g. an interposer, ceramic substrate, laminate substrate, glass substrate, a leadframe, a semiconductor substrate (chip or wafer), an encapsulated integrated circuit, an epoxy laminate (FR4), or a printed circuit board.
- first substrate 1 may be any of the substrates that the second substrates 4 can be.
- FIGS. 3 a - 3 b will be described as representing the mounting of a semiconductor chip 1 to a printed circuit board 4 (PCB).
- PCB printed circuit board 4
- the method according to FIGS. 3 a - 3 b is essentially the same as the one shown in FIGS. 2 a - 2 e .
- it includes the steps of applying a first polymer layer 15 to the first substrate 1 , e.g. a semiconductor chip; applying a second polymer layer 45 to the second substrate 4 , e.g. a printed circuit board (PCB); attaching the first connection elements 15 to the second connection elements 45 ; and causing the first polymer layer 15 and the second polymer layer 45 to swell during or after the attachment.
- a first polymer layer 15 to the first substrate 1
- a second polymer layer 45 e.g. a printed circuit board
- both polymer layers 15 , 45 have been structured to remove the polymer from the first and second connection elements 13 , 43 . This is to make sure that the first and second connection elements 13 , 43 are reliably electrically connected to each other when placed onto each other. Further, with the structuring, both polymer layers 15 , 45 can be made to have defined layer thicknesses, D 1 and D 2 , before the swelling. As a result, the gap 19 between the two polymer layers 15 , 45 also has a defined width G.
- the attachment of the first substrate 1 to the second substrate 4 by the swelling polymer layers 15 , 45 is the tighter the smaller the ratio of the gap width G to the sum of the polymer layer thicknesses D 1 and D 2 is, before the swelling.
- the first and second connection elements 13 , 43 may each have a thickness of 100 micrometer, while the first and second polymer layers 15 , 45 may each have a thickness of only 90 micrometer. Accordingly, the thickness of the gap G is 20 micrometer. Therefore, for making contact between the first and the second polymer layer, the first and second polymer layers need to swell by 10 Vol. %. Note that the dimensions for the layer thickness and gap size depend also on how well the layer thickness can be controlled and by how much the polymer layers can swell.
- the two polymer layers 15 , 45 After swelling, the two polymer layers 15 , 45 have joint to form a single swollen polymer layer 16 that is tightly bonded to the surfaces of the first and second substrates 1 , 4 . Further, after a drying process during which the swollen polymer layer 16 shrinks, the swollen polymer layer 16 exerts a permanent force to the first and second substrates 1 , 4 towards each other. This force helps absorbing some of the shear forces that otherwise would rest on the connection elements 13 , 43 during the temperature cycles that electronic devices undergo during manufacture and operation.
- the swollen polymer layer 16 between first and second substrates 1 , 4 is distinguished over conventional underfill material in that the sidewalls of the polymer layer may extend from the first surfaces 1 , 41 of the first or second substrate at a protruding angle ⁇ equal or larger than 55 degrees with respect to the respective first surface 1 , 41 .
- the protruding angle ⁇ is taken to enclose the polymer layer material 16 .
- the protruding angle ⁇ is about 120 degrees which gives the sidewall a convex shape.
- the large protruding angle ⁇ is due to the swelling of the polymer layer.
- the protruding angle ⁇ in FIG. 3 c may become smaller after the polymer layer 16 has been dried. In this case the protruding angle may become smaller than 90 degrees so that the convex shape of the sidewalls shown in FIG. 3 c turns into a concave shape.
- the protruding angle ⁇ of the swellable polymer layers is larger than the protruding angle of an underfill material that has been introduced between the first and second substrate by capillary forces.
- connection elements 13 of the first substrate 1 are pads, e.g. copper pads, instead of solder bumps.
- the attachment of the first pads 13 to the second pads 43 may be carried out in various ways, for example by welding. Alternatively, the welding may be left out since it may be sufficient to have the swollen polymer layer 16 alone tie the first substrate 1 to the second substrate 4 . Due to the shrinking of the swollen polymer layer 16 , the first and second connection elements 13 , 43 are sufficiently pressed against each other to make a reliable electric contact. Note that, if connecting the first pads 13 to the second pads 43 without welding, it may be advantageous to cover the pads with a layer of gold to avoid corrosion of the pad surfaces and to provide for a good electric contact between the two pads.
- soldering of the connection elements, as well as swelling and drying of the polymer layer may be carried out in an oven that promotes the soldering process by heating the electronic device, delivers the agents for swelling the polymer layers and, after pumping the agents out of the oven, delivers the heat necessary for drying the swollen polymer layer.
- the swelling of the polymer layers can also be induced in ways other than those described above.
- a chemical may be used to cause the polymer to swell.
- the chemicals or agents may be introduced to the polymer layer in gaseous form or by a fluid, e.g. by introducing the electronic device into a bath that contains the respective agent or chemical.
- the polymer layer 15 may be a layer that, before attaching the first connection elements 13 to the second connection elements 43 , is pressed together and swells already by the mere application of heat.
- FIGS. 4-6 illustrate some of the many electronic devices that can be manufactured with the methods described above.
- FIG. 4 is a schematic drawing showing a first wafer 101 having a first surface 111 attached to the first surface 141 of a second wafer 104 .
- the two wafers are electrically connected with each other via the first connection elements 113 and second connection elements 143 that touch each other at soldered joints 114 .
- FIG. 4 further discloses a swollen polymer layer 16 adhering to the first surface 111 of first wafer 101 and to the first surface 141 of second wafer 104 .
- the swollen polymer layer 16 may be produced in a way as described for FIGS. 3 a - 3 b .
- the swollen polymer layer 16 supports the connection elements 113 , 143 to hold the first wafer 101 to the second wafer 104 .
- connection elements 113 , 143 are shown to be spaced apart, it may desirable to have the polymer layer structured in such a way that after swelling, the swollen polymer layer 16 adjoins to the connection elements 113 , 114 to eliminate any voids between the two wafers. This way, the swollen polymer layer 16 can protect the connection elements 113 , 143 against moisture and corrosion.
- Stacking the two wafers on top of each other facilitates a high level of system integration. Further, since the soldering, application of the polymer layers, structuring of the polymer layers, swelling of the polymer layers and drying of the polymer layers is done on the wafer level, the process can be applied to the many integrated circuits on the wafers in parallel. Accordingly, dicing of the wafers is carried out after the stacking of the two wafers.
- FIG. 5 discloses schematically a further embodiment wherein the first substrate 201 is a semiconductor chip that is mounted to a second substrate 204 that in this embodiment is a printed circuit board.
- the semiconductor chip 201 is electrically connected to the copper pads 43 of PCB 204 through an array of solder bumps 13 that are rigidly attached to a first surface 211 of the semiconductor chip.
- the solder bumps 13 have been soldered to the copper pads 43 .
- the diameters of the solder bumps 13 are typically in the range of 50 to 200 micrometers; accordingly, the distance between the semiconductor chip 201 and the PCB 204 is of the same order. Therefore, when applying the polymer layer to either the semiconductor chip 201 or the PCB 204 , the polymer layer should have a thickness of typically 70 to 90 percent of the bump diameters in order to have the polymer layer 15 bond well to either the semiconductor chip 201 or the PCB 204 .
- FIG. 5 discloses the polymer layer 16 after swelling and adhering to the semiconductor chip 201 and the PCB 204 .
- the swollen polymer layer 16 may have been produced in a way as described in FIGS. 1 a - 1 e or FIGS. 2 a - 2 e .
- the polymer layer 16 has been applied to the semiconductor chip before the dicing of the wafer.
- the swelling of the polymer layer was carried out after, or during, the process of soldering the chip to the PCB.
- FIG. 6 discloses schematically a further embodiment wherein the first substrate 301 is a silicon chip and the second substrate 304 is an interposer.
- the interposer is meant to fan-out the densely disposed input/output terminals 13 (solder bumps) to allow for a larger connection pitch to the outside, represented by the larger solder balls 22 .
- a larger connection pitch and larger solder balls 22 make it easier for a customer to mount the electronic device to a standard PCB with standard equipment.
- the diameter of the large solder balls 22 is in the order of 500 to 1000 micrometers.
- semiconductor chip 301 is comprised with an array of solder balls 13 having diameters in a range of typically 50 to 200 micrometers.
- the semiconductor chip 301 is soldered onto the interposer 304 by soldering the solder balls 13 to the pads 43 of laminated to the interposer 304 .
- the semiconductor chip 204 is held to the interposer 304 by means of the swollen polymer layer 16 adhering to the semiconductor chip 301 and the interposer 304 .
- the swollen polymer layer 16 may have been applied to the semiconductor chip 301 on the wafer level, i.e. before dicing the wafer.
- the thickness of the polymer layer, before swelling, was chosen to be in the order of 50 to 100 micrometers, and to be smaller than the diameter of the solder bumps 13 . This is to make sure that space remains for the polymer layer to swell between the semiconductor chip 301 and the interposer 304 .
- the interposer 304 of FIG. 6 includes one or more metallization layers for fanning out the signals from the semiconductor chip 301 to the solder balls 22 (or vice versa).
- interposer 304 may comprise one or several vias 24 in order to direct signals from the interposer surface 41 facing the semiconductor chip 301 to the opposite surface to which the large solder balls 22 are attached.
- the material of the interposer is preferably a laminate that has a CTE similar to the CTE of a PCB (not shown). This way, the shearing forces exerted by the PCB and the interposer 304 on the large solder bumps 22 during thermal cycling are negligible. As a consequence, it is not necessary to apply an underfill material between the PCB and the interposer 304 for stabilizing the system.
- a swollen polymer layer 16 is located between the semiconductor chip 301 and the interposer 304 .
- the polymer layer 16 may have been applied to the semiconductor chip 301 on the wafer level, i.e. before the dicing of the respective wafer.
- the polymer layer 16 may have been applied to the interposer 304 , or to the interposer 304 and the semiconductor chip 301 .
- the polymer layer is made to swell to form the swollen polymer layer 16 that adheres to the semiconductor chip 301 and the interposer 304 .
- FIG. 6 discloses further mould material 20 encapsulating the semiconductor chip 304 to protect it from damaging mechanical or environmental influence.
- the molding material 20 is usually a resin that is applied in a mould at a temperature of about 150 degrees.
- FIG. 7 discloses a further embodiment wherein the substrate 401 is a semiconductor device comprising an array of connection elements 13 attached to a first surface 11 of the semiconductor device.
- the semiconductor device may be a naked semiconductor chip onto which the connection elements 13 have been attached by one of the conventional methods, as was explained in FIG. 5 .
- the semiconductor device 401 may be a packaged semiconductor chip that has been mounted to a substrate or leadframe, and that has been encapsulated in a mould, as was explained in FIG. 6 .
- connection elements 13 in FIG. 7 have each a proximal end 24 that is in direct connection with the first surface 11 of the semiconductor device 11 , and a distal end 26 that represents the location of the connection element that is the furthest away from the proximal end 24 .
- the distance D represents the distance between the proximal end 24 of a connection element and the distal end 26 of the connection element 26 .
- the distance D defines the distance of the first surface 411 of the semiconductor device to the plane of a circuit board (not shown in FIG. 7 ) to which the semiconductor device 11 is to be mounted.
- connection elements 13 are solder bumps, it should be noted that the embodiment also would work, if the connection elements 13 are pillars, pads or any other electrically conducting structure that is rigidly connected and protrudes vertically from the first surface 11 .
- FIG. 7 further discloses a swellable polymer layer 15 that is applied to the first surface 411 .
- the polymer layer 15 has a thickness T that corresponds to about 80% of the distance D. This way, when soldering the semiconductor device 401 to a circuit board, the polymer layer 15 does not touch the circuit board. As a consequence, gaseous or fluid agents can be introduced into the gap between the polymer layer 15 and the circuit board in order to swell the polymer layer 15 until the polymer layer reaches and bonds to the surface of the circuit board.
- the connection elements 13 are encapsulated by the swollen polymer, which protects the connection elements against corrosion and possibly relieves the connection elements 13 from thermo-mechanical stress. Note that the process described in connection with FIG. 7 may be conducted in a similar way as described in FIGS. 1 c - 1 e.
- connection elements 13 are electrically disconnected.
- semiconductor device 401 with the polymer layer 15 can be transported, sold and handled without being connected to a circuit board.
- This aspect is technically and commercially important since the production of semiconductor devices and the mounting of semiconductor devices to circuit boards is usually done by different manufacturers that are at different locations, and have different tools and equipment. Therefore, the application of a swellable polymer layer to semiconductor devices as a preparation for a more reliable assemblage of the semiconductor devices to a circuit board contributes significant value to the semiconductor devices.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Wire Bonding (AREA)
Abstract
Description
Claims (21)
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US11/781,282 US8872335B2 (en) | 2007-07-23 | 2007-07-23 | Electronic device and method of manufacturing same |
DE102008034159A DE102008034159A1 (en) | 2007-07-23 | 2008-07-22 | Electronic component and method for its production |
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US11/781,282 US8872335B2 (en) | 2007-07-23 | 2007-07-23 | Electronic device and method of manufacturing same |
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US20090026607A1 US20090026607A1 (en) | 2009-01-29 |
US8872335B2 true US8872335B2 (en) | 2014-10-28 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10910338B2 (en) * | 2016-08-01 | 2021-02-02 | Samsung Display Co., Ltd. | Electronic device having an under-fill element, a mounting method of the same, and a method of manufacturing a display apparatus having the electronic device |
US20210111140A1 (en) * | 2019-10-11 | 2021-04-15 | Samsung Electronics Co., Ltd. | Semiconductor packages and methods of manufacturing the semiconductor packages |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6856009B2 (en) * | 2003-03-11 | 2005-02-15 | Micron Technology, Inc. | Techniques for packaging multiple device components |
US20090200663A1 (en) * | 2008-02-11 | 2009-08-13 | Daubenspeck Timothy H | Polymer and solder pillars for connecting chip and carrier |
DE102009003079A1 (en) * | 2009-05-13 | 2010-11-18 | Robert Bosch Gmbh | Damping element for an electrical or electronic component |
US10720257B2 (en) * | 2013-02-15 | 2020-07-21 | Cambrios Film Solutions Corporation | Methods to incorporate silver nanowire-based transparent conductors in electronic devices |
JP6764568B2 (en) * | 2016-11-11 | 2020-10-07 | 住友ゴム工業株式会社 | Semi-conductive roller |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6365840B1 (en) * | 1998-08-03 | 2002-04-02 | Sony Corporation | Electrical connecting device and electrical connecting method |
US20060060987A1 (en) * | 2004-09-23 | 2006-03-23 | Tian-An Chen | High performance amine based no-flow underfill materials for flip chip applications |
US20060134901A1 (en) * | 2004-12-22 | 2006-06-22 | National Starch And Chemical Investment Holding Corporation | Hot-Melt Underfill Composition and Methos of Application |
US20060147719A1 (en) * | 2002-11-22 | 2006-07-06 | Slawomir Rubinsztajn | Curable composition, underfill, and method |
US20070182019A1 (en) * | 2006-02-06 | 2007-08-09 | Fujitsu Limited | Semiconductor device and manufacturing method for the same |
US20070284758A1 (en) * | 2006-05-22 | 2007-12-13 | General Electric Company | Electronics package and associated method |
-
2007
- 2007-07-23 US US11/781,282 patent/US8872335B2/en active Active
-
2008
- 2008-07-22 DE DE102008034159A patent/DE102008034159A1/en not_active Ceased
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6365840B1 (en) * | 1998-08-03 | 2002-04-02 | Sony Corporation | Electrical connecting device and electrical connecting method |
US20060147719A1 (en) * | 2002-11-22 | 2006-07-06 | Slawomir Rubinsztajn | Curable composition, underfill, and method |
US20060060987A1 (en) * | 2004-09-23 | 2006-03-23 | Tian-An Chen | High performance amine based no-flow underfill materials for flip chip applications |
US20060134901A1 (en) * | 2004-12-22 | 2006-06-22 | National Starch And Chemical Investment Holding Corporation | Hot-Melt Underfill Composition and Methos of Application |
US20070182019A1 (en) * | 2006-02-06 | 2007-08-09 | Fujitsu Limited | Semiconductor device and manufacturing method for the same |
US20070284758A1 (en) * | 2006-05-22 | 2007-12-13 | General Electric Company | Electronics package and associated method |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10910338B2 (en) * | 2016-08-01 | 2021-02-02 | Samsung Display Co., Ltd. | Electronic device having an under-fill element, a mounting method of the same, and a method of manufacturing a display apparatus having the electronic device |
US20210111140A1 (en) * | 2019-10-11 | 2021-04-15 | Samsung Electronics Co., Ltd. | Semiconductor packages and methods of manufacturing the semiconductor packages |
US12237290B2 (en) * | 2019-10-11 | 2025-02-25 | Samsung Electronics Co., Ltd. | Semiconductor packages and methods of manufacturing the semiconductor packages |
Also Published As
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DE102008034159A1 (en) | 2009-02-05 |
US20090026607A1 (en) | 2009-01-29 |
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