+

US8343871B2 - Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning - Google Patents

Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning Download PDF

Info

Publication number
US8343871B2
US8343871B2 US12/717,923 US71792310A US8343871B2 US 8343871 B2 US8343871 B2 US 8343871B2 US 71792310 A US71792310 A US 71792310A US 8343871 B2 US8343871 B2 US 8343871B2
Authority
US
United States
Prior art keywords
mask pattern
mask
layer
device layer
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US12/717,923
Other versions
US20110159691A1 (en
Inventor
Tah-Te Shih
Chung-Yuan Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Inotera Memories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inotera Memories Inc filed Critical Inotera Memories Inc
Assigned to INOTERA MEMORIES, INC. reassignment INOTERA MEMORIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, CHUNG-YUAN, SHIH, TAH-TE
Publication of US20110159691A1 publication Critical patent/US20110159691A1/en
Application granted granted Critical
Publication of US8343871B2 publication Critical patent/US8343871B2/en
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Assignors: MICRON TECHNOLOGY, INC.
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INOTERA MEMORIES, INC.
Assigned to JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC.
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Assigned to MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC. reassignment MICRON SEMICONDUCTOR PRODUCTS, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Definitions

  • the present invention relates generally to the field of semiconductor device manufacturing. More particularly, the present invention relates to a method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning technique.
  • the tremendous growth of the semiconductor industry has been achieved by reducing the cost per function of integrated circuits.
  • the semiconductor industry has kept on the historic productivity curve by improving equipment performance, throughput, and uptime; by improving manufacturing yield and efficiency; by improving product quality and reliability; and by increasing wafer size.
  • the most significant contributor to keeping on the historic productivity curve has been by reducing integrated circuit feature sizes through advances in lithography. Reduction in feature sizes allows semiconductor manufacturers to fabricate more devices per wafer, reduce the size (hence the cost) per device, and increase the performance of each device. These advances translate into consumer benefits through electronic products that are smaller, cheaper, and superior in performance.
  • optical lithography systems are used to remove individual parts of a thin film or substrate.
  • the system transfers a pattern from a photo mask to a photoresist using light. Chemicals are then used to etch the pattern in, beneath the photoresist.
  • the wafer may be heated in order to remove the excess moisture from the wafer surface.
  • a photoresist is then applied through spin coating. Once it is reheated or baked, driving away any lingering solvent, the resist is then exposed to the light pattern. This exposes the basic pattern to the resist and then allows it to be etched on using a chemical agent. The photoresist can then be removed with the use of a resist stripper.
  • the printing systems used for this process require a mask that lets in some light while keeping out other rays, creating a specific pattern. This type of mask lithography is well known in the art and is most commonly used in industries.
  • Double patterning technique utilizing self-aligned spacer is also known in the art. For example, a spacer layer is formed by deposition on the previous pattern, followed by etching to remove all the spacer layer material on the horizontal surfaces, leaving only the spacer layer material on the sidewalls. By removing the original patterned feature, only the spacer is left. Since there are two spacers for every line, the line density has now doubled.
  • the spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.
  • the spacer approach is unique in that with one lithographic exposure, the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes.
  • the above-described double patterning technique utilizing self-aligned spacer has several drawbacks such as corner rounding or variation of the feature size across the wafer when using the spacer as an etching hard mask.
  • drawbacks such as corner rounding or variation of the feature size across the wafer when using the spacer as an etching hard mask.
  • a method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning includes providing a device layer; forming a first mask pattern on the device layer; forming a second mask pattern on the first mask pattern, wherein the second mask pattern partially covers the first mask pattern; selectively etching the device layer not covered by the first and second mask patterns to thereby form a first trench therein; removing the first mask pattern not covered by the second mask pattern to form an intermediate mask pattern; depositing a mask material layer to fill the first trench and cover the intermediate mask pattern; polishing the mask material layer to expose a top surface of the intermediate mask pattern, thereby forming a third mask pattern; selectively removing the intermediate mask pattern to form an opening; and etching the device layer through the opening to thereby form a second trench.
  • FIGS. 1-11 are schematic, cross-sectional diagrams showing a method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning in accordance with one preferred embodiment of this invention.
  • FIGS. 1-11 are schematic, cross-sectional diagrams showing a method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning in accordance with one preferred embodiment of this invention.
  • a device layer 10 is provided.
  • the device layer 10 may be a semiconductor substrate including bur not limited to a silicon substrate.
  • the device layer 10 may be a dielectric layer including but not limited to silicon oxide.
  • the device layer 10 may be a multi-layer stack structure including but not limited to polysilicon-tungsten-silicon nitride stack structure.
  • a first mask layer 20 is formed on a top surface of the device layer 10 .
  • the first mask layer 20 has high etching selectivity to the device layer.
  • the device layer 10 is silicon oxide and the first mask layer 20 is polysilicon.
  • a photoresist pattern 30 is formed on the first mask layer 20 .
  • the photoresist pattern 30 may be a plurality of dense line patterns and has a line width to space ratio (L:S) of 1:1.
  • the photoresist pattern 30 As shown in FIG. 2 , using the photoresist pattern 30 as an etch mask, an etching process such as an anisotropic dry etching process is carried out to etch away the portion of the first mask layer 20 not covered by the photoresist pattern 30 and expose a portion of the underlying device layer 10 , thereby forming a first mask pattern 20 a .
  • the first mask pattern 20 a may be a plurality of dense line patterns and has a line width to space ratio (L:S) of 1:1. Subsequently, the photoresist pattern 30 is stripped off.
  • a second mask layer 40 is formed on the first mask pattern 20 a .
  • the second mask layer 40 covers the first mask pattern 20 a and fills into the gap or space of the first mask pattern 20 a .
  • the second mask layer 40 has high etching selectivity to both the device layer 10 and the first mask pattern 20 a .
  • the device layer 10 is a silicon oxide layer
  • the first mask pattern 20 a is a polysilicon layer
  • the second mask layer 40 is a carbon layer or an amorphous carbon layer.
  • an anti-reflection coating layer such as a dielectric anti-reflection coating (DARC) layer may be formed on the second mask layer 40 .
  • the aforesaid DARC layer may include but not limited to silicon nitride.
  • the photoresist pattern 50 is formed on the second mask layer 40 .
  • the photoresist pattern 50 may be a plurality of dense line patterns and has a line width to space ratio (L:S) of 1:1.
  • the photoresist pattern 50 laterally shifts a small distance, for example, an offset of about half pitch, such that the photoresist pattern 50 only partially overlaps with the underlying first mask pattern 20 a .
  • the aforesaid “pitch” equals to the sum of the line width and the space.
  • an etching process such as an anisotropic dry etching process is carried out to selectively etch away the second mask layer 40 not covered by the photoresist pattern 50 , thereby forming a second mask pattern 40 a .
  • the vertical sidewall of the second mask pattern 40 a and the vertical sidewall of the first mask pattern 20 a together define an opening 40 b .
  • the width of the opening 40 b is about half of the original space of the first mask pattern 20 a.
  • an etching process such as an anisotropic dry etching process is carried out to selectively etch the device layer 10 not covered by the etching hard mask 60 , thereby forming a first trench 100 .
  • the second mask pattern 40 a alone is used as an etching hard mask and an etching process such as an anisotropic dry etching process is then carried out to selectively remove the first mask pattern 20 a not covered by the second mask pattern 40 a , thereby forming an intermediate mask pattern 20 b in a self-aligned fashion.
  • This etching step may be deemed as a trimming step of the first mask pattern, in one aspect, and this etching step only selectively etches the first mask pattern 20 a but leaves the second mask pattern 40 a and the device layer 10 substantially intact.
  • a third mask layer 140 is deposited on the device layer 10 .
  • the third mask layer 140 covers the intermediate mask pattern 20 b and fills into the first trench 100 and the space of the intermediate mask pattern 20 b .
  • the second mask pattern 40 a may be optionally removed prior to the deposition of the third mask layer 140 .
  • the third mask layer 140 and the second mask pattern 40 a may be made of the same material, for example, carbon or amorphous carbon, which can be deposited by conventional plasma-enhanced chemical vapor deposition (PECVD) methods, but not limited thereto.
  • PECVD plasma-enhanced chemical vapor deposition
  • the third mask layer 140 and the second mask pattern 40 a may be made of different materials.
  • the third mask layer 140 must has high etching selectivity to both the intermediate mask pattern 20 b and the device layer 10 .
  • CMP chemical mechanical polishing
  • the third mask pattern 140 a is used as an etching hard mask an etching process such as an anisotropic dry etching process is then carried out to selectively etch away the intermediate mask 20 b , thereby forming an opening 140 b.
  • an etching process such as an anisotropic dry etching process is then carried out to selectively etch away the intermediate mask 20 b , thereby forming an opening 140 b.
  • the third mask pattern 140 a is used as an etching hard mask and an etching process such as an anisotropic dry etching process is then carried out to etch the device layer 10 through the opening 140 b thereby forming a second trench 102 in the device layer 10 , wherein each of the second trench 102 is formed between two of the first trenches 100 .
  • the first trench 100 and the second trench 102 may have the same trench depth. However, it is understood that the first trench 100 and the second trench 102 may have different trench depths in another embodiment.
  • the third mask pattern 140 a is removed, as shown in FIG. 11 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor device manufacturing. More particularly, the present invention relates to a method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning technique.
2. Description of the Prior Art
The tremendous growth of the semiconductor industry has been achieved by reducing the cost per function of integrated circuits. The semiconductor industry has kept on the historic productivity curve by improving equipment performance, throughput, and uptime; by improving manufacturing yield and efficiency; by improving product quality and reliability; and by increasing wafer size. The most significant contributor to keeping on the historic productivity curve has been by reducing integrated circuit feature sizes through advances in lithography. Reduction in feature sizes allows semiconductor manufacturers to fabricate more devices per wafer, reduce the size (hence the cost) per device, and increase the performance of each device. These advances translate into consumer benefits through electronic products that are smaller, cheaper, and superior in performance.
However, as the semiconductor technology advances to 50 nm node or beyond, for example, it is required to combine extra resolution enhancing techniques such as immersion lithography techniques and/or double patterning techniques in order to fabricate fine pattern of ultra-high density semiconductor devices with feature of 50 nm or less and to elongate the life of today's mainstream 193 nm optical lithography systems.
As known in the art, optical lithography systems are used to remove individual parts of a thin film or substrate. The system transfers a pattern from a photo mask to a photoresist using light. Chemicals are then used to etch the pattern in, beneath the photoresist. To prepare for this process, the wafer may be heated in order to remove the excess moisture from the wafer surface.
A photoresist is then applied through spin coating. Once it is reheated or baked, driving away any lingering solvent, the resist is then exposed to the light pattern. This exposes the basic pattern to the resist and then allows it to be etched on using a chemical agent. The photoresist can then be removed with the use of a resist stripper. The printing systems used for this process require a mask that lets in some light while keeping out other rays, creating a specific pattern. This type of mask lithography is well known in the art and is most commonly used in industries.
Double patterning technique utilizing self-aligned spacer is also known in the art. For example, a spacer layer is formed by deposition on the previous pattern, followed by etching to remove all the spacer layer material on the horizontal surfaces, leaving only the spacer layer material on the sidewalls. By removing the original patterned feature, only the spacer is left. Since there are two spacers for every line, the line density has now doubled. The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example. The spacer approach is unique in that with one lithographic exposure, the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes.
However, the above-described double patterning technique utilizing self-aligned spacer has several drawbacks such as corner rounding or variation of the feature size across the wafer when using the spacer as an etching hard mask. In light of the above, there is a strong need in this industry to provide an improved method for fabricating a very fine pattern of semiconductor device with a feature size of at least 50 nm or below without the above-described drawbacks.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide an improved method for fabricating very fine patterns of semiconductor device in order to solve the above-mentioned prior art problems and shortcomings.
According to the claimed invention, a method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning is provided. The method includes providing a device layer; forming a first mask pattern on the device layer; forming a second mask pattern on the first mask pattern, wherein the second mask pattern partially covers the first mask pattern; selectively etching the device layer not covered by the first and second mask patterns to thereby form a first trench therein; removing the first mask pattern not covered by the second mask pattern to form an intermediate mask pattern; depositing a mask material layer to fill the first trench and cover the intermediate mask pattern; polishing the mask material layer to expose a top surface of the intermediate mask pattern, thereby forming a third mask pattern; selectively removing the intermediate mask pattern to form an opening; and etching the device layer through the opening to thereby form a second trench.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
FIGS. 1-11 are schematic, cross-sectional diagrams showing a method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning in accordance with one preferred embodiment of this invention.
It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
DETAILED DESCRIPTION
One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale.
FIGS. 1-11 are schematic, cross-sectional diagrams showing a method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning in accordance with one preferred embodiment of this invention. As shown in FIG. 1, a device layer 10 is provided. In one embodiment, the device layer 10 may be a semiconductor substrate including bur not limited to a silicon substrate. In another embodiment, the device layer 10 may be a dielectric layer including but not limited to silicon oxide. In still another embodiment, the device layer 10 may be a multi-layer stack structure including but not limited to polysilicon-tungsten-silicon nitride stack structure. A first mask layer 20 is formed on a top surface of the device layer 10.
According to the preferred embodiment, the first mask layer 20 has high etching selectivity to the device layer. For example, the device layer 10 is silicon oxide and the first mask layer 20 is polysilicon. After the formation of the first mask layer 20, a photoresist pattern 30 is formed on the first mask layer 20. According to the preferred embodiment, for example, the photoresist pattern 30 may be a plurality of dense line patterns and has a line width to space ratio (L:S) of 1:1.
As shown in FIG. 2, using the photoresist pattern 30 as an etch mask, an etching process such as an anisotropic dry etching process is carried out to etch away the portion of the first mask layer 20 not covered by the photoresist pattern 30 and expose a portion of the underlying device layer 10, thereby forming a first mask pattern 20 a. According to the preferred embodiment of this invention, the first mask pattern 20 a may be a plurality of dense line patterns and has a line width to space ratio (L:S) of 1:1. Subsequently, the photoresist pattern 30 is stripped off.
As shown in FIG. 3, a second mask layer 40 is formed on the first mask pattern 20 a. The second mask layer 40 covers the first mask pattern 20 a and fills into the gap or space of the first mask pattern 20 a. According to the preferred embodiment of this invention, the second mask layer 40 has high etching selectivity to both the device layer 10 and the first mask pattern 20 a. For example, the device layer 10 is a silicon oxide layer, the first mask pattern 20 a is a polysilicon layer, and the second mask layer 40 is a carbon layer or an amorphous carbon layer. In another embodiment, an anti-reflection coating layer such as a dielectric anti-reflection coating (DARC) layer may be formed on the second mask layer 40. The aforesaid DARC layer may include but not limited to silicon nitride.
Subsequently, a photoresist pattern 50 is formed on the second mask layer 40. According to the preferred embodiment, for example, the photoresist pattern 50 may be a plurality of dense line patterns and has a line width to space ratio (L:S) of 1:1. Notably, the photoresist pattern 50 laterally shifts a small distance, for example, an offset of about half pitch, such that the photoresist pattern 50 only partially overlaps with the underlying first mask pattern 20 a. The aforesaid “pitch” equals to the sum of the line width and the space.
As shown in FIG. 4, using the photoresist pattern 50 as an etch mask, an etching process such as an anisotropic dry etching process is carried out to selectively etch away the second mask layer 40 not covered by the photoresist pattern 50, thereby forming a second mask pattern 40 a. At this point, the vertical sidewall of the second mask pattern 40 a and the vertical sidewall of the first mask pattern 20 a together define an opening 40 b. For example, the width of the opening 40 b is about half of the original space of the first mask pattern 20 a.
As shown in FIG. 5, thereafter, using the first mask pattern 20 a and the second mask pattern 40 a as an etching hard mask 60, an etching process such as an anisotropic dry etching process is carried out to selectively etch the device layer 10 not covered by the etching hard mask 60, thereby forming a first trench 100.
As shown in FIG. 6, after the formation of the first trench 100 in the device layer 10, the second mask pattern 40 a alone is used as an etching hard mask and an etching process such as an anisotropic dry etching process is then carried out to selectively remove the first mask pattern 20 a not covered by the second mask pattern 40 a, thereby forming an intermediate mask pattern 20 b in a self-aligned fashion. This etching step may be deemed as a trimming step of the first mask pattern, in one aspect, and this etching step only selectively etches the first mask pattern 20 a but leaves the second mask pattern 40 a and the device layer 10 substantially intact.
As shown in FIG. 7, a third mask layer 140 is deposited on the device layer 10. The third mask layer 140 covers the intermediate mask pattern 20 b and fills into the first trench 100 and the space of the intermediate mask pattern 20 b. Notably, prior to the deposition of the third mask layer 140, the second mask pattern 40 a may be optionally removed. The third mask layer 140 and the second mask pattern 40 a may be made of the same material, for example, carbon or amorphous carbon, which can be deposited by conventional plasma-enhanced chemical vapor deposition (PECVD) methods, but not limited thereto. Of course, it is understood that the third mask layer 140 and the second mask pattern 40 a may be made of different materials. Most importantly, the third mask layer 140 must has high etching selectivity to both the intermediate mask pattern 20 b and the device layer 10.
As shown in FIG. 8, subsequently, a chemical mechanical polishing (CMP) process is carried out to remove a predetermined upper thickness of the third mask layer 140 until a top surface of the intermediate mask pattern 20 b is revealed, thereby forming a third mask pattern 140 a in a self-aligned fashion.
As shown in FIG. 9, after the CMP process, the third mask pattern 140 a is used as an etching hard mask an etching process such as an anisotropic dry etching process is then carried out to selectively etch away the intermediate mask 20 b, thereby forming an opening 140 b.
As shown in FIG. 10, after the removal of the intermediate mask pattern 20 b, the third mask pattern 140 a is used as an etching hard mask and an etching process such as an anisotropic dry etching process is then carried out to etch the device layer 10 through the opening 140 b thereby forming a second trench 102 in the device layer 10, wherein each of the second trench 102 is formed between two of the first trenches 100. According to the preferred embodiment of this invention, the first trench 100 and the second trench 102 may have the same trench depth. However, it is understood that the first trench 100 and the second trench 102 may have different trench depths in another embodiment. Thereafter, the third mask pattern 140 a is removed, as shown in FIG. 11.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (16)

1. A method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning, comprising:
providing a device layer;
forming a first mask pattern on the device layer;
forming a second mask pattern on the first mask pattern, wherein the second mask pattern partially covers the first mask pattern;
selectively etching the device layer not covered by the first and second mask patterns to thereby form a first trench therein;
after forming the first trench, removing the first mask pattern not covered by the second mask pattern to form an intermediate mask pattern;
depositing a mask material layer to fill the first trench and cover the intermediate mask pattern;
polishing the mask material layer to expose a top surface of the intermediate mask pattern, thereby forming a third mask pattern;
selectively removing the intermediate mask pattern to form an opening; and
etching the device layer through the opening to thereby form a second trench.
2. The method according to claim 1 wherein the device layer is a dielectric layer.
3. The method according to claim 2 wherein the dielectric layer comprises silicon oxide.
4. The method according to claim 1 wherein the device layer is a semiconductor substrate.
5. The method according to claim 4 wherein the semiconductor substrate comprises silicon substrate.
6. The method according to claim 1 wherein the device layer is a multi-layer stack structure.
7. The method according to claim 6 wherein the multi-layer stack structure comprises polysilicon-tungsten-silicon nitride stack structure.
8. The method according to claim 1 wherein the first mask pattern comprises polysilicon.
9. The method according to claim 1 wherein the second mask pattern comprises carbon.
10. The method according to claim 1 wherein the second mask pattern comprises amorphous carbon.
11. The method according to claim 1 wherein the mask material layer and the second mask pattern are composed of the same material.
12. The method according to claim 1 wherein the mask material comprises carbon or amorphous carbon.
13. The method according to claim 1 wherein the first mask pattern comprises a plurality of dense line patterns.
14. The method according to claim 13 wherein line width to space ratio (L:S) of the plurality of dense line patterns is 1:1.
15. The method according to claim 1 wherein an anti-reflection coating layer is provided on the second mask pattern.
16. The method according to claim 1 wherein after forming the second mask pattern on the first mask pattern, the first mask pattern and the second mask pattern together form an etching hard mask with a step structure.
US12/717,923 2009-12-31 2010-03-04 Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning Active 2031-06-21 US8343871B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
TW098146610A TWI409852B (en) 2009-12-31 2009-12-31 Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning
TW098146610 2009-12-31
TW98146610A 2009-12-31

Publications (2)

Publication Number Publication Date
US20110159691A1 US20110159691A1 (en) 2011-06-30
US8343871B2 true US8343871B2 (en) 2013-01-01

Family

ID=44188068

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/717,923 Active 2031-06-21 US8343871B2 (en) 2009-12-31 2010-03-04 Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning

Country Status (2)

Country Link
US (1) US8343871B2 (en)
TW (1) TWI409852B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015047255A1 (en) 2013-09-25 2015-04-02 Intel Corporation Sacrificial material for stripping masking layers
US9117526B2 (en) 2013-07-08 2015-08-25 Macronix International Co., Ltd. Substrate connection of three dimensional NAND for improving erase performance
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9721964B2 (en) 2014-06-05 2017-08-01 Macronix International Co., Ltd. Low dielectric constant insulating material in 3D memory
US10460939B1 (en) 2018-04-17 2019-10-29 United Microelectronics Corp. Patterning method

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103390551B (en) * 2012-05-10 2017-03-01 联华电子股份有限公司 Method for fabricating patterned structure of semiconductor device
US8736069B2 (en) 2012-08-23 2014-05-27 Macronix International Co., Ltd. Multi-level vertical plug formation with stop layers of increasing thicknesses
CN103794490B (en) * 2012-10-30 2017-02-22 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligned double pattern
CN103909464B (en) * 2013-01-09 2017-10-31 华邦电子股份有限公司 Chemical mechanical polishing method and self-alignment method
US8987914B2 (en) 2013-02-07 2015-03-24 Macronix International Co., Ltd. Conductor structure and method
US8993429B2 (en) 2013-03-12 2015-03-31 Macronix International Co., Ltd. Interlayer conductor structure and method
US9214351B2 (en) 2013-03-12 2015-12-15 Macronix International Co., Ltd. Memory architecture of thin film 3D array
US9761489B2 (en) 2013-08-20 2017-09-12 Applied Materials, Inc. Self-aligned interconnects formed using substractive techniques
US9070447B2 (en) 2013-09-26 2015-06-30 Macronix International Co., Ltd. Contact structure and forming method
US8970040B1 (en) 2013-09-26 2015-03-03 Macronix International Co., Ltd. Contact structure and forming method
KR102185281B1 (en) * 2014-01-09 2020-12-01 삼성전자 주식회사 Methods of Fabricating Patterns of Semiconductor Devices Using Self-Aligned Double Patterning Processes
US9343322B2 (en) 2014-01-17 2016-05-17 Macronix International Co., Ltd. Three dimensional stacking memory film structure
US9768175B2 (en) 2015-06-21 2017-09-19 Micron Technology, Inc. Semiconductor devices comprising gate structure sidewalls having different angles
US10802185B2 (en) 2017-08-16 2020-10-13 Lumentum Operations Llc Multi-level diffractive optical element thin film coating
CN109920730B (en) * 2017-12-13 2021-04-20 联华电子股份有限公司 a patterning method
CN113078100B (en) * 2021-03-19 2021-12-17 长江存储科技有限责任公司 Self-aligned imaging method

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030127426A1 (en) * 2002-01-07 2003-07-10 Macronix International Co., Ltd. Method for pitch reduction
US20040192060A1 (en) * 2003-03-20 2004-09-30 Maik Stegemann Method for fabricating a semiconductor structure
US20050272259A1 (en) * 2004-06-08 2005-12-08 Macronix International Co., Ltd. Method of pitch dimension shrinkage
US7064078B2 (en) 2004-01-30 2006-06-20 Applied Materials Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
US20070205438A1 (en) * 2006-03-02 2007-09-06 Werner Juengling Masking process for simultaneously patterning separate regions
TW200809921A (en) 2006-08-07 2008-02-16 Taiwan Semiconductor Mfg Method of lithography patterning
US20080305642A1 (en) * 2007-06-05 2008-12-11 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US20090208886A1 (en) 2008-02-14 2009-08-20 Shin-Etsu Chemical Co., Ltd. Double patterning process

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI229905B (en) * 2003-11-13 2005-03-21 Nanya Technology Corp Method for controlling critical dimension by utilizing resist sidewall protection
TWI303751B (en) * 2004-03-16 2008-12-01 Imec Inter Uni Micro Electr Method of manufacturing a semiconductor device
JP4182125B2 (en) * 2006-08-21 2008-11-19 エルピーダメモリ株式会社 Manufacturing method of semiconductor device
KR100771891B1 (en) * 2006-11-10 2007-11-01 삼성전자주식회사 Micro pattern formation method of semiconductor device using double patterning process

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030127426A1 (en) * 2002-01-07 2003-07-10 Macronix International Co., Ltd. Method for pitch reduction
US20040192060A1 (en) * 2003-03-20 2004-09-30 Maik Stegemann Method for fabricating a semiconductor structure
US7064078B2 (en) 2004-01-30 2006-06-20 Applied Materials Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
US20050272259A1 (en) * 2004-06-08 2005-12-08 Macronix International Co., Ltd. Method of pitch dimension shrinkage
US20070205438A1 (en) * 2006-03-02 2007-09-06 Werner Juengling Masking process for simultaneously patterning separate regions
TW200809921A (en) 2006-08-07 2008-02-16 Taiwan Semiconductor Mfg Method of lithography patterning
US20080305642A1 (en) * 2007-06-05 2008-12-11 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US7576009B2 (en) 2007-06-05 2009-08-18 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US20090208886A1 (en) 2008-02-14 2009-08-20 Shin-Etsu Chemical Co., Ltd. Double patterning process

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Pang et al., Amorphous Carbon Films as Planarization Layers Deposited by Plasma-Enhanced Chemical Vapor Deposition, IEEE Electron Device Letters, vol. 11, No. 9, Sep. 1990, p. 391-393. *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9117526B2 (en) 2013-07-08 2015-08-25 Macronix International Co., Ltd. Substrate connection of three dimensional NAND for improving erase performance
WO2015047255A1 (en) 2013-09-25 2015-04-02 Intel Corporation Sacrificial material for stripping masking layers
EP3061123A4 (en) * 2013-09-25 2017-05-31 Intel Corporation Sacrificial material for stripping masking layers
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9721964B2 (en) 2014-06-05 2017-08-01 Macronix International Co., Ltd. Low dielectric constant insulating material in 3D memory
US10460939B1 (en) 2018-04-17 2019-10-29 United Microelectronics Corp. Patterning method

Also Published As

Publication number Publication date
TWI409852B (en) 2013-09-21
US20110159691A1 (en) 2011-06-30
TW201123266A (en) 2011-07-01

Similar Documents

Publication Publication Date Title
US8343871B2 (en) Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning
US10768526B2 (en) Method of forming patterns
US8288083B2 (en) Methods of forming patterned masks
US7312158B2 (en) Method of forming pattern
US8956962B2 (en) Method for fabricating large-area nanoscale pattern
US20150035064A1 (en) Inverse side-wall image transfer
US10199265B2 (en) Variable space mandrel cut for self aligned double patterning
US7981803B2 (en) Method of forming micro pattern of semiconductor device
US20090170310A1 (en) Method of forming a metal line of a semiconductor device
US11183395B2 (en) Semiconductor device and fabrication method thereof
CN103337476A (en) Method for reducing critical size of copper interconnection groove
CN103346119A (en) Method for decreasing critical size of copper-connection groove
US10056291B2 (en) Post spacer self-aligned cuts
KR100842763B1 (en) Method of forming fine pattern of semiconductor device
CN111986983A (en) Semiconductor structure and forming method thereof
US8930860B2 (en) Layout decomposition method and method for manufacturing semiconductor device applying the same
US20090227108A1 (en) Patterning method in semiconductor manufacturing process
US8110507B2 (en) Method for patterning an active region in a semiconductor device using a space patterning process
KR20070113604A (en) Method of forming fine pattern of semiconductor device
KR100783279B1 (en) Mamufaturing method of semiconductor device
US8329522B2 (en) Method for fabricating semiconductor device
KR100695434B1 (en) Method of forming fine pattern of semiconductor device
KR100650859B1 (en) Method of forming fine pattern of semiconductor device
KR100912958B1 (en) Manufacturing method of fine pattern of semiconductor device
US20240429059A1 (en) Method for improving residue formation after mandrel removal

Legal Events

Date Code Title Description
AS Assignment

Owner name: INOTERA MEMORIES, INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIH, TAH-TE;LEE, CHUNG-YUAN;REEL/FRAME:024032/0007

Effective date: 20091228

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:041675/0105

Effective date: 20170124

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INOTERA MEMORIES, INC.;REEL/FRAME:041820/0815

Effective date: 20170222

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN)

AS Assignment

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050695/0825

Effective date: 20190731

AS Assignment

Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载