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US7994584B2 - Semiconductor device having non-silicide region in which no silicide is formed on diffusion layer - Google Patents

Semiconductor device having non-silicide region in which no silicide is formed on diffusion layer Download PDF

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US7994584B2
US7994584B2 US12/277,456 US27745608A US7994584B2 US 7994584 B2 US7994584 B2 US 7994584B2 US 27745608 A US27745608 A US 27745608A US 7994584 B2 US7994584 B2 US 7994584B2
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diffusion layer
diffusion
silicide
semiconductor device
esd protection
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US20090159973A1 (en
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Takayuki Hiraoka
Kuniaki Utsumi
Tsutomu Kojima
Kenji Honda
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Toshiba Corp
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOJIMA, TSUTOMU, UTSUMI, KUNIAKI, HONDA, KENJI, HIRAOKA, TAKAYUKI
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/314—Channel regions of field-effect devices of FETs of IGFETs having vertical doping variations 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Definitions

  • This invention relates to a semiconductor device and more particularly to a metal oxide semiconductor field-effect transistor (MOSFET) electrostatic discharge (ESD) protection device for preventing a current such as electrostatic surge from flowing into a semiconductor integrated circuit device.
  • MOSFET metal oxide semiconductor field-effect transistor
  • ESD electrostatic discharge
  • the ESD protection device is provided to prevent a current such as electrostatic surge from flowing into the semiconductor integrated circuit device.
  • Some MOSFET ESD protection devices among the above ESD protection devices are designed to enhance the ESD discharging ability by forming silicide unformed portions (non-silicide regions) in drain regions and source regions (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2006-339444). That is, since a current is not concentrated in the silicide portion in a diffusion layer in the portion formed as the non-silicide region, the breakdown voltage of the device acting as the ESD protection device is enhanced.
  • a diffusion layer with the same junction depth as that of a diffusion layer lying below the gate is formed in the non-silicide region in some cases.
  • this method is applied to a transistor for low power source voltage (or low voltage which is hereinafter referred to as LV) used as the ESD protection device, the junction depth of the diffusion layer is reduced and junction leakage may occur in the non-silicide region.
  • the resistance of the non-silicide region is adjusted by using a diffusion layer with the same junction depth as that of a diffusion layer lying below the gate of the LV transistor in the non-silicide region of a transistor for high power source voltage (or high voltage which is hereinafter referred to as HV) used as the ESD protection device.
  • HV high power source voltage
  • a countermeasure against junction leakage is taken by forming a diffusion layer with the same junction depth as that of a diffusion layer lying below the gate of the HV transistor in the non-silicide region of the LV transistor.
  • a semiconductor device which includes first and second metal oxide semiconductor field-effect transistors (MOSFETs) corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein, wherein the first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.
  • MOSFETs metal oxide semiconductor field-effect transistors
  • a semiconductor device which includes a plurality of first metal oxide semiconductor field-effect transistors (MOSFETs) corresponding to first power source voltage, the plurality of first MOSFETs including non-silicide regions formed in drain portions thereof and having no silicide formed therein, first diffusion layers formed in source/drain portions, second diffusion layers formed below gate portions and formed shallower than the first diffusion layer and third diffusion layers formed with the same depth as the second diffusion layer in the non-silicide regions, and a plurality of second MOSFETs corresponding to second power source voltage lower than the first power source voltage, wherein the plurality of second MOSFETs include non-silicide regions formed in drain portions thereof and having no silicide formed therein, fourth diffusion layers formed in source/drain portions, fifth diffusion layers formed below gate portions and formed shallower than the fourth diffusion layer and sixth diffusion layers formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide regions.
  • MOSFETs metal oxide semiconductor field-effect transistors
  • a semiconductor device which includes a plurality of metal oxide semiconductor field-effect transistors (MOSFETs) respectively corresponding to a plurality of power source voltages, and non-silicide regions formed in drain portions of the plurality of MOSFETs and having no silicide formed therein, wherein diffusion layer resistance regions with the same depth as that of LDD diffusion layers of that MOSFET which corresponds to highest power source voltage among the plurality of MOSFETs are formed in the non-silicide regions of the plurality of MOSFETs.
  • MOSFETs metal oxide semiconductor field-effect transistors
  • FIGS. 1A and 1B are cross-sectional views showing an example of the structure of a semiconductor device (MOSFET ESD protection device) according to a first embodiment of this invention.
  • FIG. 2 is a diagram showing the relation between the concentrations of a P ⁇ diffusion layer and a diffusion layer resistance region of the ESD protection device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing method of the ESD protection device according to the first embodiment.
  • FIG. 4 is a cross-sectional view showing a manufacturing method of the ESD protection device according to the first embodiment.
  • FIG. 5 is a cross-sectional view showing the manufacturing method of the ESD protection device according to the first embodiment.
  • FIG. 6 is a cross-sectional view showing the manufacturing method of the ESD protection device according to the first embodiment.
  • FIGS. 7A and 7B are cross-sectional views showing the manufacturing method of the ESD protection device according to the first embodiment.
  • FIGS. 8A and 8B are cross-sectional views showing the manufacturing method of the ESD protection device according to the first embodiment.
  • FIGS. 9A and 9B are cross-sectional views showing an example of the structure of a semiconductor device (MOSFET ESD protection device) according to a second embodiment of this invention.
  • FIGS. 1A and 1B show an example of the structure of a semiconductor device according to a first embodiment of this invention.
  • FIG. 1A shows an ESD protection device used for high voltage (HV) corresponding to first power source voltage and extracted from a plurality of ESD protection devices provided on a semiconductor integrated circuit device
  • FIG. 1B shows an ESD protection device used for low voltage (LV) corresponding to second power source voltage lower than the first power source voltage and extracted from the ESD protection devices.
  • HV high voltage
  • LV low voltage
  • a plurality of element isolation regions (shallow trench isolation [STI]) 12 a , 13 a , 14 a are formed on the surface portion of a P-well region (or a p-type semiconductor substrate formed of silicon, for example) 11 a of an HV ESD protection device 11 A.
  • a P+ region 21 a for a substrate contact is formed on that surface portion of the P-well region 11 a which corresponds to a portion between the element isolation regions 12 a and 13 a.
  • First to third N+ diffusion layers (first diffusion layers) 22 a , 23 a , 24 a with high concentration are selectively formed on those surface portions of the P-well region 11 a which correspond to a portion between the element isolation regions 13 a and 14 a .
  • the first N+ diffusion layer 22 a forms a source region and the second and third diffusion layers 23 a and 24 a form drain regions.
  • Silicide layers 31 a , 32 a , 33 a , 34 a are respectively formed on the surface portions of the P+ region 21 a and first to third N+ diffusion layers 22 a , 23 a , 24 a.
  • a gate electrode (polysilicon gate) 42 a is formed above that portion of the P-well region 11 a which corresponds to a portion between the first and second N+ diffusion layers 22 a and 23 a with a gate insulating film 41 a disposed therebetween.
  • Gate sidewall insulating films 43 a are formed on the sidewall portions of the gate insulating film 41 a and gate electrode 42 a .
  • a P ⁇ diffusion layer 25 a acting as a channel region is formed on that surface portion of the P-well region 11 a which corresponds to a portion lying directly below the gate electrode 42 a (below the gate), that is, a portion between the first and second N+ diffusion layers 22 a and 23 a .
  • a source-side lightly doped drain (LDD) diffusion layer (an N ⁇ layer acting as a second diffusion layer) 26 a used to form an extension region is formed in a position adjacent to the first N+ diffusion layer 22 a on the surface portion of the P ⁇ diffusion layer 25 a .
  • a drain-side LDD diffusion layer (an N ⁇ layer acting as a second diffusion layer) 27 a used to form an extension region is formed in a position adjacent to the second N+ diffusion layer 23 a on the surface portion of the P ⁇ diffusion layer 25 a .
  • the impurity junctions of the LDD diffusion layers 26 a , 27 a are shallower than those of the first to third N+ diffusion layers 22 a , 23 a , 24 a and the depths thereof are controlled according to the first power source voltage.
  • a silicide block 51 a used to form a silicide unformed portion (non-silicide region) is formed above that portion of the P-well region 11 a which corresponds to a portion between the second and third N+ diffusion layers 23 a and 24 a .
  • a P ⁇ diffusion layer 28 a and a diffusion layer resistance region (an N ⁇ layer acting as a third diffusion layer) 29 a acting as a ballast resistor are formed directly under the silicide block 51 a , that is, on that surface portion of the P-well region 11 a which corresponds to the portion between the second and third N+ diffusion layers 23 a and 24 a .
  • the P ⁇ diffusion layer 28 a is formed with the same impurity concentration (distribution) and the same junction depth as those of the P ⁇ diffusion layer 25 a .
  • the diffusion layer resistance region 29 a is formed with the same impurity concentration and the same junction depth as those of the LDD diffusion layers 26 a , 27 a .
  • the diffusion layer resistance region 29 a of the HV ESD protection device 11 A a region that is the same as the LDD diffusion layers 26 a , 27 a lying directly below the gate electrode 42 a or a region that is connected to the surrounding second and third N+ diffusion layers 23 a , 24 a having deep junctions and formed with sufficient depth to contain the silicide layers 33 a , 34 a without causing any problem associated with the junction leakage is used.
  • Symbols 52 a , 53 a , 54 a in the drawing denote contacts respectively connected to the silicide layers 31 a , 32 a , 34 a.
  • a plurality of element isolation regions (STI) 12 b , 13 b , 14 b are formed on the surface portion of a P-well region (or a p-type semiconductor substrate formed of silicon, for example) 11 b of an LV ESD protection device 11 B.
  • a P+ region 21 b for a substrate contact is formed on that surface portion of the P-well region 11 b which corresponds to a portion between the element isolation regions 12 b and 13 b.
  • First to third N+ diffusion layers (fourth diffusion layers) 22 b , 23 b , 24 b with high concentration are selectively formed on that surface portion of the P-well region 11 b which corresponds to a portion between the element isolation regions 13 b and 14 b .
  • the first N+ diffusion layer 22 b forms a source region and the second and third diffusion layers 23 b , 24 b form drain regions.
  • Silicide layers 31 b , 32 b , 33 b , 34 b are respectively formed on the surface portions of the P+ region 21 b and first to third N+ diffusion layers 22 b , 23 b , 24 b.
  • a gate electrode (polysilicon gate) 42 b is formed above that portion of the P-well region 11 b which corresponds to a portion between the first and second N+ diffusion layers 22 b and 23 b with a gate insulating film 41 b disposed therebetween.
  • gate sidewall insulating films 43 b are formed on the sidewall portions of the gate insulating film 41 b and gate electrode 42 b .
  • a P ⁇ diffusion layer 25 b acting as a channel region is formed directly below the gate electrode 42 b (below the gate), that is, on that surface portion of the P-well region 11 b which corresponds to a portion between the first and second N+ diffusion layers 22 b and 23 b .
  • a source-side lightly doped drain (LDD) diffusion layer (an N ⁇ layer acting as a fifth diffusion layer) 26 b used to form an extension region is formed in a position adjacent to the first N+ diffusion layer 22 b on the surface portion of the P ⁇ diffusion layer 25 b .
  • a drain-side LDD diffusion layer (an N ⁇ layer acting as a fifth diffusion layer) 27 b used to form an extension region is formed in a position adjacent to the second N+ diffusion layer 23 b on the surface portion of the P ⁇ diffusion layer 25 b .
  • the impurity junctions of the LDD diffusion layers 26 b , 27 b are shallower than those of the LDD diffusion layers 26 a , 27 a and the depths thereof are controlled according to the second power source voltage.
  • a silicide block 51 b used to form a non-silicide region is formed on that portion of the P-well region 11 b which corresponds to a portion between the second and third N+ diffusion layers 23 b and 24 b .
  • a P ⁇ diffusion layer (seventh diffusion layer) 28 b and a diffusion layer resistance region (an N ⁇ layer acting as a sixth diffusion layer) 29 b acting as a ballast resistor are formed directly under the silicide block 51 b , that is, on that surface portion of the P-well region 11 b which corresponds to a portion between the second and third N+ diffusion layers 23 b and 24 b .
  • the P ⁇ diffusion layer 28 b is formed with the same impurity concentration and the same junction depth as the P ⁇ diffusion layer 25 b .
  • the diffusion layer resistance region 29 b is formed with the same impurity concentration and the same junction depth as the diffusion layer resistance region 29 a . That is, as the diffusion layer resistance region 29 b of the LV ESD protection device 11 B, a region that is different from the LDD diffusion layers 26 b , 27 b lying directly below the gate electrode 42 b and is the same as the LDD diffusion layers 26 a , 27 a lying directly below the gate electrode 42 a of the HV ESD protection device 11 A is used.
  • the diffusion layer resistance region 29 b is formed at the same time as and in the same formation process as the LDD diffusion layers 26 a , 27 a and diffusion layer resistance region 29 a by use of the same mask. As a result, the diffusion layer resistance region 29 b that is formed in a small area and does not cause junction leakage can be easily realized only by using an existing MOSFET formation process (normal transistor formation process).
  • Symbols 52 b , 53 b , 54 b in the drawing denote contacts respectively connected to the silicide layers 31 b , 32 b , 34 b.
  • FIG. 2 shows the relation between the concentrations of the P ⁇ diffusion layer and the diffusion layer resistance region.
  • the LDD structure (HV LDD) of the HV ESD protection device 11 A is used as the ballast resistor of the LV ESD protection device 11 B
  • the LDD structure (LV LDD) of the LV ESD protection device 11 B is used.
  • this is because the junction leakage in the non-silicide region of the LV ESD protection device 11 B can be reduced by using a gentle and deep junction, for example, between the P ⁇ diffusion layer 25 a and the LDD diffusion layers 26 a , 27 a of the HV ESD protection device 11 A.
  • the ESD discharging ability can be enhanced by forming the ballast resistor of the HV LDD structure that is formed of the diffusion layer resistance region 29 b in the non-silicide region of the LV ESD protection device 11 B.
  • the junction depth of the diffusion layer below the gate of the transistor is set to approximately 1 ⁇ 4 the gate length in order to suppress the short channel effect.
  • the gate length of an HV transistor of an input/output portion is set to approximately 400 nm with the transistor technique in which the gate length of an LV transistor is set in a 90 nm-generation
  • the junction depth of a diffusion layer below the gate of the LV transistor is set to 20 to 25 nm
  • the junction depth of a diffusion layer below the gate of the HV transistor is set to approximately 100 nm.
  • FIGS. 11A , 11 B a manufacturing method of the ESD protection device ( FIGS. 11A , 11 B) with the nMOSFET structure described above is simply explained with reference to FIG. 3 to FIGS. 8A and 8B .
  • a plurality of element isolation regions 12 a , 13 a , 14 a and 12 b , 13 b , 14 b are formed on the surface portions of P-well regions 11 a , 11 b by use of an existing MOSFET formation process. Then, P+ regions 21 a , 21 b for substrate contacts and P ⁇ diffusion layers 25 a , 25 b are respectively formed on the surface portions of the P-well regions 11 a , 11 b . After this, gate insulating films 41 a , 41 b and gate electrodes 42 a , 42 b are formed on the P-well regions 11 a , 11 b .
  • a reference symbol 61 in the drawing denotes a mask used at the ion-implantation time in a simplified form.
  • LDD diffusion layers 26 b , 27 b are formed in self-alignment with the gate electrode 42 b in the LV ESD protection device 11 B.
  • LDD diffusion layers 26 a , 27 a are formed in self-alignment with the gate electrode 42 a in the HV ESD protection device 11 A.
  • a diffusion layer resistance region 29 b having the same junction depth as the LDD diffusion layers 26 a , 27 a of the HV ESD protection device 11 A is formed in an area in which a silicide block 51 b is to be formed in the LV ESD protection device 11 B by using the mask 61 having an opening with the width determined by taking the mask misalignment and spread of the diffusion layer into consideration.
  • gate sidewall insulating films 43 a and silicide block 51 a of the HV ESD protection device 11 A are formed and, at the same time, gate sidewall insulating films 43 b and silicide block 51 b of the LV ESD protection device 11 B are formed by using the existing MOSFET formation process.
  • deep N+ diffusion layers 22 a , 23 a , 24 a with high concentration are formed in the source/drain regions of the HV ESD protection device 11 A and, at the same time, deep N+ diffusion layers 22 b , 23 b , 24 b with high concentration are formed in the source/drain regions of the LV ESD protection device 11 B by using the existing MOSFET formation process.
  • silicide layers 31 a , 32 a , 33 a , 34 a and 31 b , 32 b , 33 b , 34 b and contacts 52 a , 53 a , 54 a and 52 b , 53 b , 54 b are formed to complete the HV ESD protection device 11 A and LV ESD protection device 11 B with the structures shown in FIGS. 1A and 1B .
  • the LDD structure (HV LDD) of the HV ESD protection device 11 A is used in the drain portion (non-silicide region) of the LV ESD protection device 11 B. That is, the diffusion layer resistance region 29 b having the same junction depth as the LDD diffusion layers 26 a , 27 a of the HV ESD protection device 11 A is formed directly under the silicide block 51 b of the LV ESD protection device 11 B.
  • the LV ESD protection device 11 B can be formed with the structure of a small area without causing a junction leakage problem. Therefore, a MOSFET ESD protection device that corresponds to low power source voltage and enhances the ESD discharging ability without providing an additional step to the existing MOSFET formation process can be realized.
  • FIGS. 9A and 9B show an example of the structure of a semiconductor device according to a second embodiment of this invention.
  • FIG. 9A shows a high power source voltage (HV) ESD protection device that corresponds to first power source voltage and is extracted from a plurality of ESD protection devices provided on a semiconductor integrated circuit device
  • FIG. 9B shows a low power source voltage (LV) ESD protection device that corresponds to second power source voltage lower than the first power source voltage and is extracted from the ESD protection devices.
  • HV high power source voltage
  • LV low power source voltage
  • diffusion layer resistance regions (N ⁇ layers) 29 a , 29 b acting as ballast resistors and N ⁇ diffusion layers (eighth layers) 71 a , 71 b used for the formation of pMOSFETs (not shown) are respectively formed directly under silicide blocks 51 a , 51 b that constitute drain portions. That is, for example, as shown in FIG.
  • an HV ESD protection device 11 A′ is formed with the structure in which the N ⁇ diffusion layer 71 a for the channel region of the pMOSFET is formed as the diffusion layer directly below the silicide block 51 a and the diffusion layer resistance region 29 a that is formed at the same time as and in the same formation step as the LDD diffusion layers 26 a , 27 a by use of the same mask is superimposed on the above diffusion layer.
  • an LV ESD protection device 11 B′ is formed with the structure in which the N ⁇ diffusion layer 71 b for the channel region of the pMOSFET is formed as the diffusion layer directly below the silicide block 51 b and the diffusion layer resistance region 29 b that is formed at the same time as and in the same formation step as the LDD diffusion layers 26 a , 27 a and diffusion layer resistance region 29 a of the HV ESD protection device 11 A′ by use of the same mask is superimposed on the above diffusion layer.
  • the N ⁇ diffusion layers 71 a , 71 b are formed at the same time in the same formation step by use of the same mask when the channel regions of pMOSFETs (not shown) are formed.
  • the diffusion layer resistance region that is formed in a small area and has preset resistance without causing a junction leakage problem can be formed only by using the existing MOSFET formation process and the ESD discharging ability can be enhanced.
  • a deep junction can be attained directly below the silicide block without significantly lowering the diffusion layer resistance. Therefore, for example, the junction resistance of the diffusion layer can be further enhanced and a MOSFET ESD protection device having more preferable ESD protection ability can be realized.
  • this invention is not limited to the MOSFET ESD protection device with the LDD structure that corresponds to two types of HV and LV power source voltages.
  • this invention can be applied to a MOSFET ESD protection device with an LDD structure that corresponds to three or more types of power source voltages.
  • an LDD diffusion layer of the ESD protection device that corresponds to the highest power source voltage may be formed as a diffusion layer of a drain portion (directly under the silicide block) of another ESD protection device whose power source voltage is lower than that of the above ESD protection device.
  • any region whose junction is shallower than that of the second N+ diffusion layer 23 b and deeper than those of the LDD diffusion layers 26 b , 27 b can be used.

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Abstract

A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2007-333302, filed Dec. 25, 2007, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and more particularly to a metal oxide semiconductor field-effect transistor (MOSFET) electrostatic discharge (ESD) protection device for preventing a current such as electrostatic surge from flowing into a semiconductor integrated circuit device.
2. Description of the Related Art
Conventionally, semiconductor integrated circuit devices having ESD protection devices provided thereon have been developed. The ESD protection device is provided to prevent a current such as electrostatic surge from flowing into the semiconductor integrated circuit device. Some MOSFET ESD protection devices among the above ESD protection devices are designed to enhance the ESD discharging ability by forming silicide unformed portions (non-silicide regions) in drain regions and source regions (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2006-339444). That is, since a current is not concentrated in the silicide portion in a diffusion layer in the portion formed as the non-silicide region, the breakdown voltage of the device acting as the ESD protection device is enhanced.
In the ESD protection device, a diffusion layer with the same junction depth as that of a diffusion layer lying below the gate is formed in the non-silicide region in some cases. However, if this method is applied to a transistor for low power source voltage (or low voltage which is hereinafter referred to as LV) used as the ESD protection device, the junction depth of the diffusion layer is reduced and junction leakage may occur in the non-silicide region. In the above document, it is disclosed that the resistance of the non-silicide region is adjusted by using a diffusion layer with the same junction depth as that of a diffusion layer lying below the gate of the LV transistor in the non-silicide region of a transistor for high power source voltage (or high voltage which is hereinafter referred to as HV) used as the ESD protection device.
However, in the above document, it is not disclosed that a countermeasure against junction leakage is taken by forming a diffusion layer with the same junction depth as that of a diffusion layer lying below the gate of the HV transistor in the non-silicide region of the LV transistor.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor device which includes first and second metal oxide semiconductor field-effect transistors (MOSFETs) corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein, wherein the first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.
According to a second aspect of the present invention, there is provided a semiconductor device which includes a plurality of first metal oxide semiconductor field-effect transistors (MOSFETs) corresponding to first power source voltage, the plurality of first MOSFETs including non-silicide regions formed in drain portions thereof and having no silicide formed therein, first diffusion layers formed in source/drain portions, second diffusion layers formed below gate portions and formed shallower than the first diffusion layer and third diffusion layers formed with the same depth as the second diffusion layer in the non-silicide regions, and a plurality of second MOSFETs corresponding to second power source voltage lower than the first power source voltage, wherein the plurality of second MOSFETs include non-silicide regions formed in drain portions thereof and having no silicide formed therein, fourth diffusion layers formed in source/drain portions, fifth diffusion layers formed below gate portions and formed shallower than the fourth diffusion layer and sixth diffusion layers formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide regions.
According to a third aspect of the present invention, there is provided a semiconductor device which includes a plurality of metal oxide semiconductor field-effect transistors (MOSFETs) respectively corresponding to a plurality of power source voltages, and non-silicide regions formed in drain portions of the plurality of MOSFETs and having no silicide formed therein, wherein diffusion layer resistance regions with the same depth as that of LDD diffusion layers of that MOSFET which corresponds to highest power source voltage among the plurality of MOSFETs are formed in the non-silicide regions of the plurality of MOSFETs.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
FIGS. 1A and 1B are cross-sectional views showing an example of the structure of a semiconductor device (MOSFET ESD protection device) according to a first embodiment of this invention.
FIG. 2 is a diagram showing the relation between the concentrations of a P−− diffusion layer and a diffusion layer resistance region of the ESD protection device according to the first embodiment.
FIG. 3 is a cross-sectional view showing a manufacturing method of the ESD protection device according to the first embodiment.
FIG. 4 is a cross-sectional view showing a manufacturing method of the ESD protection device according to the first embodiment.
FIG. 5 is a cross-sectional view showing the manufacturing method of the ESD protection device according to the first embodiment.
FIG. 6 is a cross-sectional view showing the manufacturing method of the ESD protection device according to the first embodiment.
FIGS. 7A and 7B are cross-sectional views showing the manufacturing method of the ESD protection device according to the first embodiment.
FIGS. 8A and 8B are cross-sectional views showing the manufacturing method of the ESD protection device according to the first embodiment.
FIGS. 9A and 9B are cross-sectional views showing an example of the structure of a semiconductor device (MOSFET ESD protection device) according to a second embodiment of this invention.
 DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the drawings are schematic ones and so are not to scale. The following embodiments are directed to a device and a method for embodying the technical concept of the present invention and the technical concept does not specify the material, shape, structure or configuration of components of the present invention. Various changes and modifications can be made to the technical concept without departing from the scope of the claimed invention.
First Embodiment
FIGS. 1A and 1B show an example of the structure of a semiconductor device according to a first embodiment of this invention. In this embodiment, a case wherein this invention is applied to an ESD protection device having an nMOSFET structure is explained. FIG. 1A shows an ESD protection device used for high voltage (HV) corresponding to first power source voltage and extracted from a plurality of ESD protection devices provided on a semiconductor integrated circuit device and FIG. 1B shows an ESD protection device used for low voltage (LV) corresponding to second power source voltage lower than the first power source voltage and extracted from the ESD protection devices.
As shown in the cross-sectional view of FIG. 1A, a plurality of element isolation regions (shallow trench isolation [STI]) 12 a, 13 a, 14 a are formed on the surface portion of a P-well region (or a p-type semiconductor substrate formed of silicon, for example) 11 a of an HV ESD protection device 11A. A P+ region 21 a for a substrate contact is formed on that surface portion of the P-well region 11 a which corresponds to a portion between the element isolation regions 12 a and 13 a.
First to third N+ diffusion layers (first diffusion layers) 22 a, 23 a, 24 a with high concentration are selectively formed on those surface portions of the P-well region 11 a which correspond to a portion between the element isolation regions 13 a and 14 a. The first N+ diffusion layer 22 a forms a source region and the second and third diffusion layers 23 a and 24 a form drain regions. Silicide layers 31 a, 32 a, 33 a, 34 a are respectively formed on the surface portions of the P+ region 21 a and first to third N+ diffusion layers 22 a, 23 a, 24 a.
A gate electrode (polysilicon gate) 42 a is formed above that portion of the P-well region 11 a which corresponds to a portion between the first and second N+ diffusion layers 22 a and 23 a with a gate insulating film 41 a disposed therebetween. Gate sidewall insulating films 43 a are formed on the sidewall portions of the gate insulating film 41 a and gate electrode 42 a. A P−− diffusion layer 25 a acting as a channel region is formed on that surface portion of the P-well region 11 a which corresponds to a portion lying directly below the gate electrode 42 a (below the gate), that is, a portion between the first and second N+ diffusion layers 22 a and 23 a. A source-side lightly doped drain (LDD) diffusion layer (an N− layer acting as a second diffusion layer) 26 a used to form an extension region is formed in a position adjacent to the first N+ diffusion layer 22 a on the surface portion of the P−− diffusion layer 25 a. Further, a drain-side LDD diffusion layer (an N− layer acting as a second diffusion layer) 27 a used to form an extension region is formed in a position adjacent to the second N+ diffusion layer 23 a on the surface portion of the P−− diffusion layer 25 a. The impurity junctions of the LDD diffusion layers 26 a, 27 a are shallower than those of the first to third N+ diffusion layers 22 a, 23 a, 24 a and the depths thereof are controlled according to the first power source voltage.
A silicide block 51 a used to form a silicide unformed portion (non-silicide region) is formed above that portion of the P-well region 11 a which corresponds to a portion between the second and third N+ diffusion layers 23 a and 24 a. A P−− diffusion layer 28 a and a diffusion layer resistance region (an N− layer acting as a third diffusion layer) 29 a acting as a ballast resistor are formed directly under the silicide block 51 a, that is, on that surface portion of the P-well region 11 a which corresponds to the portion between the second and third N+ diffusion layers 23 a and 24 a. The P−− diffusion layer 28 a is formed with the same impurity concentration (distribution) and the same junction depth as those of the P−− diffusion layer 25 a. The diffusion layer resistance region 29 a is formed with the same impurity concentration and the same junction depth as those of the LDD diffusion layers 26 a, 27 a. That is, as the diffusion layer resistance region 29 a of the HV ESD protection device 11A, a region that is the same as the LDD diffusion layers 26 a, 27 a lying directly below the gate electrode 42 a or a region that is connected to the surrounding second and third N+ diffusion layers 23 a, 24 a having deep junctions and formed with sufficient depth to contain the silicide layers 33 a, 34 a without causing any problem associated with the junction leakage is used.
Symbols 52 a, 53 a, 54 a in the drawing denote contacts respectively connected to the silicide layers 31 a, 32 a, 34 a.
Further, as shown in the cross-sectional view of FIG. 1B, a plurality of element isolation regions (STI) 12 b, 13 b, 14 b are formed on the surface portion of a P-well region (or a p-type semiconductor substrate formed of silicon, for example) 11 b of an LV ESD protection device 11B. A P+ region 21 b for a substrate contact is formed on that surface portion of the P-well region 11 b which corresponds to a portion between the element isolation regions 12 b and 13 b.
First to third N+ diffusion layers (fourth diffusion layers) 22 b, 23 b, 24 b with high concentration are selectively formed on that surface portion of the P-well region 11 b which corresponds to a portion between the element isolation regions 13 b and 14 b. The first N+ diffusion layer 22 b forms a source region and the second and third diffusion layers 23 b, 24 b form drain regions. Silicide layers 31 b, 32 b, 33 b, 34 b are respectively formed on the surface portions of the P+ region 21 b and first to third N+ diffusion layers 22 b, 23 b, 24 b.
A gate electrode (polysilicon gate) 42 b is formed above that portion of the P-well region 11 b which corresponds to a portion between the first and second N+ diffusion layers 22 b and 23 b with a gate insulating film 41 b disposed therebetween. On the sidewall portions of the gate insulating film 41 b and gate electrode 42 b, gate sidewall insulating films 43 b are formed. A P−− diffusion layer 25 b acting as a channel region is formed directly below the gate electrode 42 b (below the gate), that is, on that surface portion of the P-well region 11 b which corresponds to a portion between the first and second N+ diffusion layers 22 b and 23 b. A source-side lightly doped drain (LDD) diffusion layer (an N− layer acting as a fifth diffusion layer) 26 b used to form an extension region is formed in a position adjacent to the first N+ diffusion layer 22 b on the surface portion of the P−− diffusion layer 25 b. A drain-side LDD diffusion layer (an N− layer acting as a fifth diffusion layer) 27 b used to form an extension region is formed in a position adjacent to the second N+ diffusion layer 23 b on the surface portion of the P−− diffusion layer 25 b. The impurity junctions of the LDD diffusion layers 26 b, 27 b are shallower than those of the LDD diffusion layers 26 a, 27 a and the depths thereof are controlled according to the second power source voltage.
A silicide block 51 b used to form a non-silicide region is formed on that portion of the P-well region 11 b which corresponds to a portion between the second and third N+ diffusion layers 23 b and 24 b. A P−− diffusion layer (seventh diffusion layer) 28 b and a diffusion layer resistance region (an N− layer acting as a sixth diffusion layer) 29 b acting as a ballast resistor are formed directly under the silicide block 51 b, that is, on that surface portion of the P-well region 11 b which corresponds to a portion between the second and third N+ diffusion layers 23 b and 24 b. The P−− diffusion layer 28 b is formed with the same impurity concentration and the same junction depth as the P−− diffusion layer 25 b. The diffusion layer resistance region 29 b is formed with the same impurity concentration and the same junction depth as the diffusion layer resistance region 29 a. That is, as the diffusion layer resistance region 29 b of the LV ESD protection device 11B, a region that is different from the LDD diffusion layers 26 b, 27 b lying directly below the gate electrode 42 b and is the same as the LDD diffusion layers 26 a, 27 a lying directly below the gate electrode 42 a of the HV ESD protection device 11A is used. The diffusion layer resistance region 29 b is formed at the same time as and in the same formation process as the LDD diffusion layers 26 a, 27 a and diffusion layer resistance region 29 a by use of the same mask. As a result, the diffusion layer resistance region 29 b that is formed in a small area and does not cause junction leakage can be easily realized only by using an existing MOSFET formation process (normal transistor formation process).
Symbols 52 b, 53 b, 54 b in the drawing denote contacts respectively connected to the silicide layers 31 b, 32 b, 34 b.
FIG. 2 shows the relation between the concentrations of the P−− diffusion layer and the diffusion layer resistance region. When the LDD structure (HV LDD) of the HV ESD protection device 11A is used as the ballast resistor of the LV ESD protection device 11B, it is rather preferable than in a case wherein the LDD structure (LV LDD) of the LV ESD protection device 11B is used. As is clearly understood from the drawing, this is because the junction leakage in the non-silicide region of the LV ESD protection device 11B can be reduced by using a gentle and deep junction, for example, between the P−− diffusion layer 25 a and the LDD diffusion layers 26 a, 27 a of the HV ESD protection device 11A. Thus, the ESD discharging ability can be enhanced by forming the ballast resistor of the HV LDD structure that is formed of the diffusion layer resistance region 29 b in the non-silicide region of the LV ESD protection device 11B.
The junction depth of the diffusion layer below the gate of the transistor is set to approximately ¼ the gate length in order to suppress the short channel effect. For example, if it is supposed that the gate length of an HV transistor of an input/output portion is set to approximately 400 nm with the transistor technique in which the gate length of an LV transistor is set in a 90 nm-generation, the junction depth of a diffusion layer below the gate of the LV transistor is set to 20 to 25 nm and the junction depth of a diffusion layer below the gate of the HV transistor is set to approximately 100 nm.
Next, a manufacturing method of the ESD protection device (FIGS. 11A, 11B) with the nMOSFET structure described above is simply explained with reference to FIG. 3 to FIGS. 8A and 8B.
First, for example, as shown in FIG. 3, a plurality of element isolation regions 12 a, 13 a, 14 a and 12 b, 13 b, 14 b are formed on the surface portions of P- well regions 11 a, 11 b by use of an existing MOSFET formation process. Then, P+ regions 21 a, 21 b for substrate contacts and P−− diffusion layers 25 a, 25 b are respectively formed on the surface portions of the P- well regions 11 a, 11 b. After this, gate insulating films 41 a, 41 b and gate electrodes 42 a, 42 b are formed on the P- well regions 11 a, 11 b. A reference symbol 61 in the drawing denotes a mask used at the ion-implantation time in a simplified form.
Next, for example, as shown in FIG. 4, LDD diffusion layers 26 b, 27 b are formed in self-alignment with the gate electrode 42 b in the LV ESD protection device 11B.
Then, for example, as shown in FIG. 5, LDD diffusion layers 26 a, 27 a are formed in self-alignment with the gate electrode 42 a in the HV ESD protection device 11A.
At this time, for example, as shown in FIG. 6, a diffusion layer resistance region 29 b having the same junction depth as the LDD diffusion layers 26 a, 27 a of the HV ESD protection device 11A is formed in an area in which a silicide block 51 b is to be formed in the LV ESD protection device 11B by using the mask 61 having an opening with the width determined by taking the mask misalignment and spread of the diffusion layer into consideration.
Next, for example, as shown in FIGS. 7A and 7B, gate sidewall insulating films 43 a and silicide block 51 a of the HV ESD protection device 11A are formed and, at the same time, gate sidewall insulating films 43 b and silicide block 51 b of the LV ESD protection device 11B are formed by using the existing MOSFET formation process.
Next, for example, as shown in FIGS. 8A and 8B, deep N+ diffusion layers 22 a, 23 a, 24 a with high concentration are formed in the source/drain regions of the HV ESD protection device 11A and, at the same time, deep N+ diffusion layers 22 b, 23 b, 24 b with high concentration are formed in the source/drain regions of the LV ESD protection device 11B by using the existing MOSFET formation process.
At this time, deep diffusion layers with high concentration are prevented from being formed in portions directly under the silicide blocks due to the presence of the silicide blocks 51 a, 51 b.
After this, silicide layers 31 a, 32 a, 33 a, 34 a and 31 b, 32 b, 33 b, 34 b and contacts 52 a, 53 a, 54 a and 52 b, 53 b, 54 b are formed to complete the HV ESD protection device 11A and LV ESD protection device 11B with the structures shown in FIGS. 1A and 1B.
As described above, the LDD structure (HV LDD) of the HV ESD protection device 11A is used in the drain portion (non-silicide region) of the LV ESD protection device 11B. That is, the diffusion layer resistance region 29 b having the same junction depth as the LDD diffusion layers 26 a, 27 a of the HV ESD protection device 11A is formed directly under the silicide block 51 b of the LV ESD protection device 11B. Thus, the LV ESD protection device 11B can be formed with the structure of a small area without causing a junction leakage problem. Therefore, a MOSFET ESD protection device that corresponds to low power source voltage and enhances the ESD discharging ability without providing an additional step to the existing MOSFET formation process can be realized.
Second Embodiment
FIGS. 9A and 9B show an example of the structure of a semiconductor device according to a second embodiment of this invention. In the present embodiment, a case wherein this invention is applied to an ESD protection device having an nMOSFET structure is explained. In this case, FIG. 9A shows a high power source voltage (HV) ESD protection device that corresponds to first power source voltage and is extracted from a plurality of ESD protection devices provided on a semiconductor integrated circuit device and FIG. 9B shows a low power source voltage (LV) ESD protection device that corresponds to second power source voltage lower than the first power source voltage and is extracted from the ESD protection devices. In this example, portions that are the same as those of the first embodiment (see FIGS. 1A and 1B) are denoted by the same reference symbols and detailed explanation thereof is omitted.
In the case of this embodiment, diffusion layer resistance regions (N− layers) 29 a, 29 b acting as ballast resistors and N−− diffusion layers (eighth layers) 71 a, 71 b used for the formation of pMOSFETs (not shown) are respectively formed directly under silicide blocks 51 a, 51 b that constitute drain portions. That is, for example, as shown in FIG. 9A, an HV ESD protection device 11A′ is formed with the structure in which the N−− diffusion layer 71 a for the channel region of the pMOSFET is formed as the diffusion layer directly below the silicide block 51 a and the diffusion layer resistance region 29 a that is formed at the same time as and in the same formation step as the LDD diffusion layers 26 a, 27 a by use of the same mask is superimposed on the above diffusion layer.
Further, for example, as shown in FIG. 9B, an LV ESD protection device 11B′ is formed with the structure in which the N−− diffusion layer 71 b for the channel region of the pMOSFET is formed as the diffusion layer directly below the silicide block 51 b and the diffusion layer resistance region 29 b that is formed at the same time as and in the same formation step as the LDD diffusion layers 26 a, 27 a and diffusion layer resistance region 29 a of the HV ESD protection device 11A′ by use of the same mask is superimposed on the above diffusion layer.
The N−− diffusion layers 71 a, 71 b are formed at the same time in the same formation step by use of the same mask when the channel regions of pMOSFETs (not shown) are formed.
Thus, according to the present embodiment, the diffusion layer resistance region that is formed in a small area and has preset resistance without causing a junction leakage problem can be formed only by using the existing MOSFET formation process and the ESD discharging ability can be enhanced.
Particularly, with the structure as shown in the second embodiment, a deep junction can be attained directly below the silicide block without significantly lowering the diffusion layer resistance. Therefore, for example, the junction resistance of the diffusion layer can be further enhanced and a MOSFET ESD protection device having more preferable ESD protection ability can be realized.
In each of the above embodiments, a case wherein this invention is applied to the ESD protection device with the nMOSFET structure is explained as an example, but this invention is not limited to this case. For example, this invention can be similarly applied to an ESD protection device with a pMOSFET structure.
Further, this invention is not limited to the MOSFET ESD protection device with the LDD structure that corresponds to two types of HV and LV power source voltages. For example, this invention can be applied to a MOSFET ESD protection device with an LDD structure that corresponds to three or more types of power source voltages. In this case, an LDD diffusion layer of the ESD protection device that corresponds to the highest power source voltage may be formed as a diffusion layer of a drain portion (directly under the silicide block) of another ESD protection device whose power source voltage is lower than that of the above ESD protection device.
Further, as the diffusion layer resistance region 29 b formed directly under the silicide block 51 b, any region whose junction is shallower than that of the second N+ diffusion layer 23 b and deeper than those of the LDD diffusion layers 26 b, 27 b can be used.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims (16)

1. A semiconductor device comprising:
first and second metal oxide semiconductor field-effect transistors (MOSFETs) corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and
non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein,
wherein the first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.
2. The semiconductor device according to claim 1, wherein the fourth diffusion layer has the same depth as the first diffusion layer and the fifth diffusion layer is shallower than the second diffusion layer.
3. The semiconductor device according to claim 1, wherein the sixth diffusion layer has the same depth as the second and third diffusion layers.
4. The semiconductor device according to claim 1, further comprising a seventh diffusion layer whose conductivity type is different from that of the sixth diffusion layer and which is formed in the non-silicide region of the second MOSFET.
5. The semiconductor device according to claim 4, wherein the seventh diffusion layer is deeper than the sixth diffusion layer.
6. The semiconductor device according to claim 1, further comprising an eighth diffusion layer whose conductivity type is the same as that of the sixth diffusion layer and which is used to form a MOSFET having a different conductivity type and formed in the non-silicide region of the second MOSFET.
7. The semiconductor device according to claim 6, wherein the eighth diffusion layer is deeper than the sixth diffusion layer.
8. The semiconductor device according to claim 1, wherein the third and sixth diffusion layers function as ballast resistors.
9. A semiconductor device comprising:
a plurality of first metal oxide semiconductor field-effect transistors (MOSFETs) corresponding to first power source voltage, the plurality of first MOSFETs including non-silicide regions formed in drain portions thereof and having no silicide formed therein, first diffusion layers formed in source/drain portions, second diffusion layers formed below gate portions and formed shallower than the first diffusion layer and third diffusion layers formed with the same depth as the second diffusion layer in the non-silicide regions, and
a plurality of second MOSFETs corresponding to second power source voltage lower than the first power source voltage,
wherein the plurality of second MOSFETs include non-silicide regions formed in drain portions thereof and having no silicide formed therein, fourth diffusion layers formed in source/drain portions, fifth diffusion layers formed below gate portions and formed shallower than the fourth diffusion layer and sixth diffusion layers formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide regions.
10. The semiconductor device according to claim 9, wherein the fourth diffusion layer has the same depth as the first diffusion layer and the fifth diffusion layer is shallower than the second diffusion layer.
11. The semiconductor device according to claim 9, wherein the sixth diffusion layer has the same depth as the second and third diffusion layers.
12. The semiconductor device according to claim 9, further comprising seventh diffusion layers whose conductivity type is different from that of the sixth diffusion layer and which are formed in the non-silicide regions of the plurality of second MOSFETs.
13. The semiconductor device according to claim 12, wherein the seventh diffusion layer is deeper than the sixth diffusion layer.
14. The semiconductor device according to claim 9, further comprising eighth diffusion layers whose conductivity type is the same as that of the sixth diffusion layer and which are used to form MOSFETs having different conductivity types and formed in the non-silicide regions of the plurality of second MOSFETs.
15. The semiconductor device according to claim 14, wherein the eighth diffusion layer is deeper than the sixth diffusion layer.
16. The semiconductor device according to claim 9, wherein the third and sixth diffusion layers function as ballast resistors.
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