+

US7972967B1 - Method of forming patterns of a semiconductor device including forming spacers on sidewalls of auxiliary patterns and removing exposed auxiliary patterns - Google Patents

Method of forming patterns of a semiconductor device including forming spacers on sidewalls of auxiliary patterns and removing exposed auxiliary patterns Download PDF

Info

Publication number
US7972967B1
US7972967B1 US12/914,985 US91498510A US7972967B1 US 7972967 B1 US7972967 B1 US 7972967B1 US 91498510 A US91498510 A US 91498510A US 7972967 B1 US7972967 B1 US 7972967B1
Authority
US
United States
Prior art keywords
layer
pattern
patterns
passivation
auxiliary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US12/914,985
Inventor
Chan Sun Hyun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HYUN, CHAN SUN
Application granted granted Critical
Publication of US7972967B1 publication Critical patent/US7972967B1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7023—Aligning or positioning in direction perpendicular to substrate surface
    • G03F9/703—Gap setting, e.g. in proximity printer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region

Definitions

  • An exemplary embodiment relates to a method of forming patterns of a semiconductor device and, more particularly, to a method of forming the patterns of a semiconductor device to improve the uniformity of a gap between patterns with different widths when forming the patterns in the same layer.
  • Patterns of a semiconductor device can have a variety of sizes.
  • a NAND flash memory device is described as an example.
  • a plurality of strings is formed in a memory cell array region of the NAND flash memory device.
  • Each of the strings includes a source select transistor, a drain select transistor, and a plurality of memory cells coupled in series between the source select transistor and the drain select transistor.
  • the gate of the source select transistor is coupled to the source select line
  • the gate of the drain select transistor is coupled to the drain select line
  • the gates of the memory cells are coupled to word lines.
  • each of the drain select line and the source select line can be wider than the word line.
  • the word line can have a fine line width that is narrower than the exposure resolution limit, due to the degree of integration of such devices.
  • the SPT method includes processes of forming first auxiliary patterns for providing prominence and depression shapes so that spacers can be formed, depositing a spacer layer on the surface of the entire structure including the first auxiliary patterns, forming the spacers on the sidewalls of the first auxiliary patterns by etching the spacer layer using an etch method, such as etch-back, so that the spacer layer remains on the sidewalls of the first auxiliary patterns, removing the first auxiliary patterns, and etching an underlying layer using the remaining spacers as an etch mask.
  • etch method such as etch-back
  • patterns having a fine line width can be formed by controlling the thickness of the spacer layer.
  • a process of forming second auxiliary patterns each having a line width wider than that of the spacer must be further performed after forming the first auxiliary patterns.
  • the second auxiliary patterns, together with the spacer, function as an etch mask in a process of etching the underlying layer, and they are used to form patterns each having a line width wider than the spacer.
  • FIG. 1 is a diagram showing an alignment relationship between spacers and auxiliary patterns used to form patterns with different line widths.
  • spacers 53 each defining the width of each of fine patterns narrower than the exposure resolution limit, are formed on sidewalls of first auxiliary patterns 51 .
  • a gap D 1 between the spacers 53 is defined by the first auxiliary patterns 51 .
  • a second auxiliary pattern 55 is formed over a region in which patterns, each having a width wider than a width defined by the spacer 53 , will be formed.
  • a gap D 2 between a pattern defined by the second auxiliary pattern 55 and the pattern defined by the spacer 53 is determined according to the alignment of the second auxiliary patterns 55 .
  • the gap D 2 between the finer pattern and the pattern that is wider than the exposure resolution is wider than the gap D 1 between the fine patterns defined by the spacers because of the alignment margin of the second auxiliary patterns 55 .
  • a loading effect in which there is a difference in the degree of etching according to a difference in the density of patterns occurs, which can lead to damage to some regions of the semiconductor device. Problems occurring because of the loading effect are described in more detail below with reference to FIG. 2 .
  • FIG. 2 is a cross-sectional view showing part of a NAND flash memory device formed using a conventional method of forming patterns of a semiconductor device.
  • a gate pattern including word lines WL and a select line DSL/SSL, is patterned using hard mask patterns 21 as an etch mask.
  • the select line DSL/SSL can include a drain select line DSL or a source select line SSL.
  • a hard mask pattern 21 for patterning the word line WL can have a line width defined by the above-described spacer and have a line width finer than the exposure resolution. Further, a hard mask pattern 21 for patterning the select line DSL/SSL can have its line width defined by the second auxiliary pattern and have a wider line width than that of the hard mask pattern 21 for patterning the word lines WL. However, a second gap D 2 between the select line DSL/SSL and a neighboring word line WL can be wider than a first gap D 1 between neighboring word lines WL according to the alignment of the second auxiliary patterns. Thus, in the etch process of forming the gate pattern, layers exposed between the select line DSL/SSL and the neighboring word line WL can be etched faster than layers exposed between the word lines WL, because of a loading effect.
  • the patterning process of forming the gate pattern is performed after stacking an isolation layer (not shown), a dielectric layer 17 , and a second conductive layer 19 over the first conductive layer 15 , separated from each other with the isolation layer interposed therebetween, and forming the hard mask pattern 21 over the second conductive layer 19 .
  • the first conductive layer 15 formed on a gate insulating layer 13 over a semiconductor substrate 11 can be separated with the isolation region interposed therebetween.
  • the above process can be performed by stacking the gate insulating layer 13 and the first conductive layer 15 over the semiconductor substrate 11 , forming an isolation mask pattern on the first conductive layer 15 , forming trenches (not shown) by etching the first conductive layer 15 , the gate insulating layer 13 , and the isolation regions of the semiconductor substrate 11 using the isolation mask pattern as an etch mask, and then filling the trenches with the isolation layer.
  • the height of the isolation layer preferably is lower than a top surface of the first conductive layer 15 to increase the area in which the first conductive layer 15 and the second conductive layer 19 face each other and increase the coupling ratio of the gate patterns and preferably higher than a top surface of the gate insulating layer 13 to protect the gate insulating layer 13 .
  • the dielectric layer 17 is formed on not only the top surfaces of the isolation layer and the first conductive layer 15 , but also on the exposed sidewalls of the first conductive layer 15 because of a difference in the height between the first conductive layer 15 and the isolation layer.
  • the thickness of the dielectric layer 17 preferably is controlled so that it does not fill the space between the first conductive layers 15 .
  • a contact hole through which the first conductive layer 15 is exposed is formed in the dielectric layer 17 .
  • the second conductive layer 19 is formed over the dielectric layer 17 having the contact hole formed therein.
  • the first conductive layer 15 , the dielectric layer 17 , and the second conductive layer 19 formed by the above process are etched by an etch process using the hard mask pattern 21 as an etch mask.
  • the second conductive layer 19 , the dielectric layer 17 , and the first conductive layer 15 are removed in the portion not blocked by the hard mask pattern 21 .
  • the second conductive layer 19 , the dielectric layer 17 , and the first conductive layer 15 can be etched faster in the portion opened in the second width D 2 , having a relatively wide width with respect to the first width D 1 , than in the portion opened in the first width D 1 . Consequently, the gate insulating layer 13 that must remain intact under the second conductive layer 19 can be damaged.
  • the dielectric layer 17 can remain on the sidewalls of the first conductive layer 15 , which can cause a bridge between neighboring strings and the loss of charges. Furthermore, the isolation layer is irregularly lost because of a loading effect, leading to cycling deterioration.
  • An exemplary embodiment relates to a method of forming the patterns of a semiconductor device, which is capable of improving the uniformity of a gap between patterns having different widths when forming the patterns in the same layer.
  • a method of forming the patterns of a semiconductor device comprises forming an auxiliary layer over an underlying layer comprising a cell region and a select transistor region, forming a first passivation layer over the auxiliary layer, where in the first passivation layer blocks the auxiliary layer of the select transistor region and opens the auxiliary layer of the cell region, and forming (a) a first photoresist pattern having a narrower width than the first passivation layer over the first passivation layer and (b) second photoresist patterns, each second photoresist pattern having a narrower width than the first photoresist pattern, over an opening region of the auxiliary layer, to define a gap between the first and second photoresist patterns and a gap between the second photoresist patterns, wherein the gap between the first and second photoresist patterns is identical in width with the gap defined between the second photoresist patterns.
  • the method preferably further comprises, after forming the first and second photoresist patterns, removing an exposed region of the first passivation layer, removing exposed regions of the auxiliary layer to form auxiliary patterns, removing the first and second photoresist patterns to expose the first passivation layer and the auxiliary patterns that do not overlap with the first passivation layer, forming spacers on sidewalls of the auxiliary patterns, and removing the exposed auxiliary patterns.
  • the method preferably further comprises forming a hard mask layer over the underlying layer before forming the auxiliary layer, forming hard mask patterns by removing an exposed region of the hard mask layer using the spacers and the auxiliary patterns remaining under the first passivation layer as an etch mask, and forming target patterns by etching an exposed region of the underlying layer using the hard mask pattern as an etch mask after removing the exposed auxiliary patterns.
  • the first passivation layer preferably is formed over the auxiliary layer of the select transistor region by removing the first passivation layer over the cell region after forming the first passivation layer over the entire surface of the auxiliary layer.
  • the first passivation layer over the cell region preferably is removed by forming a photoresist pattern on the first passivation layer over the select transistor region, etching an exposed region of the first passivation layer to a desired thickness, removing the photoresist pattern, and then etching the first passivation layer using a blanket etch process until the auxiliary layer is exposed.
  • the method preferably further comprises forming a second passivation layer over the auxiliary layer before forming the first and second photoresist patterns.
  • the target patterns preferably comprise a first target pattern having a width defined by the sum of a width of the auxiliary pattern under the first passivation layer and a width of the spacer formed on the sidewall of the auxiliary pattern, and second target patterns, each having a width defined by the width of the spacer.
  • the first target pattern preferably includes a drain select line or a source select line of a NAND flash memory device.
  • the second target patterns preferably include the word lines of the NAND flash memory device.
  • a method of forming the patterns of a semiconductor device comprises stacking a hard mask layer and an auxiliary layer over an underlying layer, forming a passivation pattern covering only a portion of the auxiliary layer, forming etch mask patterns over portions of the passivation pattern and the auxiliary layer not covered by the passivation pattern, removing exposed regions of the passivation pattern and the auxiliary layer not covered by the etch mask patterns, removing the etch mask patterns to expose the passivation pattern and the auxiliary layer not covered by the passivation pattern, forming spacers on sidewalls of the remaining auxiliary layer, removing an exposed portion of the auxiliary layer not covered by the passivation pattern, forming hard mask patterns by removing an exposed region of the hard mask layer using the spacers and the remaining auxiliary layer overlapped with the passivation pattern as an etch mask; and forming a plurality of target patterns by etching an exposed region of the underlying layer using the hard mask patterns as an etch mask.
  • the passivation pattern preferably is formed by forming a first passivation layer over the auxiliary layer, forming a photoresist pattern over the first passivation layer, lowering a height of the first passivation layer in an exposed region of the first passivation layer by etching the exposed region of the first passivation layer using the photoresist pattern as an etch mask, removing the photoresist pattern, and then etching the first passivation layer using a blanket etch process until the auxiliary layer is exposed.
  • the etch mask pattern preferably comprises a first photoresist pattern formed over the passivation pattern and having a narrower width than the width of the passivation pattern, and second photoresist patterns not overlapped with the passivation pattern, formed over the auxiliary layer, and each configured to have a narrower width than the width of the first photoresist pattern.
  • the method preferably further comprises forming a second passivation layer over the auxiliary layer, including the passivation pattern, before forming the etch mask pattern.
  • the second passivation layer exposed between the etch mask patterns preferably is removed.
  • the remaining second passivation layer preferably is removed after removing the etch mask pattern.
  • the auxiliary layer preferably comprises a Spin-On Carbon (SOC) layer.
  • SOC Spin-On Carbon
  • the first passivation layer preferably is deposited at a temperature in a range of 40° C. to 90° C. Further, the first passivation layer preferably comprises a Spin-On Carbon (SOC) layer, an amorphous carbon layer, or an oxide layer.
  • SOC Spin-On Carbon
  • the second passivation layer preferably comprises SiC, polysilicon, or SiON.
  • FIG. 1 is a diagram showing an alignment relationship between spacers and auxiliary patterns used to form patterns with different line widths
  • FIG. 2 is a cross-sectional view showing part of a NAND flash memory device formed using a conventional method of forming patterns of a semiconductor device
  • FIGS. 3A to 3I are cross-sectional views illustrating a method of forming the patterns of a semiconductor device according to an exemplary embodiment of this disclosure.
  • FIGS. 3A to 3I are cross-sectional views illustrating a method of forming the patterns of a semiconductor device according to an exemplary embodiment of this disclosure.
  • a hard mask layer 117 and an auxiliary layer 121 are stacked over an underlying layer for forming patterns.
  • the underlying layer can be a semiconductor substrate 101 in itself or can be a layer including at least one of a conductive layer and an insulating layer formed over the semiconductor substrate 101 .
  • the underlying layer can be a gate insulating layer 103 , a first conductive layer 105 , a dielectric layer 109 , and a second conductive layer 111 , which are stacked over the semiconductor substrate 101 .
  • a contact hole through which the first conductive layer 105 is exposed is formed in the dielectric layer 109 , and the first conductive layer 105 and the second conductive layer 111 thus can be electrically coupled through the contact hole.
  • the contact hole is disposed in a region where a source select line and a drain select line will be formed.
  • the first conductive layer 105 and the second conductive layer 111 preferably are made of polysilicon, and the dielectric layer 109 preferably is formed by stacking an oxide layer, a nitride layer, and an oxide layer.
  • the hard mask layer 117 serves as an etch mask when subsequently etching the underlying layer.
  • the hard mask layer 117 can be formed of a single layer or a plurality of stack layers according to the etch selectivity for the underlying layer.
  • the hard mask layer 117 can have a stack structure of an oxide layer 113 , being capable of serving as an etch mask when etching the second conductive layer 111 made of polysilicon in a subsequent process, and a polysilicon layer 115 capable of protecting the oxide layer 113 when etching the auxiliary layer 121 in a subsequent process.
  • the auxiliary layer 121 preferably is made of a material selected with consideration taken of the etch selectivity for a spacer layer formed in a subsequent process.
  • the auxiliary layer 121 can be formed of a Spin-On Carbon (SOC) layer.
  • a first passivation layer 123 is formed over the auxiliary layer 121 .
  • the first passivation layer 123 preferably is made of a material selected by taking the etch selectivity for the auxiliary layer 121 into consideration.
  • the first passivation layer 123 preferably is formed of a layer deposited at a temperature in a range of 40° C. to 90° C. At 40 to 90° C., an oxide layer such as an Ultra Low Temperature Oxide (ULTO) layer, a Spin On Carbon (SOC) layer, or an Amorphous Carbon Layer (ACL) can be formed.
  • the first passivation layer 123 preferably is formed in thickness of 100 ⁇ to 500 ⁇ .
  • a photoresist pattern 125 (i.e., an etch mask pattern) is formed over the first passivation layer 123 .
  • the photoresist pattern 125 is formed as a pattern for blocking the first passivation layer 123 over a region in which a first target pattern having a relatively wide width (e.g., a select transistor region where a source select line or a drain select line will be formed) and for exposing the first passivation layer 123 over a region in which a second target pattern having a narrower width than the first target pattern will be formed (e.g., a cell region where word lines will be formed).
  • a first target pattern having a relatively wide width e.g., a select transistor region where a source select line or a drain select line will be formed
  • a second target pattern having a narrower width than the first target pattern e.g., a cell region where word lines will be formed.
  • the exposed region of the first passivation layer 123 is etched using the photoresist pattern 125 as an etch mask.
  • the first passivation layer 123 can be etched to a desired thickness so that the auxiliary layer 121 is not exposed.
  • the first passivation layer 123 becomes thinner in the region not blocked by the photoresist pattern 125 than in the region blocked by the photoresist pattern 125 .
  • the photoresist pattern 125 is removed, preferably using a strip process.
  • the first passivation layer 123 over the regions in which the first and second target patterns will be formed is exposed.
  • the auxiliary layer 121 over the region in which the second target pattern will be formed is exposed by etching the first passivation layer 123 exposed over the regions in which the first and second target patterns will be formed using an etch process, such as by a blanket etch process.
  • the first passivation layer 123 over the region in which the first target pattern will be formed remains intact as a passivation pattern 123 a having a first width W 1 , as shown in FIG. 3E , so that the auxiliary layer 121 over the region where the first target pattern will be formed is blocked.
  • the first passivation layer 123 can remain as the passivation pattern 123 a having the first width W 1 over the region in which the first target pattern will be formed, as described above, because the first passivation layer 123 is thicker over the region in which the first target pattern will be formed than over the region in which the second target pattern will be formed. Meanwhile, the first width W 1 preferably is wider than the width of a first photoresist pattern which will be formed over the passivation pattern 123 a in a subsequent process. This of guarantees the alignment margin when forming the first photoresist pattern in the subsequent process.
  • the auxiliary layer 121 over the region in which the first target pattern will be formed will be fully blocked by the passivation pattern 123 a and a spacer to be formed in a subsequent process. Accordingly, when subsequently removing the auxiliary layer 121 exposed over the region in which the second target pattern will be formed, the auxiliary layer 121 over the region in which the first target pattern will be formed can be protected by the passivation pattern 123 a and the spacer, and so it can remain intact.
  • an etch mask pattern 129 is formed over the auxiliary layer 121 including the passivation pattern 123 a having the first width W 1 .
  • a second passivation layer 127 can be formed over the auxiliary layer 121 including the passivation pattern 123 a having the first width W 1 .
  • the second passivation layer 127 preferably is formed of a Multi-Function Hard Mask (MFHM) layer.
  • the second passivation layer 127 prevents the auxiliary layer 121 from being removed when removing the etch mask pattern 129 (i.e., photoresist materials) such as by using a strip process in a subsequent process.
  • the auxiliary layer 121 preferably comprises carbon-rich SiC, polysilicon, or SiON.
  • the etch mask pattern 129 includes a first photoresist pattern 129 a and a second photoresist pattern 129 b .
  • the first photoresist pattern 129 a has a second width W 2 narrower than the first width W 1 of the passivation pattern 123 a and overlapping the passivation pattern 123 a thereon.
  • the second photoresist pattern 129 b has a third width W 3 narrower than the second width W 2 and overlapping the auxiliary layer 121 not protected by the passivation pattern 123 a having the first width W 1 .
  • a gap between the first photoresist pattern 129 a and the second photoresist pattern 129 b , which are adjacent to each other, preferably has a first gap L 1 , which is identical with a gap between the second photoresist patterns 129 b adjacent to each other.
  • the gap L 1 between them can be uniformly formed. Further, since the second width W 2 of the first photoresist pattern 129 a is narrower than the first width W 1 of the passivation pattern 123 a , the second width W 2 can easily overlap with the first width W 1 thereon.
  • a passivation pattern 123 b having the second width W 2 and a plurality of auxiliary patterns 121 a protected or not protected by the passivation pattern 123 b having the second width W 2 are formed over the hard mask layer 117 .
  • a portion protected by the passivation pattern 123 b having the second width W 2 from among the auxiliary patterns 121 a , has the second width W 2 , and portions not protected by the passivation pattern 123 b having the second width W 2 have a third width W 3 .
  • a gap between the passivation pattern 123 b having the second width W 2 and the auxiliary pattern 121 a having the third width W 3 and a gap between the neighboring auxiliary patterns 121 a each having the third width W 3 are defined by etch mask patterns and so they can be formed to have the first gap L 1 identically.
  • the etch mask patterns are removed such as by using a strip process.
  • the remaining second passivation layer 127 can be removed.
  • spacers 131 are formed on the sidewalls of the auxiliary patterns 121 a .
  • the spacers 131 preferably are formed by forming a spacer layer on a surface of the hard mask layer 117 , including the auxiliary patterns 121 a and the passivation pattern 123 b having the second width W 2 , and then etching the spacer layer using an etch process, such as an etch-back process, to expose the auxiliary patterns 121 a and the passivation pattern 123 b having the second width W 2 .
  • the thickness of the spacer layer preferably is controlled so that the spacer layer does not fill the space between the auxiliary patterns 121 a .
  • the spacer layer preferably comprises an oxide layer.
  • the auxiliary pattern 121 a under the passivation pattern 123 b having the second width W 2 is protected by the passivation pattern 123 b having the second width W 2 and thus is not exposed. Furthermore, the passivation pattern 123 b having the second width W 2 can be partially removed such as by using an etch-back process for forming a spacer so that it remains, preferably with a thickness of 50 ⁇ to 400 ⁇ .
  • a second gap L 2 between the spacers 131 formed between the auxiliary patterns 121 a can become the same as the third width W 3 by controlling the thickness of the spacer layer.
  • the exposed region of the hard mask layer 117 is removed using the remaining spacers and the remaining auxiliary pattern having the second width W 2 under the passivation pattern, having the second width W 2 , as an etch mask. Accordingly, hard mask patterns 117 a with different line widths are formed.
  • the width of each of the regions opened by removing the auxiliary patterns, each having the third width W 3 is identical with the width of the region opened between the spacers, the width of each of the regions not blocked by the hard mask patterns 117 a can also be identically formed.
  • the hard mask pattern 117 a preferably has a stack structure of a polysilicon layer pattern 115 a , formed by etching a polysilicon layer, and an oxide layer pattern 113 a formed by etching an oxide layer not blocked by the polysilicon layer pattern 115 a .
  • the remaining spacers, the remaining passivation pattern having the second width, and the remaining auxiliary patterns can be removed.
  • the etch process of forming the spacers, the process of removing the auxiliary patterns each having the third width, and the etch process of forming the hard mask pattern 117 a preferably are performed in-situ. Accordingly, a process of manufacturing semiconductor devices can be simplified.
  • first target pattern DSL/SSL and the second target patterns WL each narrower than the first target pattern DSL/SSL are formed at the same time.
  • a width of the first target pattern DSL/SSL is defined by the sum of the second width and a width of the spacer formed on the sidewall of the passivation pattern having the second width.
  • a width of the second target pattern WL is defined by a width of the spacer.
  • the underlying layer removed by an etch process using hard mask patterns as an etch mask can include a second conductive layer 111 , a dielectric layer 109 , and a first conductive layer 105 .
  • the first target pattern can include a drain select line DSL or a source select line SSL
  • the second target patterns can include word lines WL.
  • a gap between the select line DSL or SSL and an edge word line neighboring the select line DSL or SSL, from among the word lines WL can become the same as a gap between the word lines WL.
  • a problem that the etch rate becomes relatively fast in some regions and the gate insulating layer 103 is damaged and a problem that there is a difference in the degree of loss in an isolation layer can be improved. More particularly, a difference in the thickness between a gate insulating layer 103 , remaining between the neighboring word lines WL, and the gate insulating layer 103 , remaining between the edge word line WL and the select line DSL or SSL, can be improved within 5 ⁇ . Further, a difference in the thickness between the isolation layer, remaining between the neighboring word lines WL, and the isolation layer, remaining between the edge word line WL and the select line DSL or SSL, can be improved within 10 ⁇
  • the edge word line WL neighboring the select line DSL or SSL is not used as a word line for driving memory cells for storing data, but can be used as a passing word line for improving disturbance.
  • this disclosure is applied to form a gate pattern, damage to the gate insulating layer 103 can be prevented. Accordingly, in accordance with this disclosure, since it is not necessary to reduce the thickness becoming an etch target of the dielectric layer 107 to prevent damage to the gate insulating layer 103 , a problem that the dielectric layer 107 remains on the sidewalls of the first conductive layer 105 can be improved. Consequently, a phenomenon in which a bridge is generated between neighboring strings because the dielectric layer 107 remains on the sidewalls of the first conductive layer 105 and a phenomenon in which a data retention characteristic deteriorates because of the loss of charges can be improved. Furthermore, in accordance with this disclosure, since an irregular loss of an isolation layer resulting from a loading effect can be improved, the deterioration of a cycling characteristic occurring because the threshold voltage is shifted by the irregular loss of the isolation layer can be improved.
  • the auxiliary layer including the passivation pattern is etched.
  • the remaining auxiliary layer is classified into a portion, not overlapped with the passivation pattern and having a top surface exposed, and a portion, overlapped with the passivation pattern and having a top surface blocked by the passivation pattern.
  • the spacers are formed on the sidewalls of the auxiliary layer and the passivation pattern remaining in a subsequent process and the exposed auxiliary layer is then removed, the auxiliary layer overlapped with and protected by the passivation pattern remains intact, thus defining the region where the first target pattern will be formed, having a relatively wide width, along with the spacer formed on the sidewall of the auxiliary layer.
  • the spacers separated from each other with the region, having the auxiliary layer removed therefrom, interposed therebetween define the respective regions in which the second target patterns, each having a narrower width than the first target pattern, will be formed. Consequently, in accordance with this disclosure, the patterns with different widths can be formed in the same layer at the same time using the remaining spacers and the remaining auxiliary layer as an etch mask.
  • the passivation pattern is wider than the photoresist pattern functioning as an etch mask when etching the passivation pattern.
  • the photoresist patterns functioning as an etch mask can be easily aligned on the passivation pattern.
  • the passivation pattern can have a target width by removing the passivation pattern and the auxiliary layer exposed between the photoresist patterns in a subsequent process. In accordance with the above process, the width of each of the regions from which the passivation pattern and the auxiliary layer have been removed is determined by a gap between the photoresist patterns formed through the same photolithography process.
  • the regions from which the passivation pattern and the auxiliary layer have been removed can have the same width. Since the width of the region from which the passivation pattern and the auxiliary layer have been removed defines a gap between the patterns of a semiconductor device to be formed, the patterns of the semiconductor device can be formed to have an uniform gap.
  • the gap between the patterns of the semiconductor device can be uniformly defined, a loading effect in which the etch rate becomes relatively fast in some regions in an etch process of forming the patterns of the semiconductor device can be improved. Accordingly, problems resulting from the loading effect can be improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of forming patterns of a semiconductor device comprising forming an auxiliary layer over an underlying layer comprising a cell region and a select transistor region, forming a first passivation layer over the auxiliary layer, wherein the first passivation layer blocks the auxiliary layer of the select transistor region and opens the auxiliary layer of the cell region, and forming a first photoresist pattern having a narrower width than the first passivation layer over (a) the first passivation layer and (b) second photoresist patterns, each having a narrower width than the first photoresist pattern, over an opening region of the auxiliary layer, wherein a gap between the first and second photoresist patterns is identical in width with a gap defined between the second photoresist patterns.

Description

CROSS-REFERENCE TO RELATED APPLICATION
Priority to Korean patent application number 10-2010-0066496 filed Jul. 9, 2010, the entire disclosure of which is incorporated by reference herein, is claimed.
BACKGROUND
An exemplary embodiment relates to a method of forming patterns of a semiconductor device and, more particularly, to a method of forming the patterns of a semiconductor device to improve the uniformity of a gap between patterns with different widths when forming the patterns in the same layer.
Patterns of a semiconductor device can have a variety of sizes. A NAND flash memory device is described as an example. A plurality of strings is formed in a memory cell array region of the NAND flash memory device. Each of the strings includes a source select transistor, a drain select transistor, and a plurality of memory cells coupled in series between the source select transistor and the drain select transistor. The gate of the source select transistor is coupled to the source select line, the gate of the drain select transistor is coupled to the drain select line, and the gates of the memory cells are coupled to word lines. Furthermore, each of the drain select line and the source select line can be wider than the word line. In particular, the word line can have a fine line width that is narrower than the exposure resolution limit, due to the degree of integration of such devices.
As described above, in order to form patterns each having a fine line width narrower than the exposure resolution limit, “Spacer Patterning Technology” (SPT) using spacers has been proposed. The SPT method includes processes of forming first auxiliary patterns for providing prominence and depression shapes so that spacers can be formed, depositing a spacer layer on the surface of the entire structure including the first auxiliary patterns, forming the spacers on the sidewalls of the first auxiliary patterns by etching the spacer layer using an etch method, such as etch-back, so that the spacer layer remains on the sidewalls of the first auxiliary patterns, removing the first auxiliary patterns, and etching an underlying layer using the remaining spacers as an etch mask. In accordance with the SPT method using spacers, patterns having a fine line width can be formed by controlling the thickness of the spacer layer. However, to form patterns each having a line width wider than that of the spacer, a process of forming second auxiliary patterns each having a line width wider than that of the spacer must be further performed after forming the first auxiliary patterns. The second auxiliary patterns, together with the spacer, function as an etch mask in a process of etching the underlying layer, and they are used to form patterns each having a line width wider than the spacer.
FIG. 1 is a diagram showing an alignment relationship between spacers and auxiliary patterns used to form patterns with different line widths.
Referring to FIG. 1, as described above, spacers 53, each defining the width of each of fine patterns narrower than the exposure resolution limit, are formed on sidewalls of first auxiliary patterns 51. A gap D1 between the spacers 53 is defined by the first auxiliary patterns 51. A second auxiliary pattern 55 is formed over a region in which patterns, each having a width wider than a width defined by the spacer 53, will be formed. Here, a gap D2 between a pattern defined by the second auxiliary pattern 55 and the pattern defined by the spacer 53 is determined according to the alignment of the second auxiliary patterns 55. In general, the gap D2 between the finer pattern and the pattern that is wider than the exposure resolution is wider than the gap D1 between the fine patterns defined by the spacers because of the alignment margin of the second auxiliary patterns 55. In this case, in an etch process of forming the patterns of a semiconductor device with different widths, a loading effect in which there is a difference in the degree of etching according to a difference in the density of patterns occurs, which can lead to damage to some regions of the semiconductor device. Problems occurring because of the loading effect are described in more detail below with reference to FIG. 2.
FIG. 2 is a cross-sectional view showing part of a NAND flash memory device formed using a conventional method of forming patterns of a semiconductor device.
Referring to FIG. 2, a gate pattern, including word lines WL and a select line DSL/SSL, is patterned using hard mask patterns 21 as an etch mask. The select line DSL/SSL can include a drain select line DSL or a source select line SSL.
A hard mask pattern 21 for patterning the word line WL can have a line width defined by the above-described spacer and have a line width finer than the exposure resolution. Further, a hard mask pattern 21 for patterning the select line DSL/SSL can have its line width defined by the second auxiliary pattern and have a wider line width than that of the hard mask pattern 21 for patterning the word lines WL. However, a second gap D2 between the select line DSL/SSL and a neighboring word line WL can be wider than a first gap D1 between neighboring word lines WL according to the alignment of the second auxiliary patterns. Thus, in the etch process of forming the gate pattern, layers exposed between the select line DSL/SSL and the neighboring word line WL can be etched faster than layers exposed between the word lines WL, because of a loading effect.
In general, the patterning process of forming the gate pattern is performed after stacking an isolation layer (not shown), a dielectric layer 17, and a second conductive layer 19 over the first conductive layer 15, separated from each other with the isolation layer interposed therebetween, and forming the hard mask pattern 21 over the second conductive layer 19. Before forming the dielectric layer 17, the first conductive layer 15 formed on a gate insulating layer 13 over a semiconductor substrate 11 can be separated with the isolation region interposed therebetween. The above process can be performed by stacking the gate insulating layer 13 and the first conductive layer 15 over the semiconductor substrate 11, forming an isolation mask pattern on the first conductive layer 15, forming trenches (not shown) by etching the first conductive layer 15, the gate insulating layer 13, and the isolation regions of the semiconductor substrate 11 using the isolation mask pattern as an etch mask, and then filling the trenches with the isolation layer. The height of the isolation layer preferably is lower than a top surface of the first conductive layer 15 to increase the area in which the first conductive layer 15 and the second conductive layer 19 face each other and increase the coupling ratio of the gate patterns and preferably higher than a top surface of the gate insulating layer 13 to protect the gate insulating layer 13. Consequently, the dielectric layer 17 is formed on not only the top surfaces of the isolation layer and the first conductive layer 15, but also on the exposed sidewalls of the first conductive layer 15 because of a difference in the height between the first conductive layer 15 and the isolation layer. The thickness of the dielectric layer 17 preferably is controlled so that it does not fill the space between the first conductive layers 15. Meanwhile, in the region in which the select line DSL/SSL will be formed, a contact hole through which the first conductive layer 15 is exposed is formed in the dielectric layer 17. The second conductive layer 19 is formed over the dielectric layer 17 having the contact hole formed therein.
The first conductive layer 15, the dielectric layer 17, and the second conductive layer 19 formed by the above process are etched by an etch process using the hard mask pattern 21 as an etch mask. Here, the second conductive layer 19, the dielectric layer 17, and the first conductive layer 15 are removed in the portion not blocked by the hard mask pattern 21. The second conductive layer 19, the dielectric layer 17, and the first conductive layer 15 can be etched faster in the portion opened in the second width D2, having a relatively wide width with respect to the first width D1, than in the portion opened in the first width D1. Consequently, the gate insulating layer 13 that must remain intact under the second conductive layer 19 can be damaged. To prevent such damage to the gate insulating layer 13, if the thickness of an etch target is reduced when etching the dielectric layer 17, the dielectric layer 17 can remain on the sidewalls of the first conductive layer 15, which can cause a bridge between neighboring strings and the loss of charges. Furthermore, the isolation layer is irregularly lost because of a loading effect, leading to cycling deterioration.
BRIEF SUMMARY
An exemplary embodiment relates to a method of forming the patterns of a semiconductor device, which is capable of improving the uniformity of a gap between patterns having different widths when forming the patterns in the same layer.
A method of forming the patterns of a semiconductor device according to an aspect of the present disclosure comprises forming an auxiliary layer over an underlying layer comprising a cell region and a select transistor region, forming a first passivation layer over the auxiliary layer, where in the first passivation layer blocks the auxiliary layer of the select transistor region and opens the auxiliary layer of the cell region, and forming (a) a first photoresist pattern having a narrower width than the first passivation layer over the first passivation layer and (b) second photoresist patterns, each second photoresist pattern having a narrower width than the first photoresist pattern, over an opening region of the auxiliary layer, to define a gap between the first and second photoresist patterns and a gap between the second photoresist patterns, wherein the gap between the first and second photoresist patterns is identical in width with the gap defined between the second photoresist patterns.
The method preferably further comprises, after forming the first and second photoresist patterns, removing an exposed region of the first passivation layer, removing exposed regions of the auxiliary layer to form auxiliary patterns, removing the first and second photoresist patterns to expose the first passivation layer and the auxiliary patterns that do not overlap with the first passivation layer, forming spacers on sidewalls of the auxiliary patterns, and removing the exposed auxiliary patterns.
The method preferably further comprises forming a hard mask layer over the underlying layer before forming the auxiliary layer, forming hard mask patterns by removing an exposed region of the hard mask layer using the spacers and the auxiliary patterns remaining under the first passivation layer as an etch mask, and forming target patterns by etching an exposed region of the underlying layer using the hard mask pattern as an etch mask after removing the exposed auxiliary patterns.
The first passivation layer preferably is formed over the auxiliary layer of the select transistor region by removing the first passivation layer over the cell region after forming the first passivation layer over the entire surface of the auxiliary layer. The first passivation layer over the cell region preferably is removed by forming a photoresist pattern on the first passivation layer over the select transistor region, etching an exposed region of the first passivation layer to a desired thickness, removing the photoresist pattern, and then etching the first passivation layer using a blanket etch process until the auxiliary layer is exposed.
The method preferably further comprises forming a second passivation layer over the auxiliary layer before forming the first and second photoresist patterns.
The target patterns preferably comprise a first target pattern having a width defined by the sum of a width of the auxiliary pattern under the first passivation layer and a width of the spacer formed on the sidewall of the auxiliary pattern, and second target patterns, each having a width defined by the width of the spacer.
The first target pattern preferably includes a drain select line or a source select line of a NAND flash memory device. The second target patterns preferably include the word lines of the NAND flash memory device.
A method of forming the patterns of a semiconductor device according to another aspect of the present disclosure comprises stacking a hard mask layer and an auxiliary layer over an underlying layer, forming a passivation pattern covering only a portion of the auxiliary layer, forming etch mask patterns over portions of the passivation pattern and the auxiliary layer not covered by the passivation pattern, removing exposed regions of the passivation pattern and the auxiliary layer not covered by the etch mask patterns, removing the etch mask patterns to expose the passivation pattern and the auxiliary layer not covered by the passivation pattern, forming spacers on sidewalls of the remaining auxiliary layer, removing an exposed portion of the auxiliary layer not covered by the passivation pattern, forming hard mask patterns by removing an exposed region of the hard mask layer using the spacers and the remaining auxiliary layer overlapped with the passivation pattern as an etch mask; and forming a plurality of target patterns by etching an exposed region of the underlying layer using the hard mask patterns as an etch mask.
The passivation pattern preferably is formed by forming a first passivation layer over the auxiliary layer, forming a photoresist pattern over the first passivation layer, lowering a height of the first passivation layer in an exposed region of the first passivation layer by etching the exposed region of the first passivation layer using the photoresist pattern as an etch mask, removing the photoresist pattern, and then etching the first passivation layer using a blanket etch process until the auxiliary layer is exposed.
The etch mask pattern preferably comprises a first photoresist pattern formed over the passivation pattern and having a narrower width than the width of the passivation pattern, and second photoresist patterns not overlapped with the passivation pattern, formed over the auxiliary layer, and each configured to have a narrower width than the width of the first photoresist pattern.
The method preferably further comprises forming a second passivation layer over the auxiliary layer, including the passivation pattern, before forming the etch mask pattern.
Before removing exposed regions of the passivation pattern and the auxiliary layer that do not overlap with the etch mask pattern, the second passivation layer exposed between the etch mask patterns preferably is removed. The remaining second passivation layer preferably is removed after removing the etch mask pattern.
In the above embodiments, the auxiliary layer preferably comprises a Spin-On Carbon (SOC) layer.
In the above embodiments, the first passivation layer preferably is deposited at a temperature in a range of 40° C. to 90° C. Further, the first passivation layer preferably comprises a Spin-On Carbon (SOC) layer, an amorphous carbon layer, or an oxide layer.
In the above embodiments, the second passivation layer preferably comprises SiC, polysilicon, or SiON.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing an alignment relationship between spacers and auxiliary patterns used to form patterns with different line widths;
FIG. 2 is a cross-sectional view showing part of a NAND flash memory device formed using a conventional method of forming patterns of a semiconductor device; and
FIGS. 3A to 3I are cross-sectional views illustrating a method of forming the patterns of a semiconductor device according to an exemplary embodiment of this disclosure.
 DESCRIPTION OF EMBODIMENT
Hereinafter, an exemplary embodiment of the present disclosure is described in detail with reference to the accompanying drawings. The drawing figures are provided to allow those having ordinary skill in the art to understand the scope of the embodiment of the disclosure.
FIGS. 3A to 3I are cross-sectional views illustrating a method of forming the patterns of a semiconductor device according to an exemplary embodiment of this disclosure.
Referring to FIG. 3A, a hard mask layer 117 and an auxiliary layer 121 are stacked over an underlying layer for forming patterns.
The underlying layer can be a semiconductor substrate 101 in itself or can be a layer including at least one of a conductive layer and an insulating layer formed over the semiconductor substrate 101. Where this disclosure is used to form gate patterns of a NAND flash memory device, the underlying layer can be a gate insulating layer 103, a first conductive layer 105, a dielectric layer 109, and a second conductive layer 111, which are stacked over the semiconductor substrate 101. In this case, a contact hole through which the first conductive layer 105 is exposed is formed in the dielectric layer 109, and the first conductive layer 105 and the second conductive layer 111 thus can be electrically coupled through the contact hole. The contact hole is disposed in a region where a source select line and a drain select line will be formed. The first conductive layer 105 and the second conductive layer 111 preferably are made of polysilicon, and the dielectric layer 109 preferably is formed by stacking an oxide layer, a nitride layer, and an oxide layer.
The hard mask layer 117 serves as an etch mask when subsequently etching the underlying layer. The hard mask layer 117 can be formed of a single layer or a plurality of stack layers according to the etch selectivity for the underlying layer. For example, where a gate pattern is to be formed, the hard mask layer 117 can have a stack structure of an oxide layer 113, being capable of serving as an etch mask when etching the second conductive layer 111 made of polysilicon in a subsequent process, and a polysilicon layer 115 capable of protecting the oxide layer 113 when etching the auxiliary layer 121 in a subsequent process.
The auxiliary layer 121 preferably is made of a material selected with consideration taken of the etch selectivity for a spacer layer formed in a subsequent process. For example, the auxiliary layer 121 can be formed of a Spin-On Carbon (SOC) layer.
Referring to FIG. 3B, a first passivation layer 123 is formed over the auxiliary layer 121. The first passivation layer 123 preferably is made of a material selected by taking the etch selectivity for the auxiliary layer 121 into consideration. For example, the first passivation layer 123 preferably is formed of a layer deposited at a temperature in a range of 40° C. to 90° C. At 40 to 90° C., an oxide layer such as an Ultra Low Temperature Oxide (ULTO) layer, a Spin On Carbon (SOC) layer, or an Amorphous Carbon Layer (ACL) can be formed. Furthermore, the first passivation layer 123 preferably is formed in thickness of 100 Å to 500 Å.
A photoresist pattern 125 (i.e., an etch mask pattern) is formed over the first passivation layer 123. The photoresist pattern 125 is formed as a pattern for blocking the first passivation layer 123 over a region in which a first target pattern having a relatively wide width (e.g., a select transistor region where a source select line or a drain select line will be formed) and for exposing the first passivation layer 123 over a region in which a second target pattern having a narrower width than the first target pattern will be formed (e.g., a cell region where word lines will be formed).
Referring to FIG. 3C, the exposed region of the first passivation layer 123 is etched using the photoresist pattern 125 as an etch mask. Here, to prevent the auxiliary layer 121 from being lost in a subsequent strip process of removing the photoresist pattern 125, the first passivation layer 123 can be etched to a desired thickness so that the auxiliary layer 121 is not exposed. Thus, the first passivation layer 123 becomes thinner in the region not blocked by the photoresist pattern 125 than in the region blocked by the photoresist pattern 125.
Referring to FIG. 3D, the photoresist pattern 125 is removed, preferably using a strip process. Thus, the first passivation layer 123 over the regions in which the first and second target patterns will be formed is exposed.
Referring to FIG. 3E, the auxiliary layer 121 over the region in which the second target pattern will be formed is exposed by etching the first passivation layer 123 exposed over the regions in which the first and second target patterns will be formed using an etch process, such as by a blanket etch process. However, the first passivation layer 123 over the region in which the first target pattern will be formed remains intact as a passivation pattern 123 a having a first width W1, as shown in FIG. 3E, so that the auxiliary layer 121 over the region where the first target pattern will be formed is blocked.
The first passivation layer 123 can remain as the passivation pattern 123 a having the first width W1 over the region in which the first target pattern will be formed, as described above, because the first passivation layer 123 is thicker over the region in which the first target pattern will be formed than over the region in which the second target pattern will be formed. Meanwhile, the first width W1 preferably is wider than the width of a first photoresist pattern which will be formed over the passivation pattern 123 a in a subsequent process. This of guarantees the alignment margin when forming the first photoresist pattern in the subsequent process. Further, if the first width W1 is wider than the width of the first photoresist pattern to be formed over the passivation pattern 123 a, the auxiliary layer 121 over the region in which the first target pattern will be formed will be fully blocked by the passivation pattern 123 a and a spacer to be formed in a subsequent process. Accordingly, when subsequently removing the auxiliary layer 121 exposed over the region in which the second target pattern will be formed, the auxiliary layer 121 over the region in which the first target pattern will be formed can be protected by the passivation pattern 123 a and the spacer, and so it can remain intact.
Referring to FIG. 3F, an etch mask pattern 129 is formed over the auxiliary layer 121 including the passivation pattern 123 a having the first width W1. Before forming the etch mask pattern 129, a second passivation layer 127 can be formed over the auxiliary layer 121 including the passivation pattern 123 a having the first width W1.
The second passivation layer 127 preferably is formed of a Multi-Function Hard Mask (MFHM) layer. The second passivation layer 127 prevents the auxiliary layer 121 from being removed when removing the etch mask pattern 129 (i.e., photoresist materials) such as by using a strip process in a subsequent process. The auxiliary layer 121 preferably comprises carbon-rich SiC, polysilicon, or SiON.
The etch mask pattern 129 includes a first photoresist pattern 129 a and a second photoresist pattern 129 b. The first photoresist pattern 129 a has a second width W2 narrower than the first width W1 of the passivation pattern 123 a and overlapping the passivation pattern 123 a thereon. The second photoresist pattern 129 b has a third width W3 narrower than the second width W2 and overlapping the auxiliary layer 121 not protected by the passivation pattern 123 a having the first width W1. To subsequently make identical the width of a gap between the first target pattern and the second target pattern and a gap between neighboring second target patterns, a gap between the first photoresist pattern 129 a and the second photoresist pattern 129 b, which are adjacent to each other, preferably has a first gap L1, which is identical with a gap between the second photoresist patterns 129 b adjacent to each other.
As described above, since the first and second photoresist patterns 129 a and 129 b with different widths are formed through a single photolithography process, the gap L1 between them can be uniformly formed. Further, since the second width W2 of the first photoresist pattern 129 a is narrower than the first width W1 of the passivation pattern 123 a, the second width W2 can easily overlap with the first width W1 thereon.
The second passivation layer 127, the passivation pattern 123 a having the first width W1, and the auxiliary layer 121, which are exposed between the etch mask patterns 129 a and 129 b, are removed.
Accordingly, as shown in FIG. 3G, a passivation pattern 123 b having the second width W2 and a plurality of auxiliary patterns 121 a protected or not protected by the passivation pattern 123 b having the second width W2 are formed over the hard mask layer 117. A portion protected by the passivation pattern 123 b having the second width W2, from among the auxiliary patterns 121 a, has the second width W2, and portions not protected by the passivation pattern 123 b having the second width W2 have a third width W3.
In this disclosure, a gap between the passivation pattern 123 b having the second width W2 and the auxiliary pattern 121 a having the third width W3 and a gap between the neighboring auxiliary patterns 121 a each having the third width W3 are defined by etch mask patterns and so they can be formed to have the first gap L1 identically.
After forming the auxiliary patterns 121 a and the passivation pattern 123 b having the second width W2, the etch mask patterns are removed such as by using a strip process. Next, the remaining second passivation layer 127 can be removed.
Next, spacers 131 are formed on the sidewalls of the auxiliary patterns 121 a. The spacers 131 preferably are formed by forming a spacer layer on a surface of the hard mask layer 117, including the auxiliary patterns 121 a and the passivation pattern 123 b having the second width W2, and then etching the spacer layer using an etch process, such as an etch-back process, to expose the auxiliary patterns 121 a and the passivation pattern 123 b having the second width W2. Here, the thickness of the spacer layer preferably is controlled so that the spacer layer does not fill the space between the auxiliary patterns 121 a. Furthermore, the spacer layer preferably comprises an oxide layer. Meanwhile, the auxiliary pattern 121 a under the passivation pattern 123 b having the second width W2 is protected by the passivation pattern 123 b having the second width W2 and thus is not exposed. Furthermore, the passivation pattern 123 b having the second width W2 can be partially removed such as by using an etch-back process for forming a spacer so that it remains, preferably with a thickness of 50 Å to 400 Å.
Furthermore, a second gap L2 between the spacers 131 formed between the auxiliary patterns 121 a can become the same as the third width W3 by controlling the thickness of the spacer layer.
Referring to FIG. 3H, after removing the auxiliary patterns 121 a, each having the third width W3, not protected by the passivation pattern having the second width W2, the exposed region of the hard mask layer 117 is removed using the remaining spacers and the remaining auxiliary pattern having the second width W2 under the passivation pattern, having the second width W2, as an etch mask. Accordingly, hard mask patterns 117 a with different line widths are formed. Here, since the width of each of the regions opened by removing the auxiliary patterns, each having the third width W3, is identical with the width of the region opened between the spacers, the width of each of the regions not blocked by the hard mask patterns 117 a can also be identically formed.
The hard mask pattern 117 a preferably has a stack structure of a polysilicon layer pattern 115 a, formed by etching a polysilicon layer, and an oxide layer pattern 113 a formed by etching an oxide layer not blocked by the polysilicon layer pattern 115 a. After forming the hard mask pattern 117 a, the remaining spacers, the remaining passivation pattern having the second width, and the remaining auxiliary patterns can be removed.
In the foregoing, the etch process of forming the spacers, the process of removing the auxiliary patterns each having the third width, and the etch process of forming the hard mask pattern 117 a preferably are performed in-situ. Accordingly, a process of manufacturing semiconductor devices can be simplified.
Referring to FIG. 3I, exposed regions of the underlying layer are removed using the hard mask patterns as an etch mask. Accordingly, the first target pattern DSL/SSL and the second target patterns WL each narrower than the first target pattern DSL/SSL are formed at the same time. Here, since the regions not blocked by the hard mask patterns have the same width, a loading effect in which the etch rate is relatively fast in some regions can be improved. Further, a width of the first target pattern DSL/SSL is defined by the sum of the second width and a width of the spacer formed on the sidewall of the passivation pattern having the second width. Furthermore, a width of the second target pattern WL is defined by a width of the spacer.
A case where a gate pattern is formed is described as an example. The underlying layer removed by an etch process using hard mask patterns as an etch mask can include a second conductive layer 111, a dielectric layer 109, and a first conductive layer 105. The first target pattern can include a drain select line DSL or a source select line SSL, and the second target patterns can include word lines WL. In case where this disclosure is applied to a process of forming the gate pattern as described above, a gap between the select line DSL or SSL and an edge word line neighboring the select line DSL or SSL, from among the word lines WL can become the same as a gap between the word lines WL. Furthermore, in accordance with this disclosure, since the regions not blocked by the hard mask patterns have the same width, a problem that the etch rate becomes relatively fast in some regions and the gate insulating layer 103 is damaged and a problem that there is a difference in the degree of loss in an isolation layer can be improved. More particularly, a difference in the thickness between a gate insulating layer 103, remaining between the neighboring word lines WL, and the gate insulating layer 103, remaining between the edge word line WL and the select line DSL or SSL, can be improved within 5 Å. Further, a difference in the thickness between the isolation layer, remaining between the neighboring word lines WL, and the isolation layer, remaining between the edge word line WL and the select line DSL or SSL, can be improved within 10 Å
In the foregoing, the edge word line WL neighboring the select line DSL or SSL is not used as a word line for driving memory cells for storing data, but can be used as a passing word line for improving disturbance.
In case where as described above, this disclosure is applied to form a gate pattern, damage to the gate insulating layer 103 can be prevented. Accordingly, in accordance with this disclosure, since it is not necessary to reduce the thickness becoming an etch target of the dielectric layer 107 to prevent damage to the gate insulating layer 103, a problem that the dielectric layer 107 remains on the sidewalls of the first conductive layer 105 can be improved. Consequently, a phenomenon in which a bridge is generated between neighboring strings because the dielectric layer 107 remains on the sidewalls of the first conductive layer 105 and a phenomenon in which a data retention characteristic deteriorates because of the loss of charges can be improved. Furthermore, in accordance with this disclosure, since an irregular loss of an isolation layer resulting from a loading effect can be improved, the deterioration of a cycling characteristic occurring because the threshold voltage is shifted by the irregular loss of the isolation layer can be improved.
As described above, in accordance with this disclosure, after forming the passivation pattern over the auxiliary layer, the auxiliary layer including the passivation pattern is etched. Thus, the remaining auxiliary layer is classified into a portion, not overlapped with the passivation pattern and having a top surface exposed, and a portion, overlapped with the passivation pattern and having a top surface blocked by the passivation pattern. Accordingly, although the spacers are formed on the sidewalls of the auxiliary layer and the passivation pattern remaining in a subsequent process and the exposed auxiliary layer is then removed, the auxiliary layer overlapped with and protected by the passivation pattern remains intact, thus defining the region where the first target pattern will be formed, having a relatively wide width, along with the spacer formed on the sidewall of the auxiliary layer. Further, the spacers separated from each other with the region, having the auxiliary layer removed therefrom, interposed therebetween define the respective regions in which the second target patterns, each having a narrower width than the first target pattern, will be formed. Consequently, in accordance with this disclosure, the patterns with different widths can be formed in the same layer at the same time using the remaining spacers and the remaining auxiliary layer as an etch mask.
Furthermore, in accordance with this disclosure, the passivation pattern is wider than the photoresist pattern functioning as an etch mask when etching the passivation pattern. Thus, when etching the auxiliary layer including the passivation pattern, the photoresist patterns functioning as an etch mask can be easily aligned on the passivation pattern. Further, the passivation pattern can have a target width by removing the passivation pattern and the auxiliary layer exposed between the photoresist patterns in a subsequent process. In accordance with the above process, the width of each of the regions from which the passivation pattern and the auxiliary layer have been removed is determined by a gap between the photoresist patterns formed through the same photolithography process. Accordingly, the regions from which the passivation pattern and the auxiliary layer have been removed can have the same width. Since the width of the region from which the passivation pattern and the auxiliary layer have been removed defines a gap between the patterns of a semiconductor device to be formed, the patterns of the semiconductor device can be formed to have an uniform gap.
In accordance with this disclosure, since the gap between the patterns of the semiconductor device can be uniformly defined, a loading effect in which the etch rate becomes relatively fast in some regions in an etch process of forming the patterns of the semiconductor device can be improved. Accordingly, problems resulting from the loading effect can be improved.

Claims (21)

1. A method of forming patterns of a semiconductor device, comprising:
forming an auxiliary layer over an underlying layer comprising a cell region and a select transistor region;
forming a first passivation layer over the auxiliary layer, wherein the first passivation layer blocks the auxiliary layer of the select transistor region and opens the auxiliary layer of the cell region;
forming (a) a first photoresist pattern having a narrower width than the first passivation layer over the first passivation layer and (b) second photoresist patterns, each second photoresist pattern having a narrower width than the first photoresist pattern, over an opening region of the auxiliary layer, to define a gap between the first and second photoresist patterns and a gap between the second photoresist patterns, wherein the gap between the first and second photoresist patterns is identical in width with the gap defined between the second photoresist patterns;
removing an exposed region of the first passivation layer;
removing exposed regions of the auxiliary layer to form auxiliary patterns;
removing the first and second photoresist patterns to expose the first passivation layer and the auxiliary patterns that do not overlap with the first passivation layer;
forming spacers on sidewalls of the auxiliary patterns; and
removing the exposed auxiliary patterns.
2. The method of claim 1, further comprising:
forming a hard mask layer over the underlying layer before forming the auxiliary layer;
forming hard mask patterns by removing an exposed region of the hard mask layer using the spacers and the auxiliary patterns remaining under the first passivation layer as an etch mask; and
forming target patterns by etching an exposed region of the underlying layer using the hard pattern as an etch mask after removing the exposed auxiliary patterns.
3. The method of claim 2, wherein the auxiliary layer comprises a Spin-On Carbon (SOC) layer.
4. The method of claim 1, comprising forming the first passivation layer over the auxiliary layer of the select transistor region by removing the first passivation layer over the cell region after forming the first passivation layer over an entire surface of the auxiliary layer.
5. The method of claim 4, comprising removing the first passivation layer over the cell region by forming a photoresist pattern on the first passivation layer over the select transistor region, etching an exposed region of the first passivation layer to a desired thickness, removing the photoresist pattern, and then etching the first passivation layer using a blanket etch process until the auxiliary layer is exposed.
6. The method of claim 1, comprising depositing the first passivation layer at a temperature in a range of 40° C. to 90° C.
7. The method of claim 6, wherein the first passivation layer comprises a Spin-On Carbon (SOC) layer, an amorphous carbon layer, or an oxide layer.
8. The method of claim 1, further comprising forming a second passivation layer over the auxiliary layer before forming the first and second photoresist patterns.
9. The method of claim 8, wherein the second passivation layer comprises SiC, polysilicon, or SiON.
10. The method of claim 2, wherein the target patterns comprise a first target pattern having a width defined by a sum of a width of the auxiliary pattern under the first passivation layer and a width of the spacer formed on a sidewall of the auxiliary pattern, and second target patterns, each having a width defined by the width of the spacer.
11. The method of claim 10, wherein:
the first target pattern includes a drain select line or a source select line of a NAND flash memory device; and
the second target patterns include word lines of the NAND flash memory device.
12. A method of forming patterns of a semiconductor device, comprising:
stacking a hard mask layer and an auxiliary layer over an underlying layer;
forming a passivation pattern covering only a portion of the auxiliary layer;
forming etch mask patterns over portions of the passivation pattern and the auxiliary layer not covered by the passivation pattern;
removing exposed regions of the passivation pattern and the auxiliary layer not covered by the etch mask patterns;
removing the etch mask patterns to expose the passivation pattern and the auxiliary layer not covered by the passivation pattern;
forming spacers on sidewalls of the remaining auxiliary layer;
removing an exposed portion of the auxiliary layer not covered by the passivation pattern;
forming hard mask patterns by removing an exposed region of the hard mask layer using the spacers and the remaining auxiliary layer overlapped with the passivation pattern as an etch mask; and
forming a plurality of target patterns by etching an exposed region of the underlying layer using the hard mask patterns as an etch mask.
13. The method of claim 12, wherein the auxiliary layer comprises a Spin-On Carbon (SOC) layer.
14. The method of claim 12, comprising forming the passivation pattern by:
forming a first passivation layer over the auxiliary layer;
forming a photoresist pattern over the first passivation layer;
lowering a height of the first passivation layer in an exposed region of the first passivation layer by etching the exposed region of the first passivation layer using the photoresist pattern as an etch mask;
removing the photoresist pattern; and
then etching the first passivation layer using a blanket etch process until the auxiliary layer is exposed.
15. The method of claim 14, comprising depositing the first passivation layer at a temperature in a range of 40° C. to 90° C.
16. The method of claim 14, wherein the first passivation layer comprises a Spin-On Carbon (SOC) layer, an amorphous carbon layer, or an oxide layer.
17. The method of claim 12, wherein the etch mask pattern comprises (a) a first photoresist pattern formed over the passivation pattern and having a narrower width than the width of the passivation pattern, and (b) second photoresist patterns not overlapped with the passivation pattern and formed over the auxiliary layer, each second photoresist pattern having a narrower width than the width of the first photoresist pattern.
18. The method of claim 17, wherein a gap defined between the first and second photoresist patterns is identical in width with a gap defined between the second photoresist patterns.
19. The method of claim 12, further comprising forming a second passivation layer over the auxiliary layer, including the passivation pattern, before forming the etch mask pattern.
20. The method of claim 19, comprising:
removing the second passivation layer exposed between the etch mask patterns before removing exposed regions of the passivation pattern and the auxiliary layer that does not overlap with the etch mask pattern; and
removing the remaining second passivation layer after removing the etch mask pattern.
21. The method of claim 20, wherein the second passivation layer comprises SiC, polysilicon, or SiON.
US12/914,985 2010-07-09 2010-10-28 Method of forming patterns of a semiconductor device including forming spacers on sidewalls of auxiliary patterns and removing exposed auxiliary patterns Expired - Fee Related US7972967B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2010-0066496 2010-07-09
KR1020100066496A KR101094486B1 (en) 2010-07-09 2010-07-09 Pattern formation method of semiconductor device

Publications (1)

Publication Number Publication Date
US7972967B1 true US7972967B1 (en) 2011-07-05

Family

ID=44202389

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/914,985 Expired - Fee Related US7972967B1 (en) 2010-07-09 2010-10-28 Method of forming patterns of a semiconductor device including forming spacers on sidewalls of auxiliary patterns and removing exposed auxiliary patterns

Country Status (4)

Country Link
US (1) US7972967B1 (en)
JP (1) JP2012019184A (en)
KR (1) KR101094486B1 (en)
CN (1) CN102315118A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8298954B1 (en) * 2011-05-06 2012-10-30 International Business Machines Corporation Sidewall image transfer process employing a cap material layer for a metal nitride layer
US20130309854A1 (en) * 2012-05-16 2013-11-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors
US8969215B2 (en) 2012-11-20 2015-03-03 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices using double patterning technology
US9378979B2 (en) 2012-11-20 2016-06-28 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices and devices fabricated thereby
US10319592B2 (en) * 2015-09-04 2019-06-11 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014053436A (en) * 2012-09-06 2014-03-20 Toshiba Corp Semiconductor storage device manufacturing method
CN104945556A (en) * 2015-07-14 2015-09-30 苏州双象光学材料有限公司 Preparation method of methyl methacrylate-styrene copolymer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100874433B1 (en) 2007-11-02 2008-12-17 주식회사 하이닉스반도체 Pattern formation method of semiconductor device
US20090035584A1 (en) * 2007-07-30 2009-02-05 Micron Technology, Inc. Methods for device fabrication using pitch reduction and associated structures
KR20090072920A (en) 2007-12-28 2009-07-02 주식회사 하이닉스반도체 Manufacturing Method of Semiconductor Device
US7727889B2 (en) * 2008-04-29 2010-06-01 Hynix Semiconductor Inc Method for forming fine pattern by spacer patterning technology

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6730610B1 (en) * 2002-12-20 2004-05-04 Taiwan Semiconductor Manufacturing Co., Ltd Multiple thickness hard mask method for optimizing laterally adjacent patterned layer linewidths
KR100784062B1 (en) * 2006-01-20 2007-12-10 주식회사 하이닉스반도체 Method of forming fine pattern of semiconductor device
KR100953049B1 (en) * 2007-12-28 2010-04-14 주식회사 하이닉스반도체 Flash memory device and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090035584A1 (en) * 2007-07-30 2009-02-05 Micron Technology, Inc. Methods for device fabrication using pitch reduction and associated structures
KR100874433B1 (en) 2007-11-02 2008-12-17 주식회사 하이닉스반도체 Pattern formation method of semiconductor device
KR20090072920A (en) 2007-12-28 2009-07-02 주식회사 하이닉스반도체 Manufacturing Method of Semiconductor Device
US7727889B2 (en) * 2008-04-29 2010-06-01 Hynix Semiconductor Inc Method for forming fine pattern by spacer patterning technology

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8298954B1 (en) * 2011-05-06 2012-10-30 International Business Machines Corporation Sidewall image transfer process employing a cap material layer for a metal nitride layer
US20120282779A1 (en) * 2011-05-06 2012-11-08 International Business Machines Corporation Sidewall image transfer process employing a cap material layer for a metal nitride layer
US20130309854A1 (en) * 2012-05-16 2013-11-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors
US9558957B2 (en) * 2012-05-16 2017-01-31 Commissariat à l'Energie Atomique et aux Energies Alternatives Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors
US8969215B2 (en) 2012-11-20 2015-03-03 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices using double patterning technology
US9378979B2 (en) 2012-11-20 2016-06-28 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices and devices fabricated thereby
US10319592B2 (en) * 2015-09-04 2019-06-11 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device

Also Published As

Publication number Publication date
KR101094486B1 (en) 2011-12-19
CN102315118A (en) 2012-01-11
JP2012019184A (en) 2012-01-26

Similar Documents

Publication Publication Date Title
US20120156866A1 (en) Method of forming patterns of semiconductor device
US7972967B1 (en) Method of forming patterns of a semiconductor device including forming spacers on sidewalls of auxiliary patterns and removing exposed auxiliary patterns
US8674425B2 (en) Semiconductor memory device and method of manufacturing the same
KR100814408B1 (en) Non-volatile memory device and manufacturing method thereof.
KR100418091B1 (en) Method of manufacturing semiconductor device
US20110248328A1 (en) Stucture for flash memory cells
US7589374B2 (en) Semiconductor device and related fabrication method
US20180076214A1 (en) Semiconductor device including stacked structure
KR100781563B1 (en) Non-volatile memory device and manufacturing method thereof.
US8048739B2 (en) Method of manufacturing flash memory device
US7679126B2 (en) Split gate type non-volatile memory device and method of manufacturing the same
US7541243B2 (en) Methods of forming integrated circuit devices having gate electrodes formed on non-uniformly thick gate insulating layers
US6953973B2 (en) Self-aligned trench isolation method and semiconductor device fabricated using the same
US7041555B2 (en) Method for manufacturing flash memory device
KR100757337B1 (en) Charge trap type nonvolatile memory device and method of manufacturing same
US8058160B2 (en) Method of forming nonvolatile memory device
US7696560B2 (en) Flash memory device
US6905930B2 (en) Memory device and fabrication method thereof
US20080203458A1 (en) Semiconductor Memory Device and Method of Fabricating the Same
US7169672B1 (en) Split gate type nonvolatile memory device and manufacturing method thereof
KR100825789B1 (en) Nonvolatile Memory Device and Manufacturing Method Thereof
US20130049094A1 (en) Non-volatile memory device and method for fabricating the same
US7109082B2 (en) Flash memory cell
KR100799039B1 (en) Manufacturing Method of Flash Memory Device
KR100912992B1 (en) Gate Forming Method of Semiconductor Device

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYUN, CHAN SUN;REEL/FRAME:025215/0163

Effective date: 20101025

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20150705

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载