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US7635639B2 - Method for the interconnection of active and passive components and resulting thin heterogeneous component - Google Patents

Method for the interconnection of active and passive components and resulting thin heterogeneous component Download PDF

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US7635639B2
US7635639B2 US10/562,685 US56268504A US7635639B2 US 7635639 B2 US7635639 B2 US 7635639B2 US 56268504 A US56268504 A US 56268504A US 7635639 B2 US7635639 B2 US 7635639B2
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support
components
terminals
layer
thinning
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US20070117369A1 (en
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Christian Val
Olivier Lignier
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3D Plus SA
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3D Plus SA
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/19043—Component type being a resistor
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/30105—Capacitance
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a method for the interconnection of active and passive components in two or three dimensions, and to the resulting thin heterogeneous components.
  • capacitors deposited on a substrate can have thicknesses comparable to those of thinned active components.
  • the drawback of these deposited capacitors derives from their very low permittivity, which ranges from 4 to a few tens, while the permittivities of ceramic capacitors reach several thousand.
  • the latter capacitors based on barium titanate are very stable and very reliable. Manufacturers have so far been trying to reduce their thickness, and it has now reached 0.5 to 0.6 mm.
  • the present invention makes it possible to overcome the aforementioned drawbacks by providing a method for the interconnection of active and passive components, which is applicable particularly to the interconnection of chip-type active components and ceramic capacitors, making it possible to produce thin heterogeneous components in two or three dimensions.
  • the method is based on simultaneously thinning the active and passive components coated in a polymer layer by a surface treatment which is heterogeneous, i.e. applied nonselectively both to the passive and active components and to the polymer layer coating them, the Applicant having shown that surprisingly this method does not significantly affect the performance of the passive components, including ceramic capacitors.
  • the invention relates to a method for the interconnection of active and passive components provided with terminals for their interconnection, characterized in that it comprises:
  • FIG. 1 represents an embodiment of the method according to the invention
  • FIGS. 2A , 2 B and 2 C represent exemplary embodiments of the steps of the method according to FIG. 1 ;
  • FIGS. 3A and 3B represent exemplary embodiments of the prior step of thinning on ceramic capacitors
  • FIG. 4 represents the diagram of a resistor to which the method according to the invention may be applied
  • FIG. 5 represents the method according to the invention applied to interconnection in three dimensions
  • FIG. 6 represents a diagram illustrating the steps of the method described in FIG. 5 ;
  • FIG. 7 represents a diagram showing a view in section of a thinned 3D heterogeneous component obtained by the method described by FIG. 5 ;
  • FIG. 8 represents a diagram illustrating the steps of a thin 3D interconnection method according to the invention in one variant.
  • FIG. 1 describes an embodiment of the method according to the invention for interconnecting active and passive components, in particular for the production of very thin heterogeneous components in three dimensions.
  • heterogeneous component is intended to mean an electronic component comprising both one or more active and passive component(s) connected together with a view to forming an electronic component in order to fulfill a given electronic function.
  • the active component comprises any component commonly referred to as a “chip” and employing semiconductor technology, for example of the diode, transistor or integrated circuit type.
  • the term passive component is intended to mean the other components, whether conventional components of the resistor, capacitor or inductor type mounted at the surface, or alternatively electromechanical components etched in silicon and known by the name MEMS (abbreviation for “MicroElectroMechanical Systems”).
  • the thickness of the passive components and in particular ceramic capacitors limits the possibility of thinning the heterogeneous components, and in particular three-dimensional heterogeneous components.
  • the method according to the invention makes it possible to overcome this drawback.
  • the method described in the example of FIG. 1 comprises in particular initially thinning the passive components (step 10 , optional), positioning and fixing at least one active component and one passive component on a flat support (step 11 ), depositing a polymer layer on all of the support and the components (step 12 ), rectifying the layer (step 13 , optional) allowing the surface of the layer to be rendered substantially plane and parallel to the support, removing the support (step 14 ), redistributing the terminals between the components and/or toward the periphery by means of metal conductors (step 15 ), making it possible to obtain a reconstituted heterogeneous structure, thinning said structure by heterogeneous surface treatment consisting in nonselective polishing of the polymer layer and at least one passive component (step 16 ).
  • the first step of the method according to the invention consists in the components, which are provided with terminals for their interconnection and intended to be connected together, being positioned and fixed on a flat support.
  • FIGS. 2A and 2B illustrate steps of the method described in FIG. 1 according to an exemplary embodiment.
  • an active component referenced 21 of a first passive component, for example a conducting wire 20
  • a second passive component referenced 22 in this example a ceramic capacitor
  • FIG. 2C describes the connection of an active component and a passive component of the MEMS type denoted by 27 .
  • These components are positioned and fixed on a support 23 .
  • the terminals of the components, respectively referenced 211 for the active component and 221 for the ceramic capacitor, are in contact with the support.
  • a large number of components arranged in the form of substantially identical patterns may be positioned and fixed on the support 23 .
  • the method is then applied collectively to all of the support, and the reconstituted structure (or reconstituted “wafer”) obtained at the end of the method will be cut in order to obtain a corresponding number of individual heterogeneous components.
  • the support 23 is advantageously an adhesive film which can be taken off without any particular treatment, for example a polyvinyl chloride film of the type used in the fabrication of silicon “wafers” and commonly referred to as a drum skin.
  • the positioning of the components which is very precise, is carried out for example using optical control by a camera with reference points as markers.
  • Using an adhesive film as a support makes it possible to avoid bonding the components with glue, which is more complicated to do because the drop of glue must be extremely well calibrated and thin so as not to touch the points, and is more limited in terms of application possibilities because the points must necessarily lie at the periphery of the component.
  • An adhesive film can furthermore be removed by peeling without any particular treatment, while fixing the support by bonding requires a heat treatment in order to polymerize the glue and a chemical treatment with acid in order to remove it.
  • the ceramic capacitor 22 has undergone a prior thinning step described by means of FIG. 3A .
  • This step which is optional, makes it possible to thin the ceramic capacitor on two opposing faces and thus further reduce its thickness.
  • the ceramic capacitor ( 30 ) comprises in the conventional way a zone of even and odd interdigitated plane electrodes, respectively referenced 31 and 32 , two ceramic filling zones 33 and 34 lying on either side of the electrode zone, which are not electrically functional, and two end terminals referenced 35 (generally of silver-palladium or nickel-gold) to which, for example, the even electrodes 31 and odd electrodes 32 are respectively connected.
  • the ceramic capacitor is thinned on one of its faces, for example by polishing.
  • the capacitor is thinned on a face parallel to the electrodes.
  • the capacitor is bonded onto a support 36 by means of an adhesive material which can be easily taken off, for example wax 37 or a bonding film as described above.
  • the polishing may take place in the zones 33 and 34 which are not electrically functional.
  • FIG. 3A shows the capacitor thinned in the ceramic zone 33 on the section plane referenced C. If this is necessary, however, the Applicant has shown that it is possible to thin in the electrode zone. Naturally, the capacitive value will decrease as the electrode levels are reduced.
  • FIG. 3B illustrates the case of initially thinning a ceramic capacitor with an attached electrode.
  • ceramic capacitors may have end terminals 35 of a material incompatible with the metallization which will be applied during the step of redistributing the terminals (step 15 described below) and which is fixed by chip terminal metallization technology. It may thus be necessary to process the thinned capacitors with non-oxidizable metals or alloys (for example gold or gold-palladium).
  • electrodes 39 in the form of a strip or wire are bonded to the end terminals 35 by means of conductive adhesive (for example containing silver) or by brazing. After thinning (cut C), the non-oxidizable electrodes 39 have sections 391 which can fulfill the function of terminals 221 of the passive component ( FIG. 2A ).
  • the capacitor may be thinned on one of its faces perpendicular to the plane of the electrode, which reduces the capacitive value but makes it possible to maintain the positioning symmetry of the electrodes with respect to the faces that are parallel to them.
  • the external metallizations 35 of the electrodes are extended on the four adjacent faces, and the capacitor may be bonded onto the adhesive support 23 via the ends of the metallizations 35 with the electrodes parallel or perpendicular to the plane of the support.
  • FIG. 4 represents the diagram of a commercial passive component of the resistor type, to which the invention may be applied.
  • the resistor 40 comprises an inert substrate 41 , for example of alumina, the thickness of which is of the order of one millimeter, a resistive layer 42 (of the order of 1 micron) and conductive terminals 43 generally formed by layers of conductive material which enclose the side faces of the component, on either side of the active layer.
  • the active layer 42 which is very thin, is positioned in proximity to one face for this type of component. The prior thinning of the component is possible on the face opposite that bearing the active layer.
  • the active component is subsequently positioned and fixed on the substrate with the face bearing the active layer pointing toward the substrate. During the interconnection method according to the invention, the component is positioned on the support 23 ( FIG.
  • step 16 of the method, described below can take place in the inert layer.
  • the zones 431 of the terminals 43 in contact with the support 23 form the terminals 221 of the component ( FIG. 2A ).
  • the invention likewise applies to a component of the inductor type, the active layer then being an inductive layer.
  • the next step, referenced 12 consists in depositing a polymer layer (referenced 24 in FIGS. 2A , 2 B), for example epoxy resin, on all of the components and the support.
  • a polymer layer referenced 24 in FIGS. 2A , 2 B
  • epoxy resin for example epoxy resin
  • the rectification of the polymer layer is an optional step of the interconnection method according to the invention, which is particularly beneficial in the event that the method is applied collectively to a reconstituted wafer. This is so because it makes it possible to render the surface of the layer substantially plane and parallel to the support 23 , and to give the structure a calibrated thickness (typically 0.8 nm) compatible with the machines conventionally used for the subsequent step of redistributing the terminals on silicon wafers.
  • the rectification, indicated by A in FIG. 2A consists in lapping optionally followed by polishing.
  • the Applicant has shown that, if the thickness of the components so requires, in particular passive components, it is possible to carry out heterogeneous i.e. nonselective thinning which leads to a cut in the thickness of the structure through the various materials formed by the diversity of the components and the layer.
  • the support 23 (step 14 ) is subsequently removed in order to redistribute the terminals (step 15 ).
  • the support being formed by an adhesive film, the removal is carried out simply by peeling the film.
  • the redistribution of the terminals is intended to connect together the components of the same pattern and/or make connections toward the periphery of the pattern with a view to subsequent three-dimensional interconnection.
  • FIG. 2B illustrates an advantageous embodiment of this step.
  • the support 23 being removed, a layer 25 of an insulation material of the photo-etchable polymer type or an etchable resist, on which a polymer layer of the photoresist ⁇ type is deposited, is deposited on all of the surface.
  • the pattern corresponding to the layout of the terminals 221 is etched into the polymer layer by exposure through a mask.
  • a metal layer is subsequently deposited, and then the metal layer is likewise etched by a similar technique according to a predetermined pattern of connections in order to form the metal conductors 26 which connect the component toward another component and/or toward the periphery.
  • several metal layers may be deposited on one another.
  • the choice of the metal must be compatible with the material from which the terminals 221 of the passive and active components are formed.
  • the metal is an alloy of the conventionally used trilayer type having layers of titanium-tungsten, nickel and gold.
  • a reconstituted heterogeneous structure is obtained at the end of this step.
  • the next step, referenced 16 then consists in thinning this structure by heterogeneous surface treatment, that is to say plane nonselective cutting in the thickness of the structure through the various materials formed by the diversity of the components and the layer.
  • the cut denoted B in FIG. 2B is thus made through the polymer forming the layer 24 , the material forming the passive component, for example ceramic for a capacitor as described in FIG. 2B , or alumina in the case of a resistor, and optionally the silicon forming the support of the active component.
  • the cut is made by lapping followed by nonselective polishing of the surface of the structure.
  • the lapping and polishing are advantageously carried out by mechanical abrasion, a method which is widely used in the field of semiconductors and inexpensive.
  • a thin heterogeneous structure is then obtained, which can be cut (step 17 ) in order to form ultrathin heterogeneous elementary components.
  • the components thus obtained are two-dimensional. They may be used per se in order to produce two-dimensional micropackages or, as described below, for stacking in three dimensions.
  • MEMS constitute another particularly advantageous case of a passive component to which the interconnection method according to the invention may be applied.
  • MEMS are electromechanical components etched in silicon and having functions of the sensor type, actuator type, switch type etc. Being very sensitive to humidity and external stresses, they are necessarily arranged in a cavity protected by a cover, for example of plastic.
  • FIG. 2C illustrates the interconnection of a MEMS 27 and a chip 21 with the method according to the invention.
  • the MEMS 27 comprises, protected by a cover 270 , a sensitive part 271 etched in a substrate 272 generally of silicon.
  • the substrate is positioned and bonded on the support 23 (not shown in FIG. 2C ).
  • the sensitive part is located on the substrate 272 on the opposite face from that in contact with the support, so that it does not need to receive adhesive or resin and remains unstressed.
  • a substrate 273 made of alumina or of a printed circuit, that is to say one comprising an insulating film with a layer of copper coated with nickel and gold, etched on each of the 2 faces makes it possible to interface the chip and its substrate with the support 23 and to connect the sensitive part of the MEMS to the conductors of the heterogeneous component.
  • the interface 273 has two faces equipped with metal contacts 275 and 276 respectively on the face next to the support 23 , on which the interface is bonded, and on the opposite face, the contacts being connected together.
  • the contacts 276 are connected to metal terminals 274 of the substrate 272 , which is in contact with the sensitive surface 271 , by connecting wires 277 .
  • the cover 270 which may consist of an organic (epoxy resin) or inorganic material (silicon, glass, ceramic such as alumina, metal or metal alloys) is “bonded” onto the interface 273 . Care is taken for the thickness of the cover to be sufficient so that it can still maintain its integrity and form a protective cavity for the MEMS after the final thinning.
  • the support is then removed in order to redistribute the terminals.
  • the terminals are redistributed according to the method described above.
  • the perimeter of the cover is not generally connected to anything.
  • metallization 278 metallize its perimeter (metallization 278 ) if it is an insulator, or do nothing if it is conductive; the perimeter 278 will then be connected to terminals 279 of the interface 273 .
  • Two metallization layers 261 and 262 are thus provided in the example of FIG. 2C , deposited on two layers of insulating material 251 , 252 which make it possible to ground the cover via its perimeter 278 .
  • the thinning (cut B) is carried out in the thickness of the cover.
  • the interconnection method as described above is applied to the production of three-dimensional thinned heterogeneous components.
  • the method carried out in order to produce 3D components adopts the steps of the method described in French Patent Application No. 90 154 73 filed on Dec. 11, 1990 in the name of the Applicant.
  • the steps are summarized in FIG. 5
  • FIG. 6 illustrates the various steps according to one example.
  • the production ( 50 ) of the thinned heterogeneous elementary components (denoted 60 in FIG. 6 ) is carried out by the interconnection method according to the invention as described above and illustrated in FIG. 1 .
  • FIG. 2B A view in section of an example of a thinned heterogeneous elementary component thus produced is shown in FIG. 2B .
  • the elementary components have, in particular, connections 601 ( FIG. 6 ) oriented toward the periphery of the component.
  • the components are then stacked and bonded (step 51 ) on a substrate 61 .
  • the components 60 are either identical components or components having different electrical functions.
  • the substrate 61 is, for example, an adhesive film of the type described above.
  • the first component 62 bonded onto the substrate is advantageously an interconnection component, for example a printed circuit substrate, for subsequent connection of the 3D components and comprising terminals 621 positioned on the face next to the substrate which are connected to terminals 622 positioned on the opposite face.
  • the elementary components 60 are therefore stacked on this first interconnection component and bonded, for example by means of an epoxy adhesive 63 .
  • the assembly formed by the stack of elementary components 60 and the interconnection component 62 is coated (step 52 , FIG. 5 ) with a polymer material 64 (for example an epoxy resin) in order to form a block of parallelepipedal shape.
  • a polymer material 64 for example an epoxy resin
  • the faces of this block are then metallized in order to form the connections (step 54 ).
  • the method employed is advantageously a collective method.
  • On a single substrate 61 the individual heterogeneous components are stacked and bonded on one another as described above.
  • the coating material is applied on all of the support, then the structure obtained is cut (step 53 ) so as to expose the sections of all the conductors ( 601 , 622 ) arriving at the periphery for each of the levels consisting of the elementary components 60 and the interconnection component 62 .
  • the faces of this block are subsequently metallized on 4 or 5 faces (step 54 ), short-circuiting all the conductors that reach the periphery of each level.
  • An etching step for example with a laser, then makes it possible to isolate groups of said conductors in order to form the electrical interconnection layout (step 55 ).
  • FIG. 7 illustrates a view in section of an exemplary embodiment of a three-dimensional thinned heterogeneous component obtained by the method as described in FIG. 5 .
  • the thinned three-dimensional heterogeneous component comprises the interconnection component 62 with the terminals 621 for connection to the substrate onto which it will be transferred in order to be interconnected with others, and, stacked on it, the thinned heterogeneous elementary components 60 between which layers of glue 63 are arranged.
  • the metallization layer 71 short-circuiting the conductors that reach the periphery of each level is deposited on the 4 or 5 faces of the three-dimensional component, making it possible to form an interconnection network between all the various levels after etching. Shown in the example illustrated in FIG. 7 are active 21 and passive 20 , 22 components of the capacitor type and connecting wires 20 , respectively.
  • connecting wires 20 is that the various levels can be interconnected using a conductive layer 63 , such an anisotropic adhesive of the ACF (anisotropic conductive film) type, either in liquid form or in film form, which is conductive in the direction in which pressure is applied.
  • a conductive layer 63 such an anisotropic adhesive of the ACF (anisotropic conductive film) type, either in liquid form or in film form, which is conductive in the direction in which pressure is applied.
  • FIG. 8 illustrates by a diagram another exemplary embodiment of the interconnection method according to the invention for the production of thinned three-dimensional components.
  • the method substantially adopts the steps of the method described in FIG. 1 .
  • a plurality of active components are stacked on one another before depositing the polymer layer (step 12 , FIG. 1 ).
  • This embodiment of the method according to the invention is particularly beneficial in the event that the active components have thicknesses small enough to be able to be stacked with a total stack height remaining less than the height of the passive component.
  • the active components will thus not be touched during the step of heterogeneously thinning the structure, although nonselective surface treatment of the polymer layer and the passive components will be carried out making it possible to reduce the thickness of the heterogeneous component thus formed.
  • the method described here comprises the positioning and fixing of at least one passive component 80 and at least a first active component 81 on a support, the terminals of the components (respectively 801 , 811 ) being in contact with the support.
  • This step similar to one described in FIG. 2A , is not represented in FIG. 8 .
  • the flat support is, for example, an adhesive film as described above.
  • the method furthermore comprises the stacking and bonding of a second active component 82 on the first active component 81 , the terminals 821 of the second component being on the opposite face from that in contact with the first component.
  • One or more other active components 83 may optionally also be stacked on the second component, the terminals 831 of each further active component being on the opposite face from that in contact with of the lower component.
  • the number of active components which can be stacked depends on their thickness with respect to that of the passive component 80 .
  • the active components are connected in the following way.
  • one or more terminal adapters 84 are positioned and fixed on the flat support (not shown) in the same way as the passive component 80 and the first active component 81 .
  • the adapters may be of the same type as those described above ( FIG. 2C ).
  • Each adapter has two faces with metal contacts connected together, respectively denoted 841 on the face in contact with the support and 842 on the other face on the opposite side.
  • the adapters 84 may be formed by a metal grid.
  • the metal grid coated in a resin consists, for example, of a ferro-nickel alloy or copper. It is coated with nickel and gold so as to be able to receive the wiring.
  • the method comprises the formation of connections by means of wires 822 between the terminals 821 of the second component 82 and the contacts 842 of the adapter and, if appropriate, the formation of connections by connecting wires 832 between the terminals of each further component 83 and the contacts 842 of the adapter or the terminals of the lower component, here the terminals 821 of the second component 82 .
  • the subsequent steps of the method are similar to those described in the example of FIG.
  • the passive components may undergo a prior thinning step.
  • the method may furthermore be applied collectively by fixing a large number of components arranged in the form of identical patterns on the same support.
  • the reconstituted structure obtained at the end of the method will then be cut in order to obtain a corresponding number of individual heterogeneous components.

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US20090260228A1 (en) * 2007-10-26 2009-10-22 3D Plus Process for the vertical interconnection of 3d electronic modules by vias
US8159076B2 (en) 2007-06-07 2012-04-17 Commissariat A L'energie Atomique Method of producing a via in a reconstituted substrate
US8359740B2 (en) 2008-12-19 2013-01-29 3D Plus Process for the wafer-scale fabrication of electronic modules for surface mounting
US8546190B2 (en) 2009-03-10 2013-10-01 3D Plus Method for positioning chips during the production of a reconstituted wafer
US9496241B2 (en) 2012-06-15 2016-11-15 Medtronic, Inc. Integrated circuit packaging for implantable medical devices
US11213690B2 (en) 2012-06-15 2022-01-04 Medtronic, Inc. Wafer level packages of high voltage units for implantable medical devices

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FR2894070B1 (fr) * 2005-11-30 2008-04-11 3D Plus Sa Sa Module electronique 3d
FR2895568B1 (fr) * 2005-12-23 2008-02-08 3D Plus Sa Sa Procede de fabrication collective de modules electroniques 3d
AT503191B1 (de) 2006-02-02 2008-07-15 Austria Tech & System Tech Leiterplattenelement mit wenigstens einem eingebetteten bauelement sowie verfahren zum einbetten zumindest eines bauelements in einem leiterplattenelement
FR2905198B1 (fr) * 2006-08-22 2008-10-17 3D Plus Sa Sa Procede de fabrication collective de modules electroniques 3d
FR2911995B1 (fr) * 2007-01-30 2009-03-06 3D Plus Sa Sa Procede d'interconnexion de tranches electroniques
FR2917234B1 (fr) 2007-06-07 2009-11-06 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice semi-conductrice.
FR2934082B1 (fr) * 2008-07-21 2011-05-27 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice
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JP7611683B2 (ja) 2020-12-07 2025-01-10 太陽誘電株式会社 セラミック電子部品、実装基板およびセラミック電子部品の製造方法
CN112928077A (zh) * 2021-01-20 2021-06-08 上海先方半导体有限公司 一种多芯片异质集成封装单元及其制造方法、堆叠结构

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EP1642336A1 (fr) 2006-04-05

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