US7696074B2 - Method of manufacturing NAND flash memory device - Google Patents
Method of manufacturing NAND flash memory device Download PDFInfo
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- US7696074B2 US7696074B2 US11/446,475 US44647506A US7696074B2 US 7696074 B2 US7696074 B2 US 7696074B2 US 44647506 A US44647506 A US 44647506A US 7696074 B2 US7696074 B2 US 7696074B2
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 43
- 150000004767 nitrides Chemical class 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000009413 insulation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the invention relates generally to a method of manufacturing a flash memory device. More particularly, the invention relates to a method of manufacturing a NAND flash memory device.
- FIGS. 1A and 1B illustrate a gate formation process of a select transistor region, which is formed using the same process when a cell gate is formed in a cell region.
- a tunnel oxide film 102 , a first polysilicon film 103 , a dielectric film 104 , a second polysilicon film 105 , a tungsten film 106 , and a hard mask film 107 are sequentially formed on a semiconductor substrate 101 , thereby forming a gate electrode in which a floating gate and a control gate are stacked and form a gate electrode having the same stack structure as that of the gate electrode in a select transistor region.
- an oxidization process is performed to form an oxide film 108 on the gate sidewalls (preferably, the sidewalls of the first and second polysilicon films 103 , 105 ).
- An ion implantation process is carried out to form a junction unit 109 serving as the source and drain.
- a first buffer oxide film 110 is formed on the entire structure, a nitride film 111 is formed.
- a blanket etch process is then performed to form spacers on the gate sidewalls.
- an insulating film 114 is formed in order to provide insulation between gate lines and insulation with an upper line.
- regions of the insulating film 114 , the SAC nitride film 113 , and the second buffer oxide film 112 are etched using a SAC etch process, forming a contact through which the junction unit 109 is exposed.
- a conductive film 115 is formed to bury the contact, thereby forming a contact plug.
- the thickness of the hard mask film 107 gradually decreases. Furthermore, since the first buffer oxide film 110 is removed during the SAC etch process, the conductive film 115 is connected to the tungsten film 106 . Accordingly, since the gate electrode and the contact plug may create a short circuit, the device may fail.
- the invention provides a method of manufacturing a NAND flash memory device; which method can prevent a problem in which a gate and a contact plug create a short circuit due to the removal of a buffer oxide film on the sidewalls of the gate in the process of exposing a junction region of a select transistor through a self-aligned contact (SAC) process and forming the contact plug.
- SAC self-aligned contact
- the invention provides a method of manufacturing a NAND flash memory device, which method can solve the above-mentioned problem by removing the buffer oxide film formed at one side of the select transistor gate before the SAC process.
- one embodiment of the invention provides a method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; stripping the buffer oxide film at one side of the gates; forming a nitride film spacers over the sidewalls of the gates; forming a self-aligned contact process (SAC) nitride film and an insulating film over the entire structure; etching regions of the insulating film and the SAC nitride film to form a contact through which the junction region is exposed; and forming a conductive film to bury the contact, thereby forming a contact plug.
- SAC self-aligned contact process
- the buffer oxide film may preferably be formed to a thickness of about 50 ⁇ about to 700 ⁇ .
- the buffer oxide film may be etched to about 10 ⁇ to about 50 ⁇ in thickness.
- the invention provides a method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; forming a nitride film spacers on sidewalls of the gates; stripping the buffer oxide film between the gates and the nitride film spacers under an oxide film over-etch condition; forming a nitride film at the portion from which the buffer oxide film has been stripped; forming a self-aligned contact process (SAC) nitride film and an insulating film on the entire structure; etching regions of the insulating film and the SAC nitride film to form a contact through which the junction region is exposed; and forming a conductive film to bury the contact, thereby forming a contact plug.
- SAC self-aligned contact process
- a removal target of the oxide film is set to about 500 ⁇ to about 1000 ⁇ .
- the nitride film may preferably be formed to a thickness of about 50 ⁇ to about 100 ⁇ using a low-pressure chemical vapor deposition (LPCVD) method.
- LPCVD low-pressure chemical vapor deposition
- FIGS. 1A and 1B are cross-sectional views illustrating a method of manufacturing a NAND flash memory device in the related art.
- FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the invention.
- FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the invention.
- FIGS. 2A to 2D are cross-sectional views of gates of a select transistor region that is formed using the same process when a cell gate is formed in a cell region.
- a tunnel oxide film 202 , a first polysilicon film 203 , a dielectric film 204 , a second polysilicon film 205 , a tungsten film 206 , and a hard mask film 207 are sequentially formed on a semiconductor substrate 201 , thereby forming a gate electrode in which a floating gate and a control gate are stacked and also forming a gate electrode having the same stack structure as that of the gate electrode in a select transistor region.
- an oxidization process is performed to form an oxide film 208 on the gate sidewalls (preferably, the sidewalls of the first and second polysilicon films 203 , 205 ).
- a first buffer oxide film 210 is formed on the entire structure.
- the first buffer oxide film 210 may be formed to a thickness of about 50 ⁇ to about 700 ⁇ .
- a photoresist film 211 is formed on the entire structure and is then patterned using a mask through which the select transistor region is exposed. Thereafter, the oxide film 208 and the first buffer oxide film 210 formed on the gate sidewalls of the select transistor region are stripped using the patterned photoresist film 211 as a mask.
- the etch process for stripping the first buffer oxide film 210 may be performed using a wet etch or dry etch process so that the oxide film remains about 10 ⁇ to about 50 ⁇ in thickness.
- a nitride film 212 is formed on the entire structure.
- a blanket etch process is then performed to form spacers on the gate sidewalls.
- a second buffer oxide film 213 and a SAC nitride film 214 are formed on the entire structure.
- An insulating film 215 for providing insulation between gate lines and insulation with an upper line is then formed.
- regions of the insulating film 215 , the SAC nitride film 214 , and the second buffer oxide film 213 are etched using a SAC etch process, forming a contact through which the junction unit 209 is exposed.
- a conductive film 216 is formed to bury the contact, thereby forming a contact plug.
- wet over-etch in which a removal target of the oxide film is set to about 500 ⁇ to about 1000 ⁇ may be performed to remove the first buffer oxide film between the gate and the nitride film spacers.
- a nitride film having a thickness of about 50 ⁇ to about 100 ⁇ is formed at the portion from which the first buffer oxide film has been removed by means of a LPCVD method.
- the buffer oxide film formed at one side of the gate is stripped by the SAC process before the junction region of the select transistor region is exposed. It is therefore possible to solve the problem in which the contact plug and the gate creates a short circuit. Accordingly, the invention is advantageous in that it can sufficiently secure SAC process margin and can improve the reliability of devices.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
A method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; stripping the buffer oxide film at one side of the gates; forming a nitride film spacers over the sidewalls of the gates; forming a self-aligned contact process (SAC) nitride film and an insulating film over the entire structure; etching regions of the insulating film and the SAC nitride film to form a contact through which the junction region is exposed; and forming a conductive film to bury the contact, thereby forming a contact plug.
Description
1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory device. More particularly, the invention relates to a method of manufacturing a NAND flash memory device.
2. Discussion of Related Art
A method of manufacturing a NAND flash memory device in the related art is described below with reference to FIGS. 1A and 1B , which illustrate a gate formation process of a select transistor region, which is formed using the same process when a cell gate is formed in a cell region.
Referring to FIG. 1A , a tunnel oxide film 102, a first polysilicon film 103, a dielectric film 104, a second polysilicon film 105, a tungsten film 106, and a hard mask film 107 are sequentially formed on a semiconductor substrate 101, thereby forming a gate electrode in which a floating gate and a control gate are stacked and form a gate electrode having the same stack structure as that of the gate electrode in a select transistor region.
Thereafter, to remove micro trenches and plasma damage occurring upon etching of the gate, an oxidization process is performed to form an oxide film 108 on the gate sidewalls (preferably, the sidewalls of the first and second polysilicon films 103, 105).
An ion implantation process is carried out to form a junction unit 109 serving as the source and drain. After a first buffer oxide film 110 is formed on the entire structure, a nitride film 111 is formed. A blanket etch process is then performed to form spacers on the gate sidewalls.
Referring to FIG. 1B , after a second buffer oxide film 112 and a SAC nitride film 113 are formed on the entire structure, an insulating film 114 is formed in order to provide insulation between gate lines and insulation with an upper line.
Thereafter, regions of the insulating film 114, the SAC nitride film 113, and the second buffer oxide film 112 are etched using a SAC etch process, forming a contact through which the junction unit 109 is exposed. A conductive film 115 is formed to bury the contact, thereby forming a contact plug.
However, as devices become more highly integrated, the thickness of the hard mask film 107 gradually decreases. Furthermore, since the first buffer oxide film 110 is removed during the SAC etch process, the conductive film 115 is connected to the tungsten film 106. Accordingly, since the gate electrode and the contact plug may create a short circuit, the device may fail.
In one embodiment, the invention provides a method of manufacturing a NAND flash memory device; which method can prevent a problem in which a gate and a contact plug create a short circuit due to the removal of a buffer oxide film on the sidewalls of the gate in the process of exposing a junction region of a select transistor through a self-aligned contact (SAC) process and forming the contact plug.
In another embodiment, the invention provides a method of manufacturing a NAND flash memory device, which method can solve the above-mentioned problem by removing the buffer oxide film formed at one side of the select transistor gate before the SAC process.
Accordingly, one embodiment of the invention provides a method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; stripping the buffer oxide film at one side of the gates; forming a nitride film spacers over the sidewalls of the gates; forming a self-aligned contact process (SAC) nitride film and an insulating film over the entire structure; etching regions of the insulating film and the SAC nitride film to form a contact through which the junction region is exposed; and forming a conductive film to bury the contact, thereby forming a contact plug.
The buffer oxide film may preferably be formed to a thickness of about 50 Å about to 700 Å. The buffer oxide film may be etched to about 10 Å to about 50 Å in thickness.
According to another embodiment, the invention provides a method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; forming a nitride film spacers on sidewalls of the gates; stripping the buffer oxide film between the gates and the nitride film spacers under an oxide film over-etch condition; forming a nitride film at the portion from which the buffer oxide film has been stripped; forming a self-aligned contact process (SAC) nitride film and an insulating film on the entire structure; etching regions of the insulating film and the SAC nitride film to form a contact through which the junction region is exposed; and forming a conductive film to bury the contact, thereby forming a contact plug.
Preferably, in an oxide film over-etch process, a removal target of the oxide film is set to about 500 Å to about 1000 Å. The nitride film may preferably be formed to a thickness of about 50 Å to about 100 Å using a low-pressure chemical vapor deposition (LPCVD) method.
A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
The invention is described in detail in connection with certain exemplary embodiments with reference to the accompanying drawings.
Referring to FIG. 2A , a tunnel oxide film 202, a first polysilicon film 203, a dielectric film 204, a second polysilicon film 205, a tungsten film 206, and a hard mask film 207 are sequentially formed on a semiconductor substrate 201, thereby forming a gate electrode in which a floating gate and a control gate are stacked and also forming a gate electrode having the same stack structure as that of the gate electrode in a select transistor region.
Thereafter, to remove micro trenches and plasma damage occurring upon etching of the gate, an oxidization process is performed to form an oxide film 208 on the gate sidewalls (preferably, the sidewalls of the first and second polysilicon films 203, 205).
An ion implantation process is carried out to form a junction unit 209 serving as the source and drain. A first buffer oxide film 210 is formed on the entire structure. The first buffer oxide film 210 may be formed to a thickness of about 50 Å to about 700 Å.
Referring to FIG. 2B , a photoresist film 211 is formed on the entire structure and is then patterned using a mask through which the select transistor region is exposed. Thereafter, the oxide film 208 and the first buffer oxide film 210 formed on the gate sidewalls of the select transistor region are stripped using the patterned photoresist film 211 as a mask.
The etch process for stripping the first buffer oxide film 210 may be performed using a wet etch or dry etch process so that the oxide film remains about 10 Å to about 50 Å in thickness.
Referring to FIG. 2C , after the photoresist film 211 is stripped, a nitride film 212 is formed on the entire structure. A blanket etch process is then performed to form spacers on the gate sidewalls. A second buffer oxide film 213 and a SAC nitride film 214 are formed on the entire structure. An insulating film 215 for providing insulation between gate lines and insulation with an upper line is then formed.
Referring to FIG. 2D , regions of the insulating film 215, the SAC nitride film 214, and the second buffer oxide film 213 are etched using a SAC etch process, forming a contact through which the junction unit 209 is exposed. A conductive film 216 is formed to bury the contact, thereby forming a contact plug.
Meanwhile, according to another embodiment of the invention, after the nitride film spacers are formed on the gate sidewalls, wet over-etch in which a removal target of the oxide film is set to about 500 Å to about 1000 Å may be performed to remove the first buffer oxide film between the gate and the nitride film spacers. A nitride film having a thickness of about 50 Å to about 100 Å is formed at the portion from which the first buffer oxide film has been removed by means of a LPCVD method. Subsequent processes, such as a second buffer oxide film formation process and a SAC nitride film formation process, are then performed.
As described above, according to the invention, the buffer oxide film formed at one side of the gate is stripped by the SAC process before the junction region of the select transistor region is exposed. It is therefore possible to solve the problem in which the contact plug and the gate creates a short circuit. Accordingly, the invention is advantageous in that it can sufficiently secure SAC process margin and can improve the reliability of devices.
While the invention has been described in connection with practical exemplary embodiments, the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (9)
1. A method of manufacturing a NAND flash memory device, the method comprising:
forming first and second gates over a semiconductor substrate, each of the first and second gates including first and second sidewalls, wherein the first sidewall of the first gate is opposed to the second sidewall of the second gate;
forming a junction region in the semiconductor substrate between the first and second gates;
forming a buffer oxide film on the first and second gates and the semiconductor substrate;
stripping the buffer oxide film at the first sidewall of the first gate and at the second sidewall of the second gate;
forming nitride film spacers over each of the first sidewall of the first gate, the second sidewall of the second gate, and the buffer oxide film remaining on the second sidewall of the first gate and the first sidewall of the second gate;
forming a self-aligned contact process (SAC) nitride film and an insulating film over the nitride film spacers;
etching the insulating film and the SAC nitride film between the first and the second gates to expose the junction region, thereby forming a contact hole; and
forming a conductive film over the insulating film including the contact hole,
wherein the nitride film spacers are formed after stripping the buffer oxide film at the first sidewall of the first gate and at the second sidewall of the second gate.
2. The method of claim 1 , wherein the buffer oxide film is formed to a thickness of about 50 Å to about 700 Å.
3. The method of claim 1 , wherein the buffer oxide film remains to a thickness of about 10 Å to about 50 Å after stripping the buffer oxide film.
4. The method of claim 1 , wherein the first and the second gates are formed of a tunnel insulating layer, floating gate layer, a dielectric layer, and the control gate layer.
5. The method of claim 1 , wherein the buffer oxide film is stripped by wet etching process.
6. A method of manufacturing a NAND flash memory device, the method comprising:
forming gates over a semiconductor substrate;
forming a junction region in the semiconductor substrate between the gates;
forming a buffer oxide film on the gates and the semiconductor substrate;
forming nitride film spacers on sidewalls of the gates;
stripping the buffer oxide film between the gate and the nitride film spacer under an oxide film over-etch condition;
forming a nitride film at the portion from which the buffer oxide film has been stripped;
forming a self-aligned contact process (SAC) nitride film and an insulating film on the entire structure after forming the nitride film;
etching the insulating film and the SAC nitride film between the gate to expose the junction region, thereby forming a contact hole; and
forming a conductive film over the insulating film including the contact hole.
7. The method of claim 6 , wherein the oxide film over-etch condition includes a removal target of the oxide film of about 500 Å to about 1000 Å.
8. The method of claim 6 , wherein the nitride film is formed to a thickness of about 50 Å to about 100 Å using a low-pressure chemical vapor deposition method.
9. The method of claim 6 , wherein the gates are formed of a tunnel insulating layer, floating gate layer, a dielectric layer, and the control gate layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2005-0096913 | 2005-10-14 | ||
| KR1020050096913A KR100739962B1 (en) | 2005-10-14 | 2005-10-14 | Manufacturing method of NAND-type flash memory device |
| KR2005-96913 | 2005-10-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20070087538A1 US20070087538A1 (en) | 2007-04-19 |
| US7696074B2 true US7696074B2 (en) | 2010-04-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/446,475 Expired - Fee Related US7696074B2 (en) | 2005-10-14 | 2006-06-02 | Method of manufacturing NAND flash memory device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7696074B2 (en) |
| JP (1) | JP5063030B2 (en) |
| KR (1) | KR100739962B1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100976684B1 (en) * | 2008-08-01 | 2010-08-18 | 주식회사 하이닉스반도체 | Contact hole formation method of semiconductor memory device |
| JP2010141281A (en) * | 2008-11-11 | 2010-06-24 | Renesas Technology Corp | Semiconductor device and method of manufacturing the same |
| US11903181B2 (en) | 2021-06-23 | 2024-02-13 | Fujian Jinhua Integrated Circuit Co., Ltd. | Semiconductor structure and method for forming the same |
| US20220415895A1 (en) * | 2021-06-23 | 2022-12-29 | Fujian Jinhua Integrated Circuit Co., Ltd. | Semiconductor structure and method for forming the same |
| CN118524704A (en) * | 2021-06-23 | 2024-08-20 | 福建省晋华集成电路有限公司 | Semiconductor structure |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010065285A (en) | 1999-12-29 | 2001-07-11 | 박종섭 | Method of manufacturing a flash memory cell |
| US6306760B1 (en) | 1999-12-09 | 2001-10-23 | United Microelectronics Corp. | Method of forming a self-aligned contact hole on a semiconductor wafer |
| KR20030002711A (en) | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method for manufacturing a flash memory cell |
| KR20040071527A (en) | 2003-02-06 | 2004-08-12 | 삼성전자주식회사 | Method of fabricating a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit fabricated thereby |
| KR20040074389A (en) | 2003-02-18 | 2004-08-25 | 주식회사 하이닉스반도체 | Method of manufacturing flash memory device |
| KR20040105949A (en) | 2003-06-10 | 2004-12-17 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
| US20050142729A1 (en) * | 2003-12-30 | 2005-06-30 | Hyunsoo Shin | Methods for forming a field effect transistor |
| KR20060075364A (en) | 2004-12-28 | 2006-07-04 | 주식회사 하이닉스반도체 | Manufacturing Method of Flash Memory Device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003297944A (en) * | 2002-04-04 | 2003-10-17 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
| JP2006041023A (en) * | 2004-07-23 | 2006-02-09 | Toshiba Corp | Semiconductor apparatus and manufacturing method thereof |
-
2005
- 2005-10-14 KR KR1020050096913A patent/KR100739962B1/en not_active Expired - Fee Related
-
2006
- 2006-05-16 JP JP2006136163A patent/JP5063030B2/en not_active Expired - Fee Related
- 2006-06-02 US US11/446,475 patent/US7696074B2/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306760B1 (en) | 1999-12-09 | 2001-10-23 | United Microelectronics Corp. | Method of forming a self-aligned contact hole on a semiconductor wafer |
| KR20010065285A (en) | 1999-12-29 | 2001-07-11 | 박종섭 | Method of manufacturing a flash memory cell |
| KR20030002711A (en) | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method for manufacturing a flash memory cell |
| KR20040071527A (en) | 2003-02-06 | 2004-08-12 | 삼성전자주식회사 | Method of fabricating a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit fabricated thereby |
| KR20040074389A (en) | 2003-02-18 | 2004-08-25 | 주식회사 하이닉스반도체 | Method of manufacturing flash memory device |
| KR20040105949A (en) | 2003-06-10 | 2004-12-17 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
| US20050142729A1 (en) * | 2003-12-30 | 2005-06-30 | Hyunsoo Shin | Methods for forming a field effect transistor |
| KR20060075364A (en) | 2004-12-28 | 2006-07-04 | 주식회사 하이닉스반도체 | Manufacturing Method of Flash Memory Device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20070041118A (en) | 2007-04-18 |
| JP2007110072A (en) | 2007-04-26 |
| JP5063030B2 (en) | 2012-10-31 |
| US20070087538A1 (en) | 2007-04-19 |
| KR100739962B1 (en) | 2007-07-16 |
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