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US7365009B2 - Structure of metal interconnect and fabrication method thereof - Google Patents

Structure of metal interconnect and fabrication method thereof Download PDF

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Publication number
US7365009B2
US7365009B2 US11/306,590 US30659006A US7365009B2 US 7365009 B2 US7365009 B2 US 7365009B2 US 30659006 A US30659006 A US 30659006A US 7365009 B2 US7365009 B2 US 7365009B2
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layer
hard mask
electric conductor
dielectric layer
patterned hard
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US20070155157A1 (en
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Pei-Yu Chou
Chun-jen Huang
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Marlin Semiconductor Ltd
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOU, PEI-YU, HUANG, CHUN-JEN
Priority to US11/748,472 priority patent/US7524742B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

Definitions

  • the present invention relates to a fabrication method and structure of metal interconnect, and more particularly, to a method and structure of metal interconnect using a hard mask as an etching mask and etch stop layer.
  • the miniaturization of semiconductor devices has achieved nanometer scale as the line width of ICs becomes smaller and smaller.
  • the integration of a single chip i.e. density of semiconductor devices on a single chip, becomes bigger, it means the interval between devices becomes smaller. This presents difficulties when attempting to form contact holes and metal interconnect.
  • FIGS. 1-11 are schematic, cross-sectional diagrams showing the process of forming contact holes and metal interconnect in accordance with a prior art method.
  • a metal-oxide-semiconductor (MOS) transistor device 20 is formed on a semiconductor substrate 10 .
  • the MOS transistor device 20 which is isolated by shallow trench isolations (STIs) 24 , includes source/drain regions 12 , a gate electrode 14 , and a spacer structure 16 disposed on the sidewalls of the gate electrode 14 .
  • STIs shallow trench isolations
  • the semiconductor substrate 10 further includes a contact etch stop layer (CESL) 32 deposited over the MOS transistor device 20 and the semiconductor substrate 10 , and a first dielectric layer 34 deposited on the contact etch stop layer 32 .
  • a bottom anti-reflective coating (BARC) layer 36 is deposited on the first dielectric layer 34 .
  • a photoresist layer 40 is formed on the BARC layer 36 , and a conventional exposure-and-development process is carried out to form openings 42 in the photoresist layer 40 to define the locations of contact holes to be formed later.
  • the photoresist layer 40 is used as an etching mask to etch the exposed BARC layer 36 and the first dielectric layer 34 through the openings 42 so as to form openings 44 .
  • the etching of the first dielectric layer 34 stops on the contact etch stop layer 32 .
  • the remaining photoresist layer 40 and the BARC layer 36 are used as an etching hard mask to etch the exposed contact etch stop layer 32 through the openings 44 , thereby forming contact holes 46 .
  • the remaining photoresist layer 40 and the BARC layer 36 over the first dielectric layer 34 are removed.
  • a diffusion barrier layer 47 such as titanium nitride (TiN)/titanium (Ti), is required to be deposited over sidewalls of every contact hole 46 and upon gate electrode 14 and source/drain regions 12 in the bottom. Then, every contact hole 46 is filled with metal 48 , such as tungsten (W), and the surface diffusion barrier layer 47 is covered with metal 48 , such as tungsten (W), as shown in FIG. 6 . Afterward as shown in FIG. 7 , a first chemical mechanical polishing (CMP) process is proceeded to remove redundant metal 48 upon surface of the first dielectric layer 34 in order to form the required contact plug 49 .
  • CMP chemical mechanical polishing
  • an etch stop layer 50 , a second dielectric layer 52 , and a patterned photoresist layer 54 are deposited upon first dielectric layer 34 and contact plug 49 in sequence.
  • the patterned photoresist layer 54 is used to as an etching mask to etch part of the second dielectric layer 52 and etch stop layer 50 to form a trench 56 , as shown in FIG. 9 .
  • a standard copper process is carried out to deposit a diffusion barrier layer of titanium nitride (TiN)/titanium (Ti) (not shown) and a seed layer (not shown) over sidewalls of every trench 56 and upon the second dielectric layer 52 and every contact plug 49 , and then electroplating is performed to form copper metal 58 , as shown in FIG. 10 .
  • a second CMP process is carried out to remove redundant copper metal 58 upon the surface of second dielectric layer 52 , and then metal wires 60 electrically connecting every contact plug 49 are formed separately, as shown in FIG. 11 .
  • a semiconductor contact hole process only use a photoresist pattern as an etching mask.
  • AEI CD after-etch-inspection critical dimension
  • the present invention provides a fabrication method and structure of metal interconnect.
  • the method includes:
  • the first patterned hard mask as an etching mask to etch the first dielectric layer to form the first opening in the first dielectric layer
  • the structure includes:
  • a first dielectric layer positioned on the substrate and covering the first electric conductor
  • the present invention transfers the pattern of a patterned photoresist layer to a hard mask layer first, and then uses the patterned hard mask as an etching mask to etch a first dielectric layer to form contact holes. Therefore, AEI CD can be made be smaller than ADI CD.
  • the patterned hard mask of the present invention can be an etching mask of contact holes, a stop layer of a CMP process for contact plugs, and an etch stop layer of a trench in a metal interconnect process.
  • the present invention uses SiC or SiCN made in low temperature as a patterned hard mask, and therefore a phase variation of NiSi positioned upon a gate electrode and source/drain regions can be avoided effectively.
  • FIGS. 1-11 are schematic, cross-sectional diagrams showing a process of fabricating a metal interconnect structure in accordance with the prior art.
  • FIGS. 12-20 are schematic, cross-sectional diagrams illustrating a method of fabricating a metal interconnect structure in accordance with a preferred embodiment of the present invention.
  • FIGS. 12-20 are schematic, cross-sectional diagrams illustrating a method of fabricating a metal interconnect structure in accordance with a preferred embodiment of the present invention.
  • a semiconductor substrate 62 such as wafer or SOI is provided, and at least one MOS transistor device 72 is formed on the semiconductor substrate 62 .
  • the MOS transistor device 72 which is isolated by shallow trench isolations 74 , includes source/drain regions 64 , a gate electrode 66 , and a spacer structure 68 disposed on the sidewalls of the gate electrode 66 .
  • the MOS transistor device 72 may further includes silicides 70 disposed on the surface of the gate electrode 66 and the source/drain regions 64 .
  • the material of the silicides 70 can be NiSi formed by a salicide process.
  • the semiconductor substrate 62 further includes a contact etch stop layer 76 deposited over the MOS transistor device 72 and the semiconductor substrate 62 , and a first dielectric layer 78 deposited on the contact etch stop layer 76 .
  • the first dielectric layer 78 may include tetraethylorthosilicate (TEOS) oxide, un-doped silicon glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), FSG, PSG or BSG.
  • TEOS tetraethylorthosilicate
  • BPSG borophosphosilicate glass
  • FSG FSG
  • PSG PSG
  • BSG borophosphosilicate glass
  • CVD chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • the contact etch stop layer 76 may include material with high stress, such as SiN, or other materials having high etching selectivity with the first dielectric layer 78 .
  • a hard mask layer 80 , a first BARC layer 82 , and a patterned photoresist layer 84 are formed upon the first dielectric layer 78 in sequence.
  • the patterned photoresist layer 84 has a plurality of openings 86 .
  • the openings 86 are disposed corresponding to the gate electrode 66 and the source/drain regions 64 so as to define the locations of contact holes.
  • material of the hard mask layer 80 is composed of a chemical compound of silicon with carbon or nitrogen, such as SiC or SiCN, that can be made at low temperature because when choosing material of the hard mask layer 80 , the forming temperature of the hard mask layer 80 is required to be under 400° C. in order to avoid phase variation of NiSi upon the gate electrode 66 and the source/drain regions 64 .
  • the first BARC layer 82 can be SiON.
  • an anisotropic etching process is performed by using the patterned photoresist layer 84 as an etching mask to etch the first BARC layer 82 and the hard mask layer 80 through the openings 86 to transfer the pattern of the patterned photoresist layer 84 to the hard mask layer 80 in order to form a first patterned hard mask 81 , as shown in FIG. 13 .
  • the ADI CD 88 of the patterned photoresist layer 84 is larger than the AEI CD 90 of the first patterned hard mask 81 in the present invention, and a semiconductor process under 45 nm can be accomplished.
  • the present invention uses the first patterned hard mask 81 as an etching mask to etch the first dielectric layer 78 and the contact etch stop layer 76 to form a plurality of openings as contact holes 92 in the first dielectric layer 78 and the contact etch stop layer 76 .
  • a cleaning process is performed to remove polymer residues or particles remaining in the sidewalls of the contact holes 92 .
  • the cleaning process can be a wet clean process or a dry clean process, and can be performed in-situ or ex-situ.
  • a diffusion barrier 94 is formed on the first patterned hard mask 81 and the sidewalls of the contact holes 92 .
  • the diffusion barrier 94 is a composite metal layer such as titanium nitride (TiN)/titanium (Ti) or tantalum nitride (TaN)/tantalum (Ta) in order to avoid metal atom diffusion damaging the device character, and to increase adhesion between metal and the first dielectric layer 78 .
  • TiN titanium nitride
  • TaN tantalum nitride
  • Ta tantalum nitride
  • Ta tantalum nitride
  • Ta tantalum nitride
  • Ta tantalum nitride
  • Ta tantalum nitride
  • Ta tantalum nitride
  • Ta tantalum nitride
  • Ta tantalum nitride
  • Ta tantalum nitride
  • Ta tantalum nitride
  • Ta tant
  • the contact holes 92 are filled with the first metal layer 98 , such as tungsten (W), and the surface diffusion barrier layer 94 is covered with the first metal layer 98 to electrically connect the gate electrode 66 and the source/drain regions 64 .
  • the first patterned hard mask 81 is used as a stop layer to in a first CMP process on the first metal layer 98 and the diffusion barrier 94 in order to form every contact plug 100 in the first dielectric layer 78 , as shown in FIG. 16 .
  • a second dielectric layer 102 , a second BARC layer 104 , and a second patterned hard mask layer 106 are formed upon the first hard mask layer 81 and every contact plug 100 in sequence.
  • the second patterned hard mask layer 106 has a plurality of openings 108 .
  • the openings 108 are disposed corresponding to every contact plug 100 electrically connecting the gate electrode 66 and the source/drain regions 64 so as to define the locations of trenches 110 .
  • second patterned hard mask layer 106 is used as an etching mask, the first hard mask layer 81 and the surface of contact plugs 100 are used as an etch stop layer to etch the second BARC layer 104 and the second dielectric layer 102 to form trenches 110 in the second BARC layer 104 and the second dielectric layer 102 , and the second patterned hard mask layer 106 and the second BARC layer 104 are removed, as shown in FIG. 18 .
  • the second dielectric layer 102 may include tetraethylorthosilicate (TEOS) oxide, un-doped silicon glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), FSG, PSG or BSG. Spin coating or CVD, such as a PECVD method, or other deposition techniques may be used to deposit the second dielectric layer.
  • the second patterned hard mask layer 106 is made of photoresist material.
  • a standard copper process or other low-resistance conductor process is carried out to deposit a diffusion barrier layer of TiN/Ti or TaN/Ta (not shown) and a seed layer (not shown) over sidewalls of every trench 110 , upon the second dielectric layer 102 , and every contact plug 100 .
  • electroplating is performed to form a second metal layer 112 to fill the trench 110 , as is well known.
  • the second dielectric layer 102 is used as a stop layer in a second CMP process on the second metal layer 112 and the diffusion barrier (not shown) in order to form every metal wire 114 electrically connected to every contact plug 100 separately, as shown in FIG. 20 .
  • the present invention also discloses a metal interconnect structure.
  • the metal interconnect structure of the present invention is positioned on a semiconductor substrate 62 , and at least a first electric conductor, such as a MOS transistor device 72 comprising a gate electrode 66 , source/drain regions 64 , and a spacer structure 68 , is positioned on the semiconductor substrate 62 .
  • a first electric conductor such as a MOS transistor device 72 comprising a gate electrode 66 , source/drain regions 64 , and a spacer structure 68 .
  • the metal interconnect structure comprises a first dielectric layer 78 positioned on the substrate and covering the first electric conductor, a first patterned hard mask 81 positioned on the first dielectric layer 78 , contact plugs 100 positioned in the first patterned hard mask 81 and the first dielectric layer 78 and electrically connected with the first electric conductor, a second dielectric layer 102 positioned on the first patterned hard mask 81 and the contact plugs 100 , and metal wires 114 positioned in the second dielectric layer 102 and over the first patterned hard mask 81 and electrically connected with the contact plugs 100 .
  • the materials of each film layer and conductor are disclosed in the embodiment of FIG. 12-20 , and are not redundantly described here.
  • the present invention uses the patterned photoresist layer 84 as an etching mask to etch the hard mask layer 80 and transfer a pattern of the patterned photoresist layer 84 to the hard mask layer 80 first to form the first patterned hard mask 81 , and then uses the first patterned hard mask 81 as an etching mask to etch the first dielectric layer 78 to form the contact holes 92 . Therefore, a etch program can be used to control a critical dimension of the pattern on the first patterned hard mask 81 to make AEI CD smaller than ADI CD.
  • the first patterned hard mask 81 of the present invention can be an etching mask of contact holes 92 , a stop layer of a CMP process for contact plugs 100 , and an etch stop layer of the trench 100 in a follow-up metal interconnect process.
  • the present invention uses SiC or SiCN made at low temperature as the hard mask layer 80 .
  • the forming temperature of the hard mask layer 80 is under 400° C., and therefore phase variation of NiSi positioned upon gate electrode 66 and source/drain regions 64 can be avoided.

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Abstract

A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method and structure of metal interconnect, and more particularly, to a method and structure of metal interconnect using a hard mask as an etching mask and etch stop layer.
2. Description of the Prior Art
The miniaturization of semiconductor devices has achieved nanometer scale as the line width of ICs becomes smaller and smaller. When the integration of a single chip, i.e. density of semiconductor devices on a single chip, becomes bigger, it means the interval between devices becomes smaller. This presents difficulties when attempting to form contact holes and metal interconnect.
Please refer to FIGS. 1-11. FIGS. 1-11 are schematic, cross-sectional diagrams showing the process of forming contact holes and metal interconnect in accordance with a prior art method. As shown in FIG. 1, a metal-oxide-semiconductor (MOS) transistor device 20 is formed on a semiconductor substrate 10. The MOS transistor device 20, which is isolated by shallow trench isolations (STIs) 24, includes source/drain regions 12, a gate electrode 14, and a spacer structure 16 disposed on the sidewalls of the gate electrode 14. The semiconductor substrate 10 further includes a contact etch stop layer (CESL) 32 deposited over the MOS transistor device 20 and the semiconductor substrate 10, and a first dielectric layer 34 deposited on the contact etch stop layer 32. Subsequently, a bottom anti-reflective coating (BARC) layer 36 is deposited on the first dielectric layer 34. Then, a photoresist layer 40 is formed on the BARC layer 36, and a conventional exposure-and-development process is carried out to form openings 42 in the photoresist layer 40 to define the locations of contact holes to be formed later.
As shown in FIG. 2, the photoresist layer 40 is used as an etching mask to etch the exposed BARC layer 36 and the first dielectric layer 34 through the openings 42 so as to form openings 44. The etching of the first dielectric layer 34 stops on the contact etch stop layer 32. Subsequently, as shown in FIG. 3, the remaining photoresist layer 40 and the BARC layer 36 are used as an etching hard mask to etch the exposed contact etch stop layer 32 through the openings 44, thereby forming contact holes 46. As shown in FIG. 4, the remaining photoresist layer 40 and the BARC layer 36 over the first dielectric layer 34 are removed.
As shown in FIG. 5, in order to increase adhesion between metal and the first dielectric layer 34, and prevent silicide spiking and electromigration when filling contact hole 46 with metal, a diffusion barrier layer 47, such as titanium nitride (TiN)/titanium (Ti), is required to be deposited over sidewalls of every contact hole 46 and upon gate electrode 14 and source/drain regions 12 in the bottom. Then, every contact hole 46 is filled with metal 48, such as tungsten (W), and the surface diffusion barrier layer 47 is covered with metal 48, such as tungsten (W), as shown in FIG. 6. Afterward as shown in FIG. 7, a first chemical mechanical polishing (CMP) process is proceeded to remove redundant metal 48 upon surface of the first dielectric layer 34 in order to form the required contact plug 49.
As shown in FIG. 8, an etch stop layer 50, a second dielectric layer 52, and a patterned photoresist layer 54 are deposited upon first dielectric layer 34 and contact plug 49 in sequence. The patterned photoresist layer 54 is used to as an etching mask to etch part of the second dielectric layer 52 and etch stop layer 50 to form a trench 56, as shown in FIG. 9. Subsequently, a standard copper process is carried out to deposit a diffusion barrier layer of titanium nitride (TiN)/titanium (Ti) (not shown) and a seed layer (not shown) over sidewalls of every trench 56 and upon the second dielectric layer 52 and every contact plug 49, and then electroplating is performed to form copper metal 58, as shown in FIG. 10. Finally, a second CMP process is carried out to remove redundant copper metal 58 upon the surface of second dielectric layer 52, and then metal wires 60 electrically connecting every contact plug 49 are formed separately, as shown in FIG. 11.
As mentioned above, a semiconductor contact hole process only use a photoresist pattern as an etching mask. There are more and more optical limitations of 193 nm photoresist in the lithography process, as semiconductor devices require smaller after-etch-inspection critical dimension (AEI CD) of contact holes. Therefore, in the prior art standard 65 nm contact hole process, photoresist thickness has to be lowered to 2800 angstroms in order to fabricate 65 nm contact holes in the lithography process; and in the 45 nm contact hole process, photoresist thickness has to be lowered to 2200 angstroms in the lithography process. However, excessively thin photoresist can cause boundary defects due to insufficient shielding in the etching process, so hard masks are required to be used in the etching process. Ordinary poly-silicon hard masks are not able to be used in 45 nm processes because phase variation of silicide, such as NiSi, can result.
In addition, The above-described prior art method of forming metal interconnect has another drawback: an etch stop layer is required to be deposited before forming a trench.
SUMMARY OF THE INVENTION
It is therefore one of the objects of the claimed invention to provide a method and structure of metal interconnect using a hard mask as an etching mask and an etch stop layer to overcome the aforementioned problems.
According to claims disclosed in the present invention, the present invention provides a fabrication method and structure of metal interconnect. The method includes:
providing a substrate and at least a first electric conductor;
forming a first dielectric layer over the first electric conductor on the substrate;
forming a first patterned hard mask on the first dielectric layer to define at least a first opening;
using the first patterned hard mask as an etching mask to etch the first dielectric layer to form the first opening in the first dielectric layer;
forming a second electric conductor in the first opening and electrically connecting the second electric conductor to the first electric conductor;
forming a second dielectric layer over the first patterned hard mask and the second electric conductor;
forming a second patterned hard mask on the second dielectric layer to define at least a second opening;
using the second patterned hard mask as an etching mask and using the first patterned hard mask and the second electric conductor surface as an etch stop layer to etch the second dielectric layer to form the second opening in the second dielectric layer; and
forming a third electric conductor in the second opening and electrically connecting the third electric conductor to the second electric conductor.
The structure includes:
a first dielectric layer positioned on the substrate and covering the first electric conductor;
a first patterned hard mask positioned on the first dielectric layer;
a second electric conductor positioned in the first patterned hard mask and the first dielectric layer and electrically connected with the first electric conductor;
a second dielectric layer positioned on the first patterned hard mask and the second electric conductor; and
a third electric conductor positioned in the second dielectric layer and over the first patterned hard mask and electrically connected with the second electric conductor
The present invention transfers the pattern of a patterned photoresist layer to a hard mask layer first, and then uses the patterned hard mask as an etching mask to etch a first dielectric layer to form contact holes. Therefore, AEI CD can be made be smaller than ADI CD. The patterned hard mask of the present invention can be an etching mask of contact holes, a stop layer of a CMP process for contact plugs, and an etch stop layer of a trench in a metal interconnect process. In addition, the present invention uses SiC or SiCN made in low temperature as a patterned hard mask, and therefore a phase variation of NiSi positioned upon a gate electrode and source/drain regions can be avoided effectively.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-11 are schematic, cross-sectional diagrams showing a process of fabricating a metal interconnect structure in accordance with the prior art.
FIGS. 12-20 are schematic, cross-sectional diagrams illustrating a method of fabricating a metal interconnect structure in accordance with a preferred embodiment of the present invention.
 DETAILED DESCRIPTION
Please refer to FIGS. 12-20. FIGS. 12-20 are schematic, cross-sectional diagrams illustrating a method of fabricating a metal interconnect structure in accordance with a preferred embodiment of the present invention. As shown in FIG. 12, first a semiconductor substrate 62 such as wafer or SOI is provided, and at least one MOS transistor device 72 is formed on the semiconductor substrate 62. The MOS transistor device 72, which is isolated by shallow trench isolations 74, includes source/drain regions 64, a gate electrode 66, and a spacer structure 68 disposed on the sidewalls of the gate electrode 66. The MOS transistor device 72 may further includes silicides 70 disposed on the surface of the gate electrode 66 and the source/drain regions 64. The material of the silicides 70 can be NiSi formed by a salicide process. The semiconductor substrate 62 further includes a contact etch stop layer 76 deposited over the MOS transistor device 72 and the semiconductor substrate 62, and a first dielectric layer 78 deposited on the contact etch stop layer 76.
In selecting the materials of the first dielectric layer 78 and the contact etch stop layer 76, etching selectivity should be a concern. Normally, the first dielectric layer 78 may include tetraethylorthosilicate (TEOS) oxide, un-doped silicon glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), FSG, PSG or BSG. Spin coating or chemical vapor deposition (CVD), such as a plasma-enhanced chemical vapor deposition (PECVD) method, or other deposition techniques may be used to deposit the first dielectric layer 78. The contact etch stop layer 76 may include material with high stress, such as SiN, or other materials having high etching selectivity with the first dielectric layer 78.
Subsequently, a hard mask layer 80, a first BARC layer 82, and a patterned photoresist layer 84 are formed upon the first dielectric layer 78 in sequence. The patterned photoresist layer 84 has a plurality of openings 86. The openings 86 are disposed corresponding to the gate electrode 66 and the source/drain regions 64 so as to define the locations of contact holes. In the preferred embodiment of the present invention, material of the hard mask layer 80 is composed of a chemical compound of silicon with carbon or nitrogen, such as SiC or SiCN, that can be made at low temperature because when choosing material of the hard mask layer 80, the forming temperature of the hard mask layer 80 is required to be under 400° C. in order to avoid phase variation of NiSi upon the gate electrode 66 and the source/drain regions 64. The first BARC layer 82 can be SiON.
Afterwards, an anisotropic etching process is performed by using the patterned photoresist layer 84 as an etching mask to etch the first BARC layer 82 and the hard mask layer 80 through the openings 86 to transfer the pattern of the patterned photoresist layer 84 to the hard mask layer 80 in order to form a first patterned hard mask 81, as shown in FIG. 13. By control and adjustment of etching parameters, the ADI CD 88 of the patterned photoresist layer 84 is larger than the AEI CD 90 of the first patterned hard mask 81 in the present invention, and a semiconductor process under 45 nm can be accomplished.
As shown in FIG. 14, after removing the patterned photoresist layer 84 and the first BARC layer 82, the present invention uses the first patterned hard mask 81 as an etching mask to etch the first dielectric layer 78 and the contact etch stop layer 76 to form a plurality of openings as contact holes 92 in the first dielectric layer 78 and the contact etch stop layer 76. A cleaning process is performed to remove polymer residues or particles remaining in the sidewalls of the contact holes 92. The cleaning process can be a wet clean process or a dry clean process, and can be performed in-situ or ex-situ. Then, a diffusion barrier 94 is formed on the first patterned hard mask 81 and the sidewalls of the contact holes 92. The diffusion barrier 94 is a composite metal layer such as titanium nitride (TiN)/titanium (Ti) or tantalum nitride (TaN)/tantalum (Ta) in order to avoid metal atom diffusion damaging the device character, and to increase adhesion between metal and the first dielectric layer 78. To ensure good conductivity of the gate electrode 66 and the source/drain regions 64 or maintain clean sidewalls of the contact holes 92, at least a surface process is carried out after forming contact holes 92. The surface process can be a doping process to lower resistance of the gate electrode 66 and the source/drain regions 64 to benefit follow-up fabrication of contact plugs.
As shown in FIG. 15, the contact holes 92 are filled with the first metal layer 98, such as tungsten (W), and the surface diffusion barrier layer 94 is covered with the first metal layer 98 to electrically connect the gate electrode 66 and the source/drain regions 64. Then, the first patterned hard mask 81 is used as a stop layer to in a first CMP process on the first metal layer 98 and the diffusion barrier 94 in order to form every contact plug 100 in the first dielectric layer 78, as shown in FIG. 16.
As shown in FIG. 17, a second dielectric layer 102, a second BARC layer 104, and a second patterned hard mask layer 106 are formed upon the first hard mask layer 81 and every contact plug 100 in sequence. The second patterned hard mask layer 106 has a plurality of openings 108. The openings 108 are disposed corresponding to every contact plug 100 electrically connecting the gate electrode 66 and the source/drain regions 64 so as to define the locations of trenches 110. Then, second patterned hard mask layer 106 is used as an etching mask, the first hard mask layer 81 and the surface of contact plugs 100 are used as an etch stop layer to etch the second BARC layer 104 and the second dielectric layer 102 to form trenches 110 in the second BARC layer 104 and the second dielectric layer 102, and the second patterned hard mask layer 106 and the second BARC layer 104 are removed, as shown in FIG. 18. The second dielectric layer 102 may include tetraethylorthosilicate (TEOS) oxide, un-doped silicon glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), FSG, PSG or BSG. Spin coating or CVD, such as a PECVD method, or other deposition techniques may be used to deposit the second dielectric layer. The second patterned hard mask layer 106 is made of photoresist material.
As shown in FIG. 19, a standard copper process or other low-resistance conductor process is carried out to deposit a diffusion barrier layer of TiN/Ti or TaN/Ta (not shown) and a seed layer (not shown) over sidewalls of every trench 110, upon the second dielectric layer 102, and every contact plug 100. Then, electroplating is performed to form a second metal layer 112 to fill the trench 110, as is well known. Finally, the second dielectric layer 102 is used as a stop layer in a second CMP process on the second metal layer 112 and the diffusion barrier (not shown) in order to form every metal wire 114 electrically connected to every contact plug 100 separately, as shown in FIG. 20.
As mentioned above, the present invention also discloses a metal interconnect structure. As shown in FIG. 20, the metal interconnect structure of the present invention is positioned on a semiconductor substrate 62, and at least a first electric conductor, such as a MOS transistor device 72 comprising a gate electrode 66, source/drain regions 64, and a spacer structure 68, is positioned on the semiconductor substrate 62. The metal interconnect structure comprises a first dielectric layer 78 positioned on the substrate and covering the first electric conductor, a first patterned hard mask 81 positioned on the first dielectric layer 78, contact plugs 100 positioned in the first patterned hard mask 81 and the first dielectric layer 78 and electrically connected with the first electric conductor, a second dielectric layer 102 positioned on the first patterned hard mask 81 and the contact plugs 100, and metal wires 114 positioned in the second dielectric layer 102 and over the first patterned hard mask 81 and electrically connected with the contact plugs 100. The materials of each film layer and conductor are disclosed in the embodiment of FIG. 12-20, and are not redundantly described here.
The present invention uses the patterned photoresist layer 84 as an etching mask to etch the hard mask layer 80 and transfer a pattern of the patterned photoresist layer 84 to the hard mask layer 80 first to form the first patterned hard mask 81, and then uses the first patterned hard mask 81 as an etching mask to etch the first dielectric layer 78 to form the contact holes 92. Therefore, a etch program can be used to control a critical dimension of the pattern on the first patterned hard mask 81 to make AEI CD smaller than ADI CD. The first patterned hard mask 81 of the present invention can be an etching mask of contact holes 92, a stop layer of a CMP process for contact plugs 100, and an etch stop layer of the trench 100 in a follow-up metal interconnect process. In addition, since a process under 65 nm needs NiSi as silicide 70 on the gate electrode 66 and the source/drain regions 64, the present invention uses SiC or SiCN made at low temperature as the hard mask layer 80. The forming temperature of the hard mask layer 80 is under 400° C., and therefore phase variation of NiSi positioned upon gate electrode 66 and source/drain regions 64 can be avoided.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (14)

1. A method for making a metal interconnect comprising:
providing a substrate and at least a first electric conductor;
forming a first dielectric layer over the first electric conductor on the substrate;
forming a first patterned hard mask on the first dielectric layer to define at least a first opening;
using the first patterned hard mask as an etching mask to etch the first dielectric layer to form the first opening in the first dielectric layer;
forming a first metal layer to fill the first opening and covering the first patterned hard mask;
using the first patterned hard mask as a polishing stop layer and performing a polishing process on the first metal layer to form a second electric conductor in the first opening and electrically connecting the second electric conductor to the first electric conductor;
forming a second dielectric layer over the first patterned hard mask and the second electric conductor;
forming a second patterned hard mask on the second dielectric layer to define at least a second opening;
using the second patterned hard mask as an etching mask and using the first patterned hard mask and the second electric conductor as an etch stop layer to etch the second dielectric layer to form the second opening in the second dielectric layer; and
forming a third electric conductor in the second opening and electrically connecting the third electric conductor to the second electric conductor.
2. The method of claim 1, wherein the first electric conductor comprises a gate, a source, a drain, or a doped region.
3. The method of claim 2, wherein the first opening is a contact hole and the second electric conductor is a contact plug.
4. The method of claim 3, wherein a contact etch stop layer (CESL) is formed between the substrate and the first dielectric layer and covers the first electric conductor.
5. The method of claim 1, wherein forming the first patterned hard mask comprises:
forming a mask layer, a bottom antireflective coating (BARC) layer, and a patterned photoresist layer on the first dielectric layer;
using the patterned photoresist layer as an etching mask to etch the BARC layer and the mask layer to transfer the pattern of the patterned photoresist layer to the mask layer to form the first patterned hard mask; and
removing the patterned photoresist layer and the BARC layer.
6. The method of claim 5, wherein an after-development-inspection critical dimension (ADI CD) of the patterned photoresist layer is larger than an after etch-inspection critical dimension (AEI CD) of the first patterned hard mask.
7. The method of claim 5, wherein the first electric conductor contains a silicide layer, and a forming temperature of the mask layer is under 400° C.
8. The method of claim 7, wherein the mask layer is composed of a chemical compound of silicon with carbon or nitrogen.
9. The method of claim 1, wherein the second opening includes a via hole, a trench, a single damascene opening, or a dual damascene opening.
10. The method of claim 9, wherein the third electric conductor includes a via plug or a metal line.
11. The method of claim 9, wherein forming the third electric conductor in the second opening comprises:
forming a second metal layer to fill the second opening and covering the second electric conductor and part of the first patterned hard mask; and
using the second dielectric layer as stop layer and performing a second CMP process for the second metal layer.
12. The method of claim 11, wherein the second metal layer includes copper.
13. The method of claim 1, wherein the second patterned hard mask layer is a patterned photoresist layer.
14. The method of claim 1, wherein a BARC layer is formed between the second patterned hard mask layer and the second dielectric layer.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210454A1 (en) * 2006-01-04 2007-09-13 Pei-Yu Chou Structure of Metal Interconnect and Fabrication Method Thereof
CN102024784A (en) * 2009-09-22 2011-04-20 台湾积体电路制造股份有限公司 Block contact plugs for mos devices
US20110223752A1 (en) * 2010-03-09 2011-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a gate structure
US20120146106A1 (en) * 2010-12-14 2012-06-14 Globalfoundries Inc. Semiconductor devices having through-contacts and related fabrication methods
US8999838B2 (en) * 2011-08-31 2015-04-07 Macronix International Co., Ltd. Semiconductor devices and methods of manufacturing the same
US9287161B2 (en) 2013-11-21 2016-03-15 Samsung Electronics Co., Ltd. Method of forming wirings
US9349873B1 (en) * 2015-07-08 2016-05-24 United Microelectronics Corp. Oxide semiconductor device and method of fabricating the same

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8236702B2 (en) * 2005-10-06 2012-08-07 United Microelectronics Corp. Method of fabricating openings and contact holes
US8164141B2 (en) 2005-10-06 2012-04-24 United Microelectronics Corp. Opening structure with sidewall of an opening covered with a dielectric thin film
US8258057B2 (en) * 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
US7378341B2 (en) * 2006-05-08 2008-05-27 United Microelectronics Corp. Automatic process control of after-etch-inspection critical dimension
US7670946B2 (en) * 2006-05-15 2010-03-02 Chartered Semiconductor Manufacturing, Ltd. Methods to eliminate contact plug sidewall slit
US7851360B2 (en) * 2007-02-14 2010-12-14 Intel Corporation Organometallic precursors for seed/barrier processes and methods thereof
JP5211503B2 (en) * 2007-02-16 2013-06-12 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
KR101178573B1 (en) 2008-05-21 2012-08-31 에스케이하이닉스 주식회사 Method for forming capacitor of semiconductor device
CN102403264B (en) * 2010-09-17 2014-03-12 中芯国际集成电路制造(北京)有限公司 Etching method for contact holes of metal grid MOS (metal oxide semiconductor) devices
CN102437089B (en) * 2011-07-12 2014-05-28 上海华力微电子有限公司 Copper subsequent interconnection technique
US9349849B2 (en) * 2012-03-28 2016-05-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device including the semiconductor device
CN103794548B (en) * 2012-10-31 2016-02-17 中芯国际集成电路制造(上海)有限公司 The formation method of local interconnect structure
US8993433B2 (en) * 2013-05-27 2015-03-31 United Microelectronics Corp. Manufacturing method for forming a self aligned contact
US9633835B2 (en) * 2013-09-06 2017-04-25 Intel Corporation Transistor fabrication technique including sacrificial protective layer for source/drain at contact location
US9231098B2 (en) 2013-10-30 2016-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanism for forming metal gate structure
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US11127834B2 (en) * 2019-10-11 2021-09-21 Globalfoundries U.S. Inc Gate structures
US11488857B2 (en) * 2019-10-31 2022-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture using a contact etch stop layer (CESL) breakthrough process
CN112750761A (en) 2019-10-31 2021-05-04 台湾积体电路制造股份有限公司 Semiconductor device and method for manufacturing the same
US11276571B2 (en) 2019-12-26 2022-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method of breaking through etch stop layer
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CN116053203B (en) * 2023-03-07 2023-06-30 合肥晶合集成电路股份有限公司 Method for preparing interconnection structure

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904565A (en) * 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6004883A (en) * 1998-10-23 1999-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene patterned conductor layer formation method without etch stop layer
US6057227A (en) * 1997-06-23 2000-05-02 Vlsi Technology, Inc. Oxide etch stop techniques for uniform damascene trench depth
US6191028B1 (en) * 1997-12-03 2001-02-20 United Microelectronics, Corp Method of patterning dielectric
US6211061B1 (en) * 1999-10-29 2001-04-03 Taiwan Semiconductor Manufactuirng Company Dual damascene process for carbon-based low-K materials
US6287961B1 (en) * 1999-01-04 2001-09-11 Taiwan Semiconductor Manufacturing Company Dual damascene patterned conductor layer formation method without etch stop layer
WO2002029892A2 (en) 2000-10-03 2002-04-11 Broadcom Corporation High-density metal capacitor using dual-damascene copper interconnect
US6479380B2 (en) * 2000-05-25 2002-11-12 Hitachi, Ltd. Semiconductor device and manufacturing method thereof
WO2003054928A2 (en) 2001-12-13 2003-07-03 International Business Machines Corporation Porous low-k dielectric interconnect structures
US20030207561A1 (en) 2002-05-03 2003-11-06 Dubin Valery M. Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs
WO2004003980A2 (en) 2002-06-28 2004-01-08 Motorola, Inc. Interconnect structure and method for forming

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5753418A (en) 1996-09-03 1998-05-19 Taiwan Semiconductor Manufacturing Company Ltd 0.3 Micron aperture width patterning process
US6255161B1 (en) * 2000-10-06 2001-07-03 Nanya Technology Corporation Method of forming a capacitor and a contact plug
CN1237598C (en) 2001-08-22 2006-01-18 联华电子股份有限公司 Method for forming metal capacitors in damascene process
US20050064629A1 (en) 2003-09-22 2005-03-24 Chen-Hua Yu Tungsten-copper interconnect and method for fabricating the same
US7365009B2 (en) * 2006-01-04 2008-04-29 United Microelectronics Corp. Structure of metal interconnect and fabrication method thereof

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6057227A (en) * 1997-06-23 2000-05-02 Vlsi Technology, Inc. Oxide etch stop techniques for uniform damascene trench depth
US5904565A (en) * 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6191028B1 (en) * 1997-12-03 2001-02-20 United Microelectronics, Corp Method of patterning dielectric
US6004883A (en) * 1998-10-23 1999-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene patterned conductor layer formation method without etch stop layer
US6287961B1 (en) * 1999-01-04 2001-09-11 Taiwan Semiconductor Manufacturing Company Dual damascene patterned conductor layer formation method without etch stop layer
US6211061B1 (en) * 1999-10-29 2001-04-03 Taiwan Semiconductor Manufactuirng Company Dual damascene process for carbon-based low-K materials
US6479380B2 (en) * 2000-05-25 2002-11-12 Hitachi, Ltd. Semiconductor device and manufacturing method thereof
WO2002029892A2 (en) 2000-10-03 2002-04-11 Broadcom Corporation High-density metal capacitor using dual-damascene copper interconnect
US6902972B2 (en) 2000-10-03 2005-06-07 Broadcom Corporation High-density metal capacitor using dual-damascene copper interconnect
WO2003054928A2 (en) 2001-12-13 2003-07-03 International Business Machines Corporation Porous low-k dielectric interconnect structures
US20030207561A1 (en) 2002-05-03 2003-11-06 Dubin Valery M. Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs
WO2004003980A2 (en) 2002-06-28 2004-01-08 Motorola, Inc. Interconnect structure and method for forming

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210454A1 (en) * 2006-01-04 2007-09-13 Pei-Yu Chou Structure of Metal Interconnect and Fabrication Method Thereof
US7524742B2 (en) * 2006-01-04 2009-04-28 United Microelectronics Corp. Structure of metal interconnect and fabrication method thereof
CN102024784A (en) * 2009-09-22 2011-04-20 台湾积体电路制造股份有限公司 Block contact plugs for mos devices
CN102024784B (en) * 2009-09-22 2013-03-20 台湾积体电路制造股份有限公司 Block contact plugs for mos devices
US20110223752A1 (en) * 2010-03-09 2011-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a gate structure
US8535998B2 (en) * 2010-03-09 2013-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a gate structure
US8952459B2 (en) 2010-03-09 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure having lightly doped region
US20120146106A1 (en) * 2010-12-14 2012-06-14 Globalfoundries Inc. Semiconductor devices having through-contacts and related fabrication methods
US8951907B2 (en) * 2010-12-14 2015-02-10 GlobalFoundries, Inc. Semiconductor devices having through-contacts and related fabrication methods
US8999838B2 (en) * 2011-08-31 2015-04-07 Macronix International Co., Ltd. Semiconductor devices and methods of manufacturing the same
US9287161B2 (en) 2013-11-21 2016-03-15 Samsung Electronics Co., Ltd. Method of forming wirings
US9349873B1 (en) * 2015-07-08 2016-05-24 United Microelectronics Corp. Oxide semiconductor device and method of fabricating the same

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