US7113425B2 - Nonvolatile semiconductor memory device with scalable two transistor memory cells - Google Patents
Nonvolatile semiconductor memory device with scalable two transistor memory cells Download PDFInfo
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- US7113425B2 US7113425B2 US10/976,626 US97662604A US7113425B2 US 7113425 B2 US7113425 B2 US 7113425B2 US 97662604 A US97662604 A US 97662604A US 7113425 B2 US7113425 B2 US 7113425B2
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
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- E06B7/00—Special arrangements or measures in connection with doors or windows
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- E06B7/23—Plastic, sponge rubber, or like strips or tubes
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- E06B7/2307—Plastic, sponge rubber, or like strips or tubes with an integrally formed part for fixing the edging with a single sealing-line or -plane between the wing and the part co-operating with the wing
- E06B7/2309—Plastic, sponge rubber, or like strips or tubes with an integrally formed part for fixing the edging with a single sealing-line or -plane between the wing and the part co-operating with the wing with a hollow sealing part
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- E—FIXED CONSTRUCTIONS
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- E05Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
- E05Y2800/00—Details, accessories and auxiliary operations not otherwise provided for
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- E—FIXED CONSTRUCTIONS
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- E05Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
- E05Y2800/00—Details, accessories and auxiliary operations not otherwise provided for
- E05Y2800/40—Physical or chemical protection
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Definitions
- This disclosure relates to semiconductor memory devices, and more particularly, to a nonvolatile semiconductor memory device with scalable two transistor memory (STTM) cells.
- STTM scalable two transistor memory
- DRAM semiconductor devices Compared to other memory devices such as SRAM semiconductor devices, DRAM semiconductor devices have an advantage of being able to achieve a higher integration density. But DRAM semiconductor devices cannot maintain a stored charge, as required by scaling, due to leakage current from memory cells, internal noise, and soft errors caused by incident alpha particles. Therefore, the memory cells of such devices require constant refreshing in order to maintain stored data. Thus, power consumption is large even in stand-by mode.
- flash memory devices or EEPROM devices
- flash memory devices have a merit in that there is no need to refresh the memory cells in order to maintain data stored in the memory cells.
- a primary drawback of flash memory devices is that it is difficult to improve its relatively slow access time because it takes a relatively long time to program the memory cells.
- a high voltage is necessary to program (write) or erase memory cells of flash memory devices. The high electric field applied during erase/write cycles degrades the SiO2 tunneling barrier to the floating gate over a predetermined number (typically about 105) of erase/write cycles and, as a result, limits the operational life of the memory device.
- a predetermined number typically about 105
- a semiconductor memory device having memory cells that allow scalable memory charge relative to cell density of the device long-term retention, low voltage, high speed, and highly reliable operational characteristics.
- One such novel memory cell which can be named as a Scalable Two-Transistor Memory cell, has been proposed by Nazato et al. (refer to IEDM 97, pp. 179–182 and U.S. Pat. No 5,952,692).
- Nazato et al. referred to their device as a Planar Localized Electron Device Memory (PLEDM) cell.
- PLEDM Planar Localized Electron Device Memory
- It also has an isolated memory node, which provides immunity against soft errors, and a gain property, which provides a large S/N ratio. It is a quantum tunneling device that works at room temperature with no hot carrier degradation effects, and can be fabricated by exsiting silicon processing technology. Using the STTM cell, the following invention discloses an improved cell array structure so that operation speed is increased.
- FIG. 1 is a circuit diagram of a nonvolatile memory device according to an embodiment of the invention.
- FIG. 2 is a timing diagram illustrating a write operation of the nonvolatile memory device according to the invention.
- FIG. 3 is a timing diagram illustrating a read operation of the nonvolatile memory device according to the invention.
- FIG. 4 shows a bulk structure used in order to measure a voltage distribution of a sense node in the nonvolatile memory device according to the invention.
- One feature of the invention is to provide a non-volatile memory device operable at high speed.
- Another feature of the invention is to provide a non-volatile memory device having an improved cell array structure.
- Still other feature of the invention is to provide a non-volatile memory device capable of verifying a voltage distribution of a sense node in a STTM cell.
- a non-volatile memory device comprises a bit line; first and second data lines; a first group of scalable two transistor memory (STTM) cells connected in parallel between the bit line and the first data line; and a second group of STTM cells connected in parallel between the bit line and the second data line.
- STTM scalable two transistor memory
- the memory device further includes a first group of control lines respectively connected to the STTM cells of the first group, and a second group of control lines respectively connected to the STTM cells of the second group.
- the control lines of the first and second groups are alternately arranged.
- the memory device further includes a selection circuit for selecting one of the first and second data lines in response to the control signals; and a sense amplification circuit for sensing and amplifying a voltage difference between the bit line and the selected data line.
- the sense amplification circuit senses data stored in a selected STTM cell and writes data to be written to the selected STTM cell in a write operation.
- the sense amplification circuit senses data stored in a selected STTM cell and outputs the sensed data to the outside in a read operation. And, the sensed data is outputted to the outside, and at the same time, is restored in the sensed data in the selected STTM cell.
- the sense amplification circuit supplies a bias current to the selected STTM cell in sensing data stored in a selected STTM cell.
- each of the STTM cells includes a read transistor and a write transistor.
- the sense amplification circuit includes a bias current supply part for supplying a bias current to the selected STTM cell in a read/write operation.
- bulk regions of read transistors in the STTM cells are electrically separated from a bulk region of the bias current supply part in the sense amplification circuit.
- the sense node voltage distribution of the STTM cells is verified by controlling a voltage applied to bulk regions of the read transistors of the STTM cells.
- a non-volatile memory device comprises a plurality of data line pairs; a plurality of bit lines arranged between each pair of data lines; a plurality of scalable two transistor memory (STTM) cells arranged so as to share a bit line arranged between each pair of data lines; a plurality of data line selectors corresponding to each pair of the data lines, each of the data line selectors selecting one data line among a corresponding data line pair; and a plurality of sense amplifiers each corresponding to the data line selectors, each of the sense amplifiers sensing and amplying a voltage difference between a data line selected by a corresponding data line selector and a corresponding bit line.
- STTM scalable two transistor memory
- STTM cells connected to each of the data line pairs are classified into a first group and a second group.
- the first group of STTM cells are respectively connected to control lines of the first group.
- the second group of STTM cells are respectively connected to control lines of the second group.
- the control lines of the first and second groups are alternately arranged.
- each of the sense amplifiers senses data stored in a selected STTM cell and then writes data to be written to the selected STTM cell in a write operation.
- Each of the sense amplifiers senses data stored in the selected STTM and outputs the sensed data to the outside. The sensed data is outputted to the outside, and at the same time, is restored in the selected STTM cell in a read operation.
- Each of the sense amplifiers supplies a bias current to the selected STTM cell in sensing data stored in the selected STTM cell.
- each of the STTM cells includes a read transistor and a write transistor.
- Each of the sense amplifiers includes a bias current supply part of supplying a bias current to the selected STTM cell in a read/write operation. Bulk regions of read transistors in the STTM cells are electrically separated from a bulk region of the bias current supply part of each of the sense amplifiers. The sense node voltage distribution of the STTM cells is verified by controlling a voltage applied to bulk regions of the read transistors of the STTM cells.
- FIG. 1 is a circuit diagram showing a non-volatile memory device according to an embodiment of the invention.
- the non-volatile memory device includes a memory cell array 110 .
- a plurality of STTM cells (or non-volatile memory cells) are arranged in a matrix format in the memory cell array 110 .
- Each of the STTM cells MC comprises a write transistor (or a vertical transistor) N 1 and a read transistor (or a sense transistor) N 2 .
- the memory cell array 110 includes a plurality of data lines, a plurality of bit lines and a plurality of control lines. As shown in FIG. 1 , one bit line is shared by STTM cells in two columns. For instance, a bit line BL 0 is shared by STTM cells connected to data lines DL 0 e and DL 0 o .
- a bit line BL 1 is shared by STTM cells connected to data lines DL 1 e and DL 1 o .
- STTM cells connected to the data line DL 0 e and the bit line BL 0 are connected to a control line CL 0 .
- STTM cells connected to the data line DL 1 e and the bit line BL 1 are connected to a control line CL 1 .
- Similary, STTM cells connected to the data line DL 1 e and the bit line BL 1 are connected to a control line CL 0 .
- STTM cells connected to the data line DL 1 o and the bit line BL 1 are connected to a control line CL 1 .
- each of the STTM cells is connected to a corresponding data line.
- One bit line e.g., BL 0
- BL 0 is arranged between two adjacent data lines (e.g., DL 0 e and DL 0 o ).
- a corresponding bit line BL 0 is arranged between each pair of data lines (e.g., DL 0 e and DL 0 o ).
- STTM cells connected to DL 0 e and BL 0 lines are selected when the control line CL 0 becomes activated.
- STTM cells connected to DL 0 o and BL 0 lines are selected when the control line CL 1 becomes activated.
- FIG. 1 only four data lines DL 0 e , DL 0 o , DL 1 e and DL 1 o , and two bit lines BL 0 and BL 1 are shown. However, as not shown in FIG. 1 , the repetition of the circuit pattern shown in FIG. 1 is apparent to those skilled in the art.
- the non-volatile memory device 100 further includes data line selector blocks, sense amplifier blocks, and column gate blocks.
- data line selector blocks 120 a and 120 b two data line selector blocks 120 a and 120 b , two sense amplifier blocks 130 a and 130 b , and two column gate blocks 140 a an 140 b are shown in FIG. 1 .
- Each of the date line selector blocks 120 a and 120 b is configured to select one of two corresponding data lines.
- the data line block 120 a selects one of data lines DL 0 e and DL 0 o in response to control signals PIS 0 DLe and PIS 0 DLo.
- the data line selector block 120 b selects one of data lines DL 1 e and DL 1 o also in response to control signals PIS 0 DLe and PIS 0 DLo.
- Each of the data line selector blocks 120 a and 120 b comprises two NMOS transistors M 0 and M 1 .
- the NMOS transistor M 0 is connected between the data line DL 0 e and a latch node BLSA 0 and controlled by the control signal PIS 0 DLe.
- the NMOS transistor M 1 is connected between the data line DL 0 o and a latch node BLSA 0 and controlled by the control signal PIS 0 DLo.
- NMOS transistors M 0 and M 1 of the data line selector block 120 b are connected in the same way as described for 120 a , and the description thereof is thus omitted.
- Each of the sense amplifier blocks 130 a and 130 b senses and amplifies a voltage difference between a selected bit line and a bit line related thereto.
- the sense amplifer blocks 130 a and 130 b comprise NMOS transistors M 2 , M 3 , M 4 , M 5 , M 6 , M 9 , M 10 and M 12 , and PMOS transistors M 7 , M 8 and M 11 , which are connected as shown in FIG. 1 .
- the elements of the sense amplifier blocks 130 a and 130 b are denoted by the same reference numbers. For instance, during a read mode, each of the sense amplifier blocks reads data stored in a selected STTM cell through a bit line and restores the read data to the reselected STTM cell by a data line.
- the read data may be outputted through a corresponding column gate block to the outside.
- each sense amplifier block previously reads data stored in the selected STTM cell through a bit line. Additionally, after data to be written is loaded to a bit line, each sense amplifier block stores the data to be written to the selected STTM cell through a data line. Now, this will be more fully described hereinafter.
- the NMOS transistor M 3 and the PMOS transistor M 11 form a bias current supply part for supplying a bias current to a read transistor of the selected STTM cell during a read/write operation.
- the above-mentioned non-volatile memory device has an array structure and a peripheral circuit, which are suitable to well-known read/write operations, so that it may be operated at high speed.
- FIG. 2 is a timing diagram illustrating a write operation of the non-volatile memory device in accordance to the invention.
- charges e.g., holes
- SNe/SNo sense node
- the write operation will be described employing a pair of STTM cells that are respectively connected to the data lines DL 0 e and DL 0 o . Also, it is apparent that the write operation of STTM cells connected to the rest of the data lines is performed similarly.
- the control signal PIS 0 DLe becomes activated to a high level at a high voltage Vpp, and on the other hand, the control signal PIS 0 DLo becomes inactivated to a low level at a negative voltage Vb.
- the data line DLOe is connected to the latch node BLSA 0 of the sense amplification block 130 a by the NMOS transistor M 0 , and the data line DL 0 o is electrically insulated from the latch node BLSA 0 of the sense amplification node 130 a . That is, only one data line is connected to the sense amplification node.
- a bias current is supplied to the latch node BLSA 0 B by the PMOS transistor M 11 .
- the bias current supplied to the latch node BLSA 0 B is supplied to the bit line BL 0 by the NMOS transistor M 3 .
- the bias current supplied to the bit line BL 0 is limited by the NMOS transistor M 3 according to a voltage level of a control line PCLAMP.
- a current supplied to the bit line BL 0 will be selectively discharged through the read transistor N 2 of a selected STTM cell in accordance with a stored data of the selected STTM. For instance, in case data “1” is stored in the selected STTM cell, the current supplied to the bit line BL 0 is not discharged by the read transistor N 2 of the selected STTM cell.
- a voltage of the latch node BLSA 0 B becomes higher than a pre-charge voltage VBL.
- a voltage of the latch node BLSA 0 B becomes amplified to the power voltage Vcc
- a voltage of the latch node BLSA 0 becomes amplified to the negative voltage Vb.
- the control signal CSL 0 by activating the control signal CSL 0 , data to be written is transferred to the latch node BLSA 0 B by the NMOS transistor M 13 of a column gate block 140 a.
- control lines PIS 0 DLe, PSAB and PSA become a high level at the power voltage Vcc.
- the control signals PREBL, PEQ and PREDL become activated to a high level at the power voltage Vcc., so the bit line BL 0 is pre-charged to the ground voltage Vss, and data lines DLOe and DL 0 o become respectively pre-charged to the VBL voltage.
- the control signal PIS 0 DLo becomes activated to a high level at the high voltage Vpp, and on the other hand, the control signal PIS 0 DLe becomes inactivated to a low level at the negative voltage Vb.
- the data line DLOo is connected to the latch node BLSA 0 of the sense amplification block 130 a by the NMOS transistor M 1 , and the data line DL 0 e is electrically insulated from the latch node BLSA 0 of the sense amplification block 130 a .
- a bias current is supplied to the latch node BLSA 0 B by the PMOS transistor M 11 .
- the bias current supplied to the latch node BLSA 0 B is supplied to the bit line BL 0 by the NMOS transistor M 3 .
- the bias current supplied to the bit line BL 0 is limited by the NMOS transistor M 3 according to a voltage level of the control line PCLAMP.
- a current supplied to the bit line BL 0 will be discharged through a read transistor of a selected STTM cell according to a stored data of the selected STTM cell. For example, in case data “0” is stored in the selected STTM cell, the current supplied to the bit line BL 0 is discharged by the read transistor of the selected STTM cell.
- a voltage of the latch node BLSA 0 B becomes low in comparison with the pre-charge voltage VBL. Since the power voltage Vcc is supplied to the signal line PSAB, and a voltage lower than the power voltage Vcc is supplied to the signal line PSA, the voltage of the latch node BLSA 0 B is amplified to the negative voltage Vb, and the voltage of the latch node BLSA 0 is amplified to the power voltage Vcc. At the same time, by activating the control signal CSL 0 , data to be written to the latch node BLSA 0 B is transferred by the NMOS transistor M 13 of the column gate block 140 a.
- the values of the latch nodes BLSA 0 B and BLSA 0 become inversed.
- the voltage of the latch node BLSA 0 is changed from the negative voltage Vb to the power voltage Vcc
- the voltage of the latch node BLSA 0 is changed from the power voltage Vcc to the negative voltage Vb.
- the negative voltage Vb is supplied to the data line DL 0 o .
- the voltage of the control line CL 1 is increased to the high voltage Vpp., so that a write transistor N 1 of the selected STTM cell becomes turned on. Accordingly, charges are not charged on the sense node SNo of the selected STTM cell. That is, data “1” is written to the selected STTM cell by performing the above-mentioned operations.
- control lines PIS 0 DLe, PIS 0 DLo, PSAB and PSA become a high level at the power voltage Vcc.
- control signals PREBL, PEQ and PREDL are activated to a high level at the power voltage Vcc., so that the bit line is pre-charged to the ground voltage Vss, and the data lines DL 0 e and DLOo are respectively pre-charged to the VBL voltage.
- FIG. 3 is a timing diagram illustrating a read operation of the non-volatile memory device according to the invention.
- a read operation here we suppose that in case data “0” is stored in a STTM cell, charges are charged in a sense node (SNe/SNo) of the STTM cell, and in case data “1” is stored in the STTM cell, charges are not charged in the sense node (SNe/SNo) of the STTM cell.
- the read operation according to the non-volatile memory device of the invention will be more fully described hereinafter.
- the read operation will be described employing a pair of STTM cells that are respectively connected to the data lines DL 0 e and DL 0 o . Also, it is apparent that the read operation of STTM cells connected to the rest of the data lines is performed similarly.
- the control signal PIS 0 DLe becomes activated to a high level at a high voltage Vpp, and on the other hand, the control signal PIS 0 DLo becomes inactivated to a low level at a negative voltage Vb.
- the data line DLOe is connected to the latch node BLSA 0 of the sense amplification block 130 a by the NMOS transistor M 0 , and the data line DL 0 o is electrically insulated from the latch node BLSA 0 of the sense amplification node 130 a . That is, only one data line is connected to the sense amplification node.
- a bias current is supplied to the latch node BLSA 0 B by the PMOS transistor M 11 .
- the bias current supplied to the latch node BLSA 0 B is supplied to the bit line BL 0 by the NMOS transistor M 3 .
- the bias current supplied to the bit line BL 0 is limited by the NMOS transistor M 3 .
- a current supplied to the bit line BL 0 will be selectively discharged through the read transistor N 2 of a selected STTM cell in accordance with a stored data of the selected STTM. For instance, in case data “1” is stored in the selected STTM cell, the current supplied to the bit line BL 0 is not discharged by the read transistor of the selected STTM cell.
- a voltage of the latch node BLSA 0 B becomes higher than a pre-charge voltage VBL.
- a voltage of the latch node BLSA 0 B becomes amplified to the power voltage Vcc
- a voltage of the latch node BLSA 0 becomes amplified to the negative voltage Vb.
- the read data is restored in the selected STTM cell.
- the voltage of the control line CL 0 becomes increased to the high voltage Vpp., and the write transistor N 1 of the selected STTM cell is turned on. Because the negative voltage Vb is supplied to the data line DLOe, charges are not charged with the sense node SNe of the selected STTM cell. By these operations, data “1” is read, and at the same time, a restore operation is performed.
- control lines PIS 0 DLe, PSAB and PSA become a high level of the power voltage Vcc.
- the control signals PREBL, PEQ and PREDL also become activated to a high level of the power voltage Vcc., so that the bit line BL 0 is pre-charged to the ground voltage Vss, and data lines DL 0 e and DL 0 o become respectively pre-charged to the VBL voltage.
- the control signal PIS 0 DLo becomes activated to a high level at the high voltage Vpp, and on the other hand, the control signal PIS 0 DLe becomes inactivated to a low level at the negative voltage Vb.
- the data line DL 0 o is connected to the latch node BLSA 0 of the sense amplification block 130 a by the NMOS transistor M 1 , and the data line DL 0 e is electrically insulated from the latch node BLSA 0 of the sense amplification block 130 a .
- a bias current is supplied to the latch node BLSA 0 B by the PMOS transistor M 11 .
- the bias current supplied to the latch node BLSA 0 B is supplied to the bit line BL 0 by the NMOS transistor M 3 .
- a current supplied to the bit line BL 0 will be selectively discharged through the read transistor N 2 of a selected STTM cell according to a stored data of the selected STTM cell. For example, in case data “0” is stored in the selected STTM cell, the current supplied to the bit line BL 0 is discharged by the read transistor of the selected STTM cell.
- the voltage of the latch node BLSA 0 B becomes low in comparison with the pre-charge voltage VBL. Since the power voltage Vcc is supplied to the signal line PSAB, and a voltage lower than the power voltage Vcc is supplied to the signal line PSA, a voltage of the latch node BLSA 0 B becomes amplified to the power voltage Vcc, and a voltage of the latch node BLSA 0 is amplified to the negative voltage Vb. By activating the control signal CSL 0 , the voltage of the latch node BLSA 0 B will be outputted as read data to the outside by the NMOS transistor M 13 of the column gate block 140 a .
- the read data is restored in the selected STTM cell.
- the voltage of the control line CL 0 becomes increased to the high voltage Vpp.
- the write transistor N 1 of the selected STTM cell becomes turned on. Because the power voltage Vcc is supplied to the data line DLOe, charges are charged on the sense node SNe of the selected STTM cell. By previous operations, data “0” is read, and at the same time, a restore operation is performed.
- control lines PIS 0 DLe, PIS 0 DLo, PSAB and PSA become a high level of the power voltage Vcc.
- the control signals PREBL, PEQ and PREDL are activated to a high level at the power voltage Vcc., so that the bit line BL 0 is pre-charged to the ground voltage Vss, and the data lines DL 0 e and DLOo are respectively pre-charged to the VBL voltage.
- FIG. 4 shows a bulk structure used to measure a voltage distribution of a sense node in the non-volatile memory device according to the invention.
- a bulk voltage Vbb 1 of the read transistor of the STTM cell MC is different from a bulk voltage Vbb 2 of the NMOS transistor M 3 .
- a bulk region of a memory cell array where STTM cells arranged is separated from a bulk region of sense amplification block where the NMOS transistor M 3 is formed.
- the reason for this is to verify a voltage distribution of the sense node SN of the STTM cell MC. It is possible to verify the voltage distribution of the STTM cell MC by controlling a bulk-source voltage Vbs of the read transistor N 2 , that is, by varying the bulk voltage Vbb 1 of the read transistor N 2 .
- a bias current supplied by the PMOS transistor M 11 maintains constant.
- Another method for verifying the voltage distribution of the sense node SN of the STTM cell MC is to control a bias current by a control circuit 170 comprising the PMOS transistor M 14 and the NMOS transistors M 15 an M 16 .
- the voltage distribution of the sense node of the STTM cells where data “0” is stored may be verified by fixing the bulk voltage Vbb 1 to 0V and varying a bias voltage VBIAS.
- the voltage distribution of the sense node of the STTM cells where data “1” is stored may be verified by fixing the bulk voltage Vbb 1 to a voltage lower than 0V and varying the bias voltage VBIAS.
- a read/write operation is possibly performed by improving an array structure, so that a non-volatile memory device operated at high speed may be embodied.
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Abstract
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Application Number | Priority Date | Filing Date | Title |
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KR2004-603 | 2004-01-06 | ||
KR10-2004-0000603A KR100528484B1 (en) | 2004-01-06 | 2004-01-06 | Nonvolatile semiconductor memory device with scalable two transistor memory cells |
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US7113425B2 true US7113425B2 (en) | 2006-09-26 |
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US10/976,626 Expired - Lifetime US7113425B2 (en) | 2004-01-06 | 2004-10-29 | Nonvolatile semiconductor memory device with scalable two transistor memory cells |
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US (1) | US7113425B2 (en) |
JP (1) | JP5095083B2 (en) |
KR (1) | KR100528484B1 (en) |
CN (1) | CN100524522C (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080198676A1 (en) * | 2007-02-15 | 2008-08-21 | Qimonda Ag | Semiconductor memory device and method with a changeable substrate potential |
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CN102576330B (en) | 2009-06-12 | 2015-01-28 | 提琴存储器公司 | Memory system having persistent garbage collection |
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US5896327A (en) * | 1997-10-27 | 1999-04-20 | Macronix International Co., Ltd. | Memory redundancy circuit for high density memory with extra row and column for failed address storage |
US5952692A (en) | 1996-11-15 | 1999-09-14 | Hitachi, Ltd. | Memory device with improved charge storage barrier structure |
US6710465B2 (en) * | 2001-06-21 | 2004-03-23 | Samsung Electronics Co., Ltd. | Scalable two transistor memory device |
US6757196B1 (en) * | 2001-03-22 | 2004-06-29 | Aplus Flash Technology, Inc. | Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device |
US6831860B2 (en) * | 2001-05-23 | 2004-12-14 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device |
US6882561B2 (en) * | 2002-09-14 | 2005-04-19 | Samsung Electronics Co., Ltd. | Semiconductor memory device comprising memory having active restoration function |
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JP3554666B2 (en) * | 1997-10-07 | 2004-08-18 | 株式会社日立製作所 | Semiconductor memory device |
JP2002216482A (en) * | 2000-11-17 | 2002-08-02 | Toshiba Corp | Semiconductor memory integrated circuit |
JP4149170B2 (en) * | 2002-01-22 | 2008-09-10 | 株式会社ルネサステクノロジ | Semiconductor memory device |
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2004
- 2004-01-06 KR KR10-2004-0000603A patent/KR100528484B1/en not_active Expired - Fee Related
- 2004-10-29 US US10/976,626 patent/US7113425B2/en not_active Expired - Lifetime
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2005
- 2005-01-05 JP JP2005000851A patent/JP5095083B2/en not_active Expired - Fee Related
- 2005-01-06 CN CNB200510004106XA patent/CN100524522C/en not_active Expired - Fee Related
Patent Citations (6)
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US5952692A (en) | 1996-11-15 | 1999-09-14 | Hitachi, Ltd. | Memory device with improved charge storage barrier structure |
US5896327A (en) * | 1997-10-27 | 1999-04-20 | Macronix International Co., Ltd. | Memory redundancy circuit for high density memory with extra row and column for failed address storage |
US6757196B1 (en) * | 2001-03-22 | 2004-06-29 | Aplus Flash Technology, Inc. | Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device |
US6831860B2 (en) * | 2001-05-23 | 2004-12-14 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device |
US6710465B2 (en) * | 2001-06-21 | 2004-03-23 | Samsung Electronics Co., Ltd. | Scalable two transistor memory device |
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Cited By (2)
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US20080198676A1 (en) * | 2007-02-15 | 2008-08-21 | Qimonda Ag | Semiconductor memory device and method with a changeable substrate potential |
US7808853B2 (en) * | 2007-02-15 | 2010-10-05 | Qimonda Ag | Semiconductor memory device and method with a changeable substrate potential |
Also Published As
Publication number | Publication date |
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US20050146929A1 (en) | 2005-07-07 |
CN100524522C (en) | 2009-08-05 |
KR20050072229A (en) | 2005-07-11 |
KR100528484B1 (en) | 2005-11-15 |
JP5095083B2 (en) | 2012-12-12 |
CN1637950A (en) | 2005-07-13 |
JP2005196958A (en) | 2005-07-21 |
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