US6829245B1 - Head of line blocking - Google Patents
Head of line blocking Download PDFInfo
- Publication number
- US6829245B1 US6829245B1 US09/348,351 US34835199A US6829245B1 US 6829245 B1 US6829245 B1 US 6829245B1 US 34835199 A US34835199 A US 34835199A US 6829245 B1 US6829245 B1 US 6829245B1
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- 230000000903 blocking effect Effects 0.000 title description 6
- 238000000034 method Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000002265 prevention Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection or protection within a single switching element
- H04L49/505—Corrective measures
- H04L49/508—Head of Line Blocking Avoidance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/201—Multicast operation; Broadcast operation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection or protection within a single switching element
- H04L49/501—Overload detection
Definitions
- the present invention relates to network switching communication protocols generally and to prevention of head of line blocking in particular.
- a network switch creates a network among a plurality of end nodes, such as workstations, and other network switches connected thereto. Each end node is connected to one port of the network. The ports also serve to connect network switches together.
- Each end node sends packets of data to the network switch which the switch then routes either to another of the end nodes connected thereto or to a network switch to which the destination end node is connected. In the latter case, the receiving network switch routes the packet to the destination end node.
- Each network switch has to temporarily store the packets of data which it receives from the units (end node or network switch) connected to it while the switch determines how, when and through which port to retransmit the packets.
- Each packet can be transmitted to only one destination address (a “unicast” packet) or to more than one unit (a “multicast” or “broadcast” packet).
- the switch typically stores the packet only once and transmits multiple copies of the packet to some (multicast) or all (broadcast) of its ports. Once the packet has been transmitted to all of its destinations, it can be removed from the memory or written over.
- Switch 10 comprises a central queuing manager 12 , an output buffer 14 , and a multiplicity of output ports 16 .
- Switch 10 receives incoming data 18 which it stores until transmission as queued data 24 in output buffer 14 .
- switch 10 transfers the queued data 24 out of the relevant output port 16 as outgoing data 26 .
- Output buffer 14 is either a pooled buffer which services the entire switch 10 or a plurality of dedicated queues within buffer 14 , one queue per output port 16 .
- the exemplary switch 10 shown in FIG. 1 comprises a pooled output buffer 14 and two output ports 16 B and 16 C.
- Incoming data 18 comprises data packets 30 , 32 , 34 arid 36 , which are designated for various destination ports 16 .
- Data 18 is received by manager 12 , which identifies the appropriate destination port 16 of the packets 30 , 32 , 34 , and 36 respectively, and dispatches them to the output buffer 14 .
- unicast data packets 32 and 36 are designated for port 16 C
- unicast data packet 30 is designated for port 16 B
- multicast packet 34 is designated for both ports 16 B and 16 C.
- Output buffer 14 stores the queued data 24 until the relevant port 16 is available, at which point, the outgoing data 26 is transferred to the relevant port 16 .
- Manager 12 is aware of the backup in the output buffer 14 , typically through a fullness sensor (not shown) measuring the fullness of output buffer 14 , and, accordingly, stops receiving incoming data 18 to switch 10 .
- switch 10 Although switch 10 no longer receives incoming data 18 , it continues to send outgoing data 26 , and thus, clears out the output buffer 14 . Once enough outgoing data 26 has been sent, output buffer 14 empties out and is again able to receive more data 24 . Manager 12 reopens inflow of data 18 to switch 10 .
- Manager 12 halts the incoming flow of data 18 . All data 18 incoming into switch 12 is halted and discarded, including unicast data packets 32 and 36 and multicast data packet 34 which are designated for the available port 16 C.
- a network switch which includes a plurality of output ports, at least one input port and a queuing manager.
- Each output port has a control unit associated therewith.
- the input port receives incoming data destined for various ones of the output ports.
- the queuing manager directs the incoming data to their destination output ports.
- Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask.
- the output queue stores the incoming data destined for its associated output port.
- the sensor senses when the output queue reaches a fullness or an emptiness state.
- the HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.
- a control unit for an output port of a network switch as described hereinabove.
- a method of controlling flow within a network switch comprising the steps of sensing when an output queue of the network switch reaches a fullness or an emptiness state, blocking queueing of incoming data to the output queue when the fullness state is sensed, discarding of unicast packets destined to the full output port queue, avoiding queuing of multicast packets to said output port queue and enabling queueing when the emptiness state is sensed.
- FIG. 1 is a schematic illustration of a prior art network switching protocol
- FIG. 2 is a schematic illustration of a network switching protocol constructed and operative in accordance with a preferred embodiment of the present invention.
- FIG. 2 illustrates, in general terms, a portion of the data packet transfer process that takes place within the operations of a network switch 50 , constructed and operative in accordance with a preferred embodiment of the present invention.
- Switch 50 comprises many of the elements described in the prior art FIG. 1 .
- Elements of FIG. 2 which are similar to those of FIG. 1 have the same reference numerals.
- switch 50 comprises a plurality of: output queues 66 , head of line (HOL) masks 52 , fullness watermarks 60 , emptiness watermarks 62 and sensors 64 .
- HOL head of line
- the output queues 66 function similar to output buffer 14 in that the output queue 66 s temporarily store data 24 waiting for transmission to output ports 16 . However, in contrast to output buffer 14 , output queues 66 are dedicated to their associated output ports 16 , for example, output queue 66 B is dedicated to output port 16 B, and so.
- HOL masks 52 control data flow to their output queues 14 .
- FIG. 2 shows HOL masks 52 B and 52 C as logical switches and operative for output queues 14 B and 14 C, respectively.
- Each sensor 64 is dedicated to an associated output queue 66 and relays to manager 12 the fullness or emptiness state of that associated queue 14 .
- Each sensor 64 is a counter which has two thresholds, one associated with its fullness watermark 60 and one associated with its emptiness watermark 62 .
- Switch 50 receives, distributes, queues and sends data in a manner similar to that described for switch 10 . Additionally similar to switch 10 , from time to time one of the output ports 16 is busier than the other output ports 16 .
- the data 24 in one or more output queue 66 backs up and reaches the fullness threshold 60 of that queue 66 .
- queue 66 is almost full and temporarily can not receive any more data 24 .
- switch 50 continues to transfer incoming data 18 to the output queues 66 which are not affected by a backup. Hence, the data going to output queue 66 C will be received and its associated output port 16 C will continue to operate unhindered. However, incoming data 18 designated for port 16 B is discarded.
- data 18 comprises data packets 54 , 56 , and 58 .
- Packets 54 and 58 are unicast packets destined for ports 16 B and 16 C, respectively.
- Packet 58 is a multicast packet destined for both ports 16 B and 16 C. All packets 54 , 56 and 58 are received by switch 50 .
- Queuing manager 12 identifies the packets and distributes them to the appropriate output queues 66 ; unicast packet 54 to output queue 66 B, multicast packet 56 to output queues 66 B and 66 C, and unicast packet 58 to output queue 66 C.
- Multicast packet 56 and unicast packet 58 designated for output queue 66 C are properly queued for delivery. However, since output queue 66 B is full, HOL mask 52 B does not queue unicast packet 54 and multicast packet 56 designated for port 16 B, and thus, packet 54 is discarded, and packet 56 is queued only to output queue 66 C.
- Port 16 B continues transmitting data 26 B, until eventually the data 24 B in output queue 66 B reaches the emptiness watermark 62 signaling that output queue 68 B is almost empty. This information is relayed by sensor 64 B to HOL mask 52 B which, in turn, reopens inflow to its associated output queue 66 B, and data will again be queued to output queue 66 B. In this manner, packets destined for output queues 66 which are not full are not affected by HOL blocking from other backed up output queues 66 .
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
A network switch which includes a plurality of output ports, at least one input port and a queuing manager. Each output port has a control unit associated therewith. The input port receives incoming data destined for various ones of the output ports. The queuing manager directs the incoming data to their destination output ports. Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask. The output queue stores the incoming data destined for its associated output port. The sensor senses when the output queue reaches a fullness or an emptiness state. The HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.
Description
The present invention relates to network switching communication protocols generally and to prevention of head of line blocking in particular.
A network switch creates a network among a plurality of end nodes, such as workstations, and other network switches connected thereto. Each end node is connected to one port of the network. The ports also serve to connect network switches together.
Each end node sends packets of data to the network switch which the switch then routes either to another of the end nodes connected thereto or to a network switch to which the destination end node is connected. In the latter case, the receiving network switch routes the packet to the destination end node.
Each network switch has to temporarily store the packets of data which it receives from the units (end node or network switch) connected to it while the switch determines how, when and through which port to retransmit the packets. Each packet can be transmitted to only one destination address (a “unicast” packet) or to more than one unit (a “multicast” or “broadcast” packet). For multicast and broadcast packets, the switch typically stores the packet only once and transmits multiple copies of the packet to some (multicast) or all (broadcast) of its ports. Once the packet has been transmitted to all of its destinations, it can be removed from the memory or written over.
Reference is now made to FIG. 1 which schematically illustrates a portion of the data packet transfer process that takes place within the operations of a network switch 10. Switch 10 comprises a central queuing manager 12, an output buffer 14, and a multiplicity of output ports 16. Switch 10 receives incoming data 18 which it stores until transmission as queued data 24 in output buffer 14. At the appropriate time, which is generally when the relevant output port 16 in available, switch 10 transfers the queued data 24 out of the relevant output port 16 as outgoing data 26.
Incoming data 18 comprises data packets 30, 32, 34 arid 36, which are designated for various destination ports 16. Data 18 is received by manager 12, which identifies the appropriate destination port 16 of the packets 30, 32, 34, and 36 respectively, and dispatches them to the output buffer 14. As an example unicast data packets 32 and 36 are designated for port 16C, unicast data packet 30 is designated for port 16B and multicast packet 34 is designated for both ports 16B and 16C. Output buffer 14 stores the queued data 24 until the relevant port 16 is available, at which point, the outgoing data 26 is transferred to the relevant port 16.
Occasionally, one of the output ports 16 transfers at a faster pace than the other ports or, alternatively, receives more data then the other ports. For whatever reason, a condition may arise where the data 24 for one of the output ports 16 backs up in the output buffer 14 creating a condition where output buffer 14 is unable to receive more data. Manager 12 is aware of the backup in the output buffer 14, typically through a fullness sensor (not shown) measuring the fullness of output buffer 14, and, accordingly, stops receiving incoming data 18 to switch 10.
All incoming data 18 not received by switch 10 is discarded, regardless of its destination output port 16. Not only is the incoming data 18 destined for the full output port discarded but the incoming data 18 destined for the available ports are also discarded. This problem is known as “Head of Line Blocking”.
Although switch 10 no longer receives incoming data 18, it continues to send outgoing data 26, and thus, clears out the output buffer 14. Once enough outgoing data 26 has been sent, output buffer 14 empties out and is again able to receive more data 24. Manager 12 reopens inflow of data 18 to switch 10.
For example, if port 16B is backed up, then the output buffer 14 will become full with queued data 24B, while output port 16C will still available to transmit. Manager 12 halts the incoming flow of data 18. All data 18 incoming into switch 12 is halted and discarded, including unicast data packets 32 and 36 and multicast data packet 34 which are designated for the available port 16C.
It is an object of the present invention to prevent Head of Line Blocking as much as possible.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a network switch which includes a plurality of output ports, at least one input port and a queuing manager. Each output port has a control unit associated therewith. The input port receives incoming data destined for various ones of the output ports. The queuing manager directs the incoming data to their destination output ports. Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask. The output queue stores the incoming data destined for its associated output port. The sensor senses when the output queue reaches a fullness or an emptiness state. The HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.
There is also provided. In accordance with a preferred embodiment of the present invention, a control unit for an output port of a network switch as described hereinabove.
Finally, there is provided, a method of controlling flow within a network switch, the method comprising the steps of sensing when an output queue of the network switch reaches a fullness or an emptiness state, blocking queueing of incoming data to the output queue when the fullness state is sensed, discarding of unicast packets destined to the full output port queue, avoiding queuing of multicast packets to said output port queue and enabling queueing when the emptiness state is sensed.
The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which;
FIG. 1 is a schematic illustration of a prior art network switching protocol; and
FIG. 2 is a schematic illustration of a network switching protocol constructed and operative in accordance with a preferred embodiment of the present invention.
Reference is now made to FIG. 2 which illustrates, in general terms, a portion of the data packet transfer process that takes place within the operations of a network switch 50, constructed and operative in accordance with a preferred embodiment of the present invention. Switch 50 comprises many of the elements described in the prior art FIG. 1. Elements of FIG. 2 which are similar to those of FIG. 1 have the same reference numerals.
In addition to the prior art elements, switch 50 comprises a plurality of: output queues 66, head of line (HOL) masks 52, fullness watermarks 60, emptiness watermarks 62 and sensors 64.
The output queues 66 function similar to output buffer 14 in that the output queue 66 s temporarily store data 24 waiting for transmission to output ports 16. However, in contrast to output buffer 14, output queues 66 are dedicated to their associated output ports 16, for example, output queue 66B is dedicated to output port 16B, and so.
HOL masks 52 control data flow to their output queues 14. FIG. 2 shows HOL masks 52B and 52C as logical switches and operative for output queues 14B and 14C, respectively. Each sensor 64 is dedicated to an associated output queue 66 and relays to manager 12 the fullness or emptiness state of that associated queue 14. Each sensor 64 is a counter which has two thresholds, one associated with its fullness watermark 60 and one associated with its emptiness watermark 62.
The data 24 in one or more output queue 66 backs up and reaches the fullness threshold 60 of that queue 66. Hence queue 66 is almost full and temporarily can not receive any more data 24.
The associated sensor 64 notifies the state of fullness to its associated HOL mask 62, which stops inflow of data to the almost full output queue 66. As an example, when the data 24 in output queue 66B reaches almost fullness, it crosses the fullness threshold 60B. Sensor 64B notifies such to HOL mask 52B which stops data flow to output queue 66B.
Unlike in the prior art which halted all inflow of data 18 to switch 10, switch 50 continues to transfer incoming data 18 to the output queues 66 which are not affected by a backup. Hence, the data going to output queue 66C will be received and its associated output port 16C will continue to operate unhindered. However, incoming data 18 designated for port 16B is discarded.
As a further example, data 18 comprises data packets 54, 56, and 58. Packets 54 and 58 are unicast packets destined for ports 16B and 16C, respectively. Packet 58 is a multicast packet destined for both ports 16B and 16C. All packets 54, 56 and 58 are received by switch 50. Queuing manager 12 identifies the packets and distributes them to the appropriate output queues 66; unicast packet 54 to output queue 66B, multicast packet 56 to output queues 66B and 66C, and unicast packet 58 to output queue 66C. Multicast packet 56 and unicast packet 58 designated for output queue 66C are properly queued for delivery. However, since output queue 66B is full, HOL mask 52B does not queue unicast packet 54 and multicast packet 56 designated for port 16B, and thus, packet 54 is discarded, and packet 56 is queued only to output queue 66C.
It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described herein above. Rather the scope of the invention is defined by the claims that follow:
Claims (1)
1. A network switch comprising:
a plurality of output ports each having a control unit associated therewith;
at least one input port for receiving incoming data destined for various ones of said output ports; and
a queuing manager for directing said incoming data to their destination output ports;
wherein each control unit comprises:
an output queue for storing said incoming data destined for its associated output port;
a fullness/emptiness sensor for sensing when said output queue reaches a fullness or an emptiness state; and
a head of line (HOL) mask, connected to the output of said sensor, for preventing queuing of said incoming data to said output queue when said sensor senses said fullness state and for enabling queuing when said sensor senses said emptiness state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/876,653 US20050041579A1 (en) | 1998-07-08 | 2004-06-28 | Head of line blocking |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IL125271 | 1998-07-08 | ||
| IL12527198A IL125271A0 (en) | 1998-07-08 | 1998-07-08 | Head of line blocking |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/876,653 Continuation US20050041579A1 (en) | 1998-07-08 | 2004-06-28 | Head of line blocking |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US6829245B1 true US6829245B1 (en) | 2004-12-07 |
Family
ID=11071722
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
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| US09/348,351 Expired - Lifetime US6829245B1 (en) | 1998-07-08 | 1999-07-08 | Head of line blocking |
| US10/876,653 Abandoned US20050041579A1 (en) | 1998-07-08 | 2004-06-28 | Head of line blocking |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/876,653 Abandoned US20050041579A1 (en) | 1998-07-08 | 2004-06-28 | Head of line blocking |
Country Status (2)
| Country | Link |
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| US (2) | US6829245B1 (en) |
| IL (1) | IL125271A0 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020034187A1 (en) * | 2000-09-20 | 2002-03-21 | Broadcom Corporation | Network switch having port blocking capability |
| US20040223456A1 (en) * | 2001-03-06 | 2004-11-11 | Deepak Mansharamani | System for fabric packet Control |
| US20050088970A1 (en) * | 2001-12-19 | 2005-04-28 | Schmidt Steven G. | Deferred queuing in a buffered switch |
| US20060064535A1 (en) * | 2004-09-22 | 2006-03-23 | Walker Robert M | Efficient multi-bank memory queuing system |
| US7308523B1 (en) | 2006-04-10 | 2007-12-11 | Pericom Semiconductor Corp. | Flow-splitting and buffering PCI express switch to reduce head-of-line blocking |
| US7792131B1 (en) | 2009-03-10 | 2010-09-07 | Cisco Technologies, Inc. | Queue sharing with fair rate guarantee |
| US20120127860A1 (en) * | 2010-11-18 | 2012-05-24 | Cisco Technology, Inc. | Dynamic Flow Redistribution for Head of Line Blocking Avoidance |
| US8554976B2 (en) | 2011-07-08 | 2013-10-08 | Plx Technology, Inc. | Single pipe non-blocking architecture |
| US8705366B2 (en) | 2012-01-23 | 2014-04-22 | Cisco Technology, Inc. | Dynamic load balancing without packet reordering |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7403521B2 (en) * | 2001-12-03 | 2008-07-22 | Intel Corporation | Multicast and broadcast operations in ethernet switches |
| US20060013135A1 (en) * | 2004-06-21 | 2006-01-19 | Schmidt Steven G | Flow control in a switch |
| DE102007024868A1 (en) * | 2006-07-21 | 2008-01-24 | Robert Bosch Gmbh | Image processing apparatus, monitoring system, method for generating a scene reference image and computer program |
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| US5448559A (en) * | 1993-05-07 | 1995-09-05 | Roke Manor Research Limited | ATM communication system with interrogation of output port servers for available handing capacity |
| US5455820A (en) * | 1993-05-20 | 1995-10-03 | Nec Corporation | Output-buffer switch for asynchronous transfer mode |
| US5841722A (en) * | 1996-02-14 | 1998-11-24 | Galileo Technologies Ltd. | First-in, first-out (FIFO) buffer |
| WO1998009471A1 (en) | 1996-08-30 | 1998-03-05 | Sgs-Thomson Microelectronics Limited | Improvements in or relating to an atm switch |
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Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7227862B2 (en) * | 2000-09-20 | 2007-06-05 | Broadcom Corporation | Network switch having port blocking capability |
| US20020034187A1 (en) * | 2000-09-20 | 2002-03-21 | Broadcom Corporation | Network switch having port blocking capability |
| US20040223456A1 (en) * | 2001-03-06 | 2004-11-11 | Deepak Mansharamani | System for fabric packet Control |
| US7719963B2 (en) * | 2001-03-06 | 2010-05-18 | Pluris, Inc. | System for fabric packet control |
| US20100265821A1 (en) * | 2001-12-19 | 2010-10-21 | Mcdata Services Corporation | Deferred Queuing in a Buffered Switch |
| US20050088970A1 (en) * | 2001-12-19 | 2005-04-28 | Schmidt Steven G. | Deferred queuing in a buffered switch |
| US7773622B2 (en) * | 2001-12-19 | 2010-08-10 | Mcdata Services Corporation | Deferred queuing in a buffered switch |
| US8379658B2 (en) | 2001-12-19 | 2013-02-19 | Brocade Communications Systems, Inc. | Deferred queuing in a buffered switch |
| US20060064535A1 (en) * | 2004-09-22 | 2006-03-23 | Walker Robert M | Efficient multi-bank memory queuing system |
| US7308523B1 (en) | 2006-04-10 | 2007-12-11 | Pericom Semiconductor Corp. | Flow-splitting and buffering PCI express switch to reduce head-of-line blocking |
| US7792131B1 (en) | 2009-03-10 | 2010-09-07 | Cisco Technologies, Inc. | Queue sharing with fair rate guarantee |
| US20100232446A1 (en) * | 2009-03-10 | 2010-09-16 | Cisco Technology, Inc. | Queue sharing with fair rate guarantee |
| GB2468585A (en) * | 2009-03-10 | 2010-09-15 | Cisco Tech Inc | Using separate counters for each separate flow in a packet queue |
| GB2468585B (en) * | 2009-03-10 | 2014-05-14 | Cisco Tech Inc | Queue sharing with fair rate guarantee |
| US20120127860A1 (en) * | 2010-11-18 | 2012-05-24 | Cisco Technology, Inc. | Dynamic Flow Redistribution for Head of Line Blocking Avoidance |
| US8565092B2 (en) * | 2010-11-18 | 2013-10-22 | Cisco Technology, Inc. | Dynamic flow redistribution for head of line blocking avoidance |
| US8554976B2 (en) | 2011-07-08 | 2013-10-08 | Plx Technology, Inc. | Single pipe non-blocking architecture |
| US8705366B2 (en) | 2012-01-23 | 2014-04-22 | Cisco Technology, Inc. | Dynamic load balancing without packet reordering |
Also Published As
| Publication number | Publication date |
|---|---|
| IL125271A0 (en) | 1999-03-12 |
| US20050041579A1 (en) | 2005-02-24 |
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