US6693785B1 - Electronic component with reduced inductive coupling - Google Patents
Electronic component with reduced inductive coupling Download PDFInfo
- Publication number
- US6693785B1 US6693785B1 US09/913,442 US91344201A US6693785B1 US 6693785 B1 US6693785 B1 US 6693785B1 US 91344201 A US91344201 A US 91344201A US 6693785 B1 US6693785 B1 US 6693785B1
- Authority
- US
- United States
- Prior art keywords
- input
- output
- pins
- electronic component
- contact pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the invention relates to an electronic component comprising:
- an integrated circuit which is encased in said package, and which includes N input contact pads and M output contact pads, which are connected, respectively, to the N input pins and M output pins by conducting wires, which integrated circuit includes a plurality of current paths, which are each used to connect an input contact pad to an output contact pad.
- each current path in an electronic component in accordance with the opening paragraph comprises a buffer element, exhibiting a high input impedance.
- each output pin thus supplies a signal which is representative only of signal contributions arriving at the input contact pads which are effectively electrically connected to said output pin, which signal consequently does not contain the parasitic component described hereinabove.
- the buffers are advantageously composed of amplifiers, whose input impedance is naturally high, for example an assembly based on a Darlington-type structure.
- each input contact pad is connected to a buffer. This ensures that all currents flowing through the conducting wires connecting the input pins to input contact pads are negligibly small.
- the invention can be employed in any type of electronic component comprising at least two input pins, the invention is advantageously used in multiplexers intended to receive and supply signals at very high frequencies, for example in the gigahertz range.
- an electronic component as described hereinabove includes:
- each switch having a first terminal and a second terminal, the first terminal being connected to one of the input contact pads, and all the second terminals being jointly connected to the input of one of the buffers, and
- control means for controlling the switching stages, which are arranged in such a way that only one of the switches included in a same switching stage can be conductive at any given instant.
- This structure which is used for multiplexing, by selecting M data signals from the N signals received on the input pins in order to direct these signals towards the M output pins, only requires M buffer, instead of the N buffers, which would have been necessary in accordance with the particular embodiment described hereinabove.
- FIG. 1 is a functional diagram showing an electronic component in accordance with a preferred embodiment of the invention.
- This component comprises:
- the integrated circuit IC comprises:
- control means CNT for controlling the switching stages SW1 and SW2, which are arranged in such a way that only one of the switches included in a same switching stage can be conductive at any given instant.
- control means CNT supply two control signals CNT1 and CNT2 to the switching stages SW1 and SW2, which control signals are coded on four bits, and one of said control signals is in the active mode, for example at a logic level 1, at a given instant.
- the switches included in the switching stages SW1 and SW2 can be implemented by means of MOS-type transistors or any other equivalent components.
- the control means CNT activate that switch of the first switching stage SW1 which is arranged between the input contact pad C11 and the output contact pad CS1, thereby producing a current path between these contact pads, then a current 11 flows through the conducting wire W11.
- the control means CNT simultaneously activate that switch of the second switching stage SW2, which is arranged between the input contact pad C12 and the output contact pad CS2, thereby producing a further current path between the contact points, then a current 12 flows through the conducting wire W12.
- the two currents 11 and 12 then create a mutual inductance between the conducting wires W11 and W12, and the signal supplied by the output pin PS1 will contain a parasitic component that is representative of the current 12, while the signal supplied by the output pin PS2 will contain a parasitic component that is representative of the current 11.
- the buffers B1 and B2 which exhibit a large input impedance, render the currents 11 and 12 negligibly small, and thereby considerably reduce the effects of the mutual inductance phenomenon occurring between the conducting wires W11 and W12.
- the output signals supplied by the output pins PS1 and PS2 thus will contain no significant parasitic component representative of, respectively, the currents 12 and 11.
- the output pins PSj will be smaller in number than the input pins PIi. It will thus be possible, in principle, to space out these output pins PSj by distributing them at the periphery of the package PACK, so that the mutual inductance between the conducting wires WSj cannot have significant effects owing to the space between said conducting wires. If such a distribution is impossible, the output pins PSj will advantageously be connected to buffers having a high input impedance, arranged outside the package PACK, and not shown in the drawing.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9915757 | 1999-12-14 | ||
FR9915757 | 1999-12-14 | ||
PCT/EP2000/012371 WO2001045260A1 (en) | 1999-12-14 | 2000-12-08 | Electronic component with reduced inductive coupling |
Publications (1)
Publication Number | Publication Date |
---|---|
US6693785B1 true US6693785B1 (en) | 2004-02-17 |
Family
ID=9553241
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/913,442 Expired - Lifetime US6693785B1 (en) | 1999-12-14 | 2000-12-08 | Electronic component with reduced inductive coupling |
Country Status (5)
Country | Link |
---|---|
US (1) | US6693785B1 (en) |
EP (1) | EP1157467A1 (en) |
JP (1) | JP2003517236A (en) |
CN (1) | CN1173472C (en) |
WO (1) | WO2001045260A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060256781A1 (en) * | 2005-05-16 | 2006-11-16 | Altera Corporation | Low-power routing multiplexers |
GB2432063A (en) * | 2005-11-01 | 2007-05-09 | Zetex Semiconductors Plc | A monolithic multiplexer for high frequency signals |
US20090267679A1 (en) * | 2008-04-25 | 2009-10-29 | Nec Electronics Corporation | Analog multiplexer and its select signal generating method |
US20140167739A1 (en) * | 2012-12-14 | 2014-06-19 | Hon Hai Precision Industry Co., Ltd. | Current detecting circuit board |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112992827B (en) * | 2021-04-27 | 2021-08-06 | 微龛(广州)半导体有限公司 | Multi-channel signal multiplexing packaging structure |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3904977A (en) * | 1973-10-05 | 1975-09-09 | Ibm | Multiplexing switch with wide bandpass characteristics and high isolation impedance between inputs |
US5017813A (en) * | 1990-05-11 | 1991-05-21 | Actel Corporation | Input/output module with latches |
US5654660A (en) * | 1995-09-27 | 1997-08-05 | Hewlett-Packard Company | Level shifted high impedance input multiplexor |
US5789966A (en) * | 1996-09-18 | 1998-08-04 | International Business Machines Corporation | Distributed multiplexer |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03133274A (en) * | 1989-10-19 | 1991-06-06 | Matsushita Electric Ind Co Ltd | Switch circuit |
JPH02223221A (en) * | 1990-01-29 | 1990-09-05 | Hitachi Ltd | Semiconductor integrated circuit device |
JPH04326617A (en) * | 1991-04-26 | 1992-11-16 | Nec Ic Microcomput Syst Ltd | Signal changeover circuit |
JPH04369923A (en) * | 1991-06-19 | 1992-12-22 | Matsushita Electric Ind Co Ltd | Signal changeover device |
JP3392561B2 (en) * | 1995-02-01 | 2003-03-31 | 東芝マイクロエレクトロニクス株式会社 | Semiconductor device |
-
2000
- 2000-12-08 WO PCT/EP2000/012371 patent/WO2001045260A1/en active Application Filing
- 2000-12-08 EP EP00987367A patent/EP1157467A1/en not_active Ceased
- 2000-12-08 CN CNB008037132A patent/CN1173472C/en not_active Expired - Fee Related
- 2000-12-08 US US09/913,442 patent/US6693785B1/en not_active Expired - Lifetime
- 2000-12-08 JP JP2001545437A patent/JP2003517236A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3904977A (en) * | 1973-10-05 | 1975-09-09 | Ibm | Multiplexing switch with wide bandpass characteristics and high isolation impedance between inputs |
US5017813A (en) * | 1990-05-11 | 1991-05-21 | Actel Corporation | Input/output module with latches |
US5654660A (en) * | 1995-09-27 | 1997-08-05 | Hewlett-Packard Company | Level shifted high impedance input multiplexor |
US5789966A (en) * | 1996-09-18 | 1998-08-04 | International Business Machines Corporation | Distributed multiplexer |
Non-Patent Citations (1)
Title |
---|
Greg Schoffer, Monolithic CMOS Video mux/amp pushes 50 Mhz, Electronic Engineering, Oct. 1987, pp. 43, 44, 48, 52. * |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060256781A1 (en) * | 2005-05-16 | 2006-11-16 | Altera Corporation | Low-power routing multiplexers |
US7982501B2 (en) | 2005-05-16 | 2011-07-19 | Altera Corporation | Low-power routing multiplexers |
US8405425B2 (en) | 2005-05-16 | 2013-03-26 | Altera Corporation | Low-power routing multiplexers |
GB2432063A (en) * | 2005-11-01 | 2007-05-09 | Zetex Semiconductors Plc | A monolithic multiplexer for high frequency signals |
GB2432063B (en) * | 2005-11-01 | 2009-09-09 | Zetex Semiconductors Plc | A multiplexer |
CN101352050B (en) * | 2005-11-01 | 2011-12-07 | 赛特克斯半导体公司 | A multiplexer |
US20090267679A1 (en) * | 2008-04-25 | 2009-10-29 | Nec Electronics Corporation | Analog multiplexer and its select signal generating method |
US20140167739A1 (en) * | 2012-12-14 | 2014-06-19 | Hon Hai Precision Industry Co., Ltd. | Current detecting circuit board |
Also Published As
Publication number | Publication date |
---|---|
CN1173472C (en) | 2004-10-27 |
WO2001045260A1 (en) | 2001-06-21 |
EP1157467A1 (en) | 2001-11-28 |
JP2003517236A (en) | 2003-05-20 |
CN1340243A (en) | 2002-03-13 |
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Legal Events
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AS | Assignment |
Owner name: U.S. PHILIPS CORPORATION, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CORDIER, CHRISTOPHE;PATRICK, JEAN;REEL/FRAME:012234/0834;SIGNING DATES FROM 20010705 TO 20010709 |
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STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
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AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:U.S. PHILIPS CORPORATION;REEL/FRAME:018635/0755 Effective date: 20061127 |
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Year of fee payment: 4 |
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Year of fee payment: 8 |
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FPAY | Fee payment |
Year of fee payment: 12 |
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Owner name: ST WIRELESS SA, SWITZERLAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NXP B.V.;REEL/FRAME:037624/0831 Effective date: 20080728 |
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AS | Assignment |
Owner name: ST-ERICSSON SA, SWITZERLAND Free format text: CHANGE OF NAME;ASSIGNOR:ST WIRELESS SA;REEL/FRAME:037683/0128 Effective date: 20080714 Owner name: ST-ERICSSON SA, EN LIQUIDATION, SWITZERLAND Free format text: STATUS CHANGE-ENTITY IN LIQUIDATION;ASSIGNOR:ST-ERICSSON SA;REEL/FRAME:037739/0493 Effective date: 20150223 |