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US20070032016A1 - Protective layer in memory device and method therefor - Google Patents

Protective layer in memory device and method therefor Download PDF

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Publication number
US20070032016A1
US20070032016A1 US11/490,483 US49048306A US2007032016A1 US 20070032016 A1 US20070032016 A1 US 20070032016A1 US 49048306 A US49048306 A US 49048306A US 2007032016 A1 US2007032016 A1 US 2007032016A1
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layer
forming
protective layer
nitride
polysilicon
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US11/490,483
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Ilan Bloom
Boaz Eitan
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Spansion Israel Ltd
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Spansion Israel Ltd
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Assigned to SAIFUN SEMICONDUCTORS LTD reassignment SAIFUN SEMICONDUCTORS LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BLOOM, ILAN, EITAN, BOAZ
Publication of US20070032016A1 publication Critical patent/US20070032016A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/954—Making oxide-nitride-oxide device

Definitions

  • the present invention relates to the manufacture of semiconductor products in general, and particularly to protection against damage to semiconductor circuits from effects of electromagnetic wave energy generated during an etch process.
  • the chip contains a memory array, it typically has a plurality of memory transistors that may be programmed or erased.
  • the memory transistors may be floating gate transistors, nitride read only memory (NROM) transistors, silicon oxide-nitride oxide-silicon (SONOS) transistors, and any other non-volatile memory metal oxide semiconductor (MOS) devices capable of storing charge.
  • NROM nitride read only memory
  • SONOS silicon oxide-nitride oxide-silicon
  • MOS non-volatile memory metal oxide semiconductor
  • the manufacturing process may have some undesirable side effects. For example, in MOS technology, the charging of active elements during the manufacturing process may alter die device's characteristics or even damage them.
  • FIG. 1 illustrates a typical cross-section of an MOS or complementary MOS (CMOS) transistor wafer It is typically formed of a gate oxide 10 over which is a polysilicon element 12 On either side of tile gate oxide 10 are field oxides 14 which are much thicker than the gate oxide 10 Typically, tie polysilicon element 12 also spreads over the field oxides 14 A more advanced process may have trench isolation instead of field oxides but the effects discussed hereinbelow are the same in such a case.
  • CMOS complementary MOS
  • die field oxides 14 are first produced on a substrate 8 , after which the gate oxides 10 are grown.
  • a layer of polysilicon is laid over the oxides 10 and 14 , and then etched to the desired shapes, such as by employing a shaped photoresist layer 15 .
  • the etching process typically involves placing a plasma 16 , as is now explained.
  • the etching process may be carried out by many methods, however, plasma based processes such as plasma enhanced chemical vapor deposition (CVD) and reactive ion etching (RIE) are very common.
  • energy for etching is generated by coupling radio frequency (RF) electromagnetic energy to a plasma 16 .
  • the RF energy may be supplied by an RF generator coupled to a power supply
  • the etching process involves placing plasma 16 between die transistor and a electrified plate 18 connected to a high voltage source, and electrically connecting a second electrified plate 20 to the substrate 8
  • Plasma may generate ultraviolet (UV) photons
  • UV photons may also be generated during deposition of metal layers, such as in sputtering techniques.
  • High energy electrons associated with the UV photons may charge the transistor. More specifically, since polysilicon is a conductive material, the polysilicon element 12 may become charged by the high energy photons. This is known as the “charging effect”
  • the charging effect is not generally a problem in conventional floating gate transistors because the excess charge may be erased. However, it may degrade tile gate oxide as is now explained.
  • the extent of the F-N tunneling is a function of the size of the polysilicon element 12 , the area of the gate oxide 10 and its thickness. As long as the area of polysilicon over the field oxides 14 is no larger than K times die area over the the gate oxides 10 (where K, called the “antenna ratio”, varies according to tie specific manufacturing process), the F-N tunneling will not occur Alternatively, the total charge passing through the oxide will be small enough not to cause breakdown of the oxide. Accordingly, the account of F-N tunneling may be reduced by reducing the area of die field oxide relative to the area of the gate.
  • the abovementioned charging effect may be reduced by various techniques, such as tie reduction of the antenna ratio K and adding discharge devices along the poly lines.
  • various techniques such as tie reduction of the antenna ratio K and adding discharge devices along the poly lines.
  • Such techniques are discussed in applicant/assignee's U.S. patent application Ser. No. 09/336,666, filed Jun. 18, 1999 and entitled “Method and Circuit for Minimizing the Charging Effect During Manufacture of Semiconductor Devices”.
  • NROM devices yet another problem may occur, wherein excess charge may accumulate along the edges of word lines.
  • the excess charge is not uniform, and increases the threshold voltage V 1 of the cell.
  • the increase in threshold voltage being non-uniformly across the device width, may degrade the reliability and endurance of tie cell
  • programmed bits in the charge-trapping nitride layer are generally erased by hot hole injection.
  • hot hole injection may only erase charge next to the source/drain junctions
  • the charge along the word line edge, far from the source/drain junctions may not generally be erased. It would therefore be desirable to prevent UV photon-induced charge effect in die word-line edges of NROM devices
  • the present invention seeks to provide methods and apparatus for protecting against plasma-induced damage to semiconductor circuits
  • the invention may be used in any non-volatile memory device, particularly a memory device with a non-conducting charge layer
  • the invention will be described with reference to an NROM device, although it is understood that the invention is not limited to NROM devices.
  • a protective layer is formed in the NROM device over a polycide structure (e.g., a word line).
  • the protective layer may comprise an ultraviolet absorber, e.g, a nitride layer
  • Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the plasma etching from inducing stress in the polysilicon layer or gate stress in al oxide-nitride-oxide (ONO) layer.
  • One preferred nitride comprises a thick silicon-rich silicon nitride alloy.
  • the protective layer may comprise a layer of highly resistive undoped polysilicon.
  • a method for protecting a non-volatile memory device die method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light
  • non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and a protective layer formed over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light.
  • the protective layer includes an ultraviolet absorber.
  • the protective layer includes a nitride layer.
  • the nitride layer includes a silicon-rich silicon nitride alloy.
  • tile nitride layer includes Si 3+x N 4 , wherein x>0.
  • the nitride layer includes a hydrogenated silicon-rich silicon nitride alloy.
  • the nitride layer includes an amorphous silicon-rich silicon nitride alloy.
  • the protective layer includes a nitride layer with a thickness of 50-1000 ⁇ .
  • the protective layer includes a layer of resistive undoped polysilicon.
  • the protective layer of undoped polysilicon includes a resistivity of at least 1 G ⁇ .
  • the protective layer of undoped polysilicon includes a thickness of 30-600 ⁇ .
  • At least one additional layer is formed over the protective layer.
  • the at least one additional layer includes at least one of a layer of undoped glass, a layer of doped glass, and a metal layer
  • the polycide structure includes a polysilicon layer and a metal silicide film.
  • die polysilicon layer includes a polycrystalline silicon (polysilicon).
  • the polysilicon layer may or may not be doped with a dopant.
  • the metal silicide film includes at least one of a tungsten silicide film and a titanium silicide film.
  • the non-volatile memory device includes a nitride, read only memory (NROM) device, and die non-conducting charge trapping layer includes a nitride charge trapping layer.
  • FIG. 1 is a schematic illustration of a prior art metal oxide semiconductor (MOS) transistor in a semiconductor chip during an etching operation;
  • MOS metal oxide semiconductor
  • FIG. 2 is a simplified illustration of a charging effect in an NROM non-volatile memory device
  • FIGS. 3 and 4 are simplified cross-sectional illustrations of application of a protective layer over portions of the NROM device of FIG. 2 , in accordance with a preferred embodiment of the present invention, wherein FIG. 3 is a cross-section along poly lines and FIG. 4 is a cross-section of word lines between bit lines.
  • FIG. 2 illustrates a charging effect in an NROM non-volatile memory device 43 , which includes one or more word lines (WL) 40 and bit lines (BL) 42 Bit lines 42 may be separated from each other by a distance L D .
  • portions of device 43 such as but not limited to, edges 50 of word line 40 , may accumulate charge (indicated by dots along edges 50 in FIG. 2 ) due to the deleterious charge effect mentioned hereinabove.
  • WL 40 may comprise a polycide structure, comprising for example, a lower polysilicon layer 44 and an upper layer formed of a metal silicide film 48
  • Polysilicon layer 44 may comprise without limitation a polycrystalline silicon (polysilicon), which may or may not be doped with a dopant such as phosphorus, for example.
  • Metal silicide film 48 may comprise without limitation a tungsten silicide film or a titanium silicide film, for example.
  • bit line 42 may include a BL oxide layer 54 and a BL junction 56
  • Additional layers may be formed over polysilicon layer 44 and metal silicide film 48 .
  • Such layers may include, without limitation, a layer of undoped glass 60 (silicon dioxide), a layer of doped glass 62 , and a metal layer 64
  • the doped glass layer 62 may comprise borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG), for example.
  • the additional layers may be grown, or deposited by physical deposition (e g, sputtering) or formed by any other suitable technique, and are generally etched to their final dimensions and form by plasma etching. As mentioned hereinabove, high energy electrons from UV light photons generated by the sputtering and etching may cause charge to be accumulated in the edges 50 .
  • a protective layer 52 is applied over at least a portion of the polycide structure of polysilicon layer 44 and metal silicide film 48
  • the protective layer 52 may be applied prior to the formation of the additional layers 60 and 62 .
  • the protective layer 52 may be applied over additional layers 60 and 62 , and prior to tile formation of the metal layer 64 , as seen in FIG. 3 .
  • the protective layer 52 has the property of absorbing electromagnetic wave energy, such as but not limited to UV light, and serves as a protective mask that may prevent high energy photons from reaching the polycide structure of polysilicon layer 44 and metal silicide film 48 while sputtering aid etching the additional layers 60 and 62 , or metal layer 64 .
  • protective layer 52 may absorb electromagnetic wave energy having a wavelength shorter than visible light.
  • the protective layer 52 comprises an ultraviolet absorber, e g., a nitride layer Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the sputtering or plasma etching from inducing stress in the polycide structure of polysilicon layer 44 and/or metal silicide film 48 , or gate stress in the ONO layer 46 .
  • a nitride layer Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the sputtering or plasma etching from inducing stress in the polycide structure of polysilicon layer 44 and/or metal silicide film 48 , or gate stress in the ONO layer 46 .
  • One preferred nitride comprises a silicon-rich silicon nitride alloy, such as Si 3+x N 4 , wherein x>0.
  • the silicon-rich silicon nitride alloy may be hydrogenated and/or amorphous.
  • Tile nitride layer is preferably relatively very thick, such as without limitation, in the range of 50-1000 ⁇ .
  • the nitride layer may be formed using any suitable technique, such as but not limited to, a low pressure chemical vapor deposition technique (LPCVD).
  • LPCVD low pressure chemical vapor deposition technique
  • the protective layer 52 may comprise a layer of highly resistive undoped polysilicon
  • the layer of undoped polysilicon may be deposited using any suitable technique, such as but not limited to, CVD methods.
  • the undoped polysilicon layer is preferably relatively very thin, such as without limitation, in the range of 30-600 ⁇ .
  • the undoped polysilicon layer preferably has a high resistance, such as without limitation, at least 1 G ⁇ .
  • the additional layers 60 and 62 may be formed over protective layer 52 , such as but not limited to, by sputtering and etching If the protective layer 52 has been formed over the additional layers 60 and 62 , the metal layer 64 may be deposited or etched over protective layer 52 , for example.
  • the protective layer 52 may have a high electrical resistivity so as to prevent leakage from one contact to another contact (or from one via to another via) formed in the device 43 . The protective layer 52 may thus prevent electrical stress and gate stress problems, as well as prevent leakage between contacts in device 43 .

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  • Crystallography & Structural Chemistry (AREA)
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Abstract

A method protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, die protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light. A device constructed in accordance with the method is also disclosed.

Description

    FIELD OF THE INVENTION
  • The present invention relates to the manufacture of semiconductor products in general, and particularly to protection against damage to semiconductor circuits from effects of electromagnetic wave energy generated during an etch process.
    • BACKGROUND OF THE INVENTION
  • During the manufacture of semiconductor products, layers of material are laid down or grown. Some layers are then etched, to produce die desired shapes of transistors, metal lines, and other microelectronics devices. When the processing has finished, a functioning chip is produced. If the chip contains a memory array, it typically has a plurality of memory transistors that may be programmed or erased. For example, the memory transistors may be floating gate transistors, nitride read only memory (NROM) transistors, silicon oxide-nitride oxide-silicon (SONOS) transistors, and any other non-volatile memory metal oxide semiconductor (MOS) devices capable of storing charge. Unfortunately, the manufacturing process may have some undesirable side effects. For example, in MOS technology, the charging of active elements during the manufacturing process may alter die device's characteristics or even damage them.
  • Reference is now made to FIG. 1, which illustrates a typical cross-section of an MOS or complementary MOS (CMOS) transistor wafer It is typically formed of a gate oxide 10 over which is a polysilicon element 12 On either side of tile gate oxide 10 are field oxides 14 which are much thicker than the gate oxide 10 Typically, tie polysilicon element 12 also spreads over the field oxides 14 A more advanced process may have trench isolation instead of field oxides but the effects discussed hereinbelow are the same in such a case.
  • During manufacture, die field oxides 14 are first produced on a substrate 8, after which the gate oxides 10 are grown. A layer of polysilicon is laid over the oxides 10 and 14, and then etched to the desired shapes, such as by employing a shaped photoresist layer 15. The etching process typically involves placing a plasma 16, as is now explained.
  • The etching process may be carried out by many methods, however, plasma based processes such as plasma enhanced chemical vapor deposition (CVD) and reactive ion etching (RIE) are very common. Typically, energy for etching is generated by coupling radio frequency (RF) electromagnetic energy to a plasma 16. The RF energy may be supplied by an RF generator coupled to a power supply In FIG. 1, the etching process involves placing plasma 16 between die transistor and a electrified plate 18 connected to a high voltage source, and electrically connecting a second electrified plate 20 to the substrate 8
  • Plasma may generate ultraviolet (UV) photons, UV photons may also be generated during deposition of metal layers, such as in sputtering techniques. High energy electrons associated with the UV photons may charge the transistor. More specifically, since polysilicon is a conductive material, the polysilicon element 12 may become charged by the high energy photons. This is known as the “charging effect” The charging effect is not generally a problem in conventional floating gate transistors because the excess charge may be erased. However, it may degrade tile gate oxide as is now explained.
  • The more charge the polysilicon element 12 attracts, the greater the voltage drop between die polysilicon element 12 and the substrate 8 If the voltage drop is high enough, it induces Fowler-Nordheim (F-N) tunneling of charge from the substrate 8 to the polysilicon element 12, via the gate oxide 10, as indicated by arrows 24 Since the field oxides 14 are quite thick, no F-N tunneling generally occurs through them Unfortunately, F-N tunneling may cause breakdown of tile gate oxide 10, especially if the gate oxide 10 is quite thin. It is appreciated that, once the gate oxide 10 has broken down, the transistor will not function.
  • Solutions are known for handling the gate oxide degradation problem of CMOS and floating gate transistors. The extent of the F-N tunneling is a function of the size of the polysilicon element 12, the area of the gate oxide 10 and its thickness. As long as the area of polysilicon over the field oxides 14 is no larger than K times die area over the the gate oxides 10 (where K, called the “antenna ratio”, varies according to tie specific manufacturing process), the F-N tunneling will not occur Alternatively, the total charge passing through the oxide will be small enough not to cause breakdown of the oxide. Accordingly, the account of F-N tunneling may be reduced by reducing the area of die field oxide relative to the area of the gate.
  • In NROM devices, similar to the CMOS and floating gate memory devices, the abovementioned charging effect may be reduced by various techniques, such as tie reduction of the antenna ratio K and adding discharge devices along the poly lines. Such techniques are discussed in applicant/assignee's U.S. patent application Ser. No. 09/336,666, filed Jun. 18, 1999 and entitled “Method and Circuit for Minimizing the Charging Effect During Manufacture of Semiconductor Devices”.
  • However, in NROM devices, yet another problem may occur, wherein excess charge may accumulate along the edges of word lines. The excess charge is not uniform, and increases the threshold voltage V1 of the cell. The increase in threshold voltage being non-uniformly across the device width, may degrade the reliability and endurance of tie cell In N-ROM cells, programmed bits in the charge-trapping nitride layer are generally erased by hot hole injection. However, hot hole injection may only erase charge next to the source/drain junctions The charge along the word line edge, far from the source/drain junctions, may not generally be erased. It would therefore be desirable to prevent UV photon-induced charge effect in die word-line edges of NROM devices
    • SUMMARY OF THE INVENTION
  • The present invention seeks to provide methods and apparatus for protecting against plasma-induced damage to semiconductor circuits The invention may be used in any non-volatile memory device, particularly a memory device with a non-conducting charge layer The invention will be described with reference to an NROM device, although it is understood that the invention is not limited to NROM devices.
  • In accordance with a preferred embodiment of the present invention, a protective layer is formed in the NROM device over a polycide structure (e.g., a word line). The protective layer may comprise an ultraviolet absorber, e.g, a nitride layer Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the plasma etching from inducing stress in the polysilicon layer or gate stress in al oxide-nitride-oxide (ONO) layer. One preferred nitride comprises a thick silicon-rich silicon nitride alloy. Additionally or alternatively, the protective layer may comprise a layer of highly resistive undoped polysilicon.
  • There is thus provided in accordance with a preferred embodiment of the present invention a method for protecting a non-volatile memory device, die method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light
  • There is also provided in accordance with a preferred embodiment of the present invention a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and a protective layer formed over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light.
  • In accordance with a preferred embodiment of the present invention the protective layer includes an ultraviolet absorber.
  • Further in accordance with a preferred embodiment of the present invention the protective layer includes a nitride layer.
  • 5 Still further in accordance with a preferred embodiment of the present invention the nitride layer includes a silicon-rich silicon nitride alloy.
  • In accordance with a preferred embodiment of the present invention tile nitride layer includes Si3+xN4, wherein x>0.
  • Further in accordance with a preferred embodiment of die present invention the nitride layer includes a hydrogenated silicon-rich silicon nitride alloy.
  • Still further in accordance with a preferred embodiment of tile present invention the nitride layer includes an amorphous silicon-rich silicon nitride alloy.
  • In accordance with a preferred embodiment of the present invention the protective layer includes a nitride layer with a thickness of 50-1000 Å.
  • Further in accordance with a preferred embodiment of the present invention the protective layer includes a layer of resistive undoped polysilicon.
  • Still further in accordance with a preferred embodiment of the present invention the protective layer of undoped polysilicon includes a resistivity of at least 1 GΩ.
  • In accordance with a preferred embodiment of the present invention the protective layer of undoped polysilicon includes a thickness of 30-600 Å.
  • Further in accordance with a preferred embodiment of the present invention at least one additional layer is formed over the protective layer.
  • Still further in accordance with a preferred embodiment of the present invention the at least one additional layer includes at least one of a layer of undoped glass, a layer of doped glass, and a metal layer
  • In accordance with a preferred embodiment of the present invention the polycide structure includes a polysilicon layer and a metal silicide film.
  • Further in accordance with a preferred embodiment of die present invention die polysilicon layer includes a polycrystalline silicon (polysilicon). The polysilicon layer may or may not be doped with a dopant.
  • Still further in accordance with a preferred embodiment of the present invention the metal silicide film includes at least one of a tungsten silicide film and a titanium silicide film.
  • In accordance with a preferred embodiment of the present invention the non-volatile memory device includes a nitride, read only memory (NROM) device, and die non-conducting charge trapping layer includes a nitride charge trapping layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will be understood and appreciated more fully from the following detailed description taken in conjuction with the appended drawings in which:
  • FIG. 1 is a schematic illustration of a prior art metal oxide semiconductor (MOS) transistor in a semiconductor chip during an etching operation;
  • FIG. 2 is a simplified illustration of a charging effect in an NROM non-volatile memory device; and
  • FIGS. 3 and 4 are simplified cross-sectional illustrations of application of a protective layer over portions of the NROM device of FIG. 2, in accordance with a preferred embodiment of the present invention, wherein FIG. 3 is a cross-section along poly lines and FIG. 4 is a cross-section of word lines between bit lines.
    • DETAILED DESCRIPTION OF THE PRESENT INVENTION
  • Reference is now made to FIG. 2, which illustrates a charging effect in an NROM non-volatile memory device 43, which includes one or more word lines (WL) 40 and bit lines (BL) 42 Bit lines 42 may be separated from each other by a distance LD. During etching and/or sputtering processes, portions of device 43, such as but not limited to, edges 50 of word line 40, may accumulate charge (indicated by dots along edges 50 in FIG. 2) due to the deleterious charge effect mentioned hereinabove.
  • Reference is now made to FIGS. 3 and 4, which illustrate cross-sections of the NROM non-volatile memory device 43. WL 40 may comprise a polycide structure, comprising for example, a lower polysilicon layer 44 and an upper layer formed of a metal silicide film 48 Polysilicon layer 44 may comprise without limitation a polycrystalline silicon (polysilicon), which may or may not be doped with a dopant such as phosphorus, for example. Metal silicide film 48 may comprise without limitation a tungsten silicide film or a titanium silicide film, for example.
  • The polycide structure of polysilicon layer 44 and metal silicide film 48 may be formed over an ONO layer 46 ONO layer 46 is also referred to as a nitride charge trapping layer. As seen in FIG. 3, bit line 42 may include a BL oxide layer 54 and a BL junction 56
  • Additional layers may be formed over polysilicon layer 44 and metal silicide film 48. Such layers may include, without limitation, a layer of undoped glass 60 (silicon dioxide), a layer of doped glass 62, and a metal layer 64 The doped glass layer 62 may comprise borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG), for example. The additional layers may be grown, or deposited by physical deposition (e g, sputtering) or formed by any other suitable technique, and are generally etched to their final dimensions and form by plasma etching. As mentioned hereinabove, high energy electrons from UV light photons generated by the sputtering and etching may cause charge to be accumulated in the edges 50.
  • In accordance with a preferred embodiment of the present invention, in order to prevent the change effect, a protective layer 52 is applied over at least a portion of the polycide structure of polysilicon layer 44 and metal silicide film 48 The protective layer 52 may be applied prior to the formation of the additional layers 60 and 62. Alternatively, the protective layer 52 may be applied over additional layers 60 and 62, and prior to tile formation of the metal layer 64, as seen in FIG. 3. The protective layer 52 has the property of absorbing electromagnetic wave energy, such as but not limited to UV light, and serves as a protective mask that may prevent high energy photons from reaching the polycide structure of polysilicon layer 44 and metal silicide film 48 while sputtering aid etching the additional layers 60 and 62, or metal layer 64. In general, protective layer 52 may absorb electromagnetic wave energy having a wavelength shorter than visible light.
  • In accordance with a preferred embodiment of die present invention, the protective layer 52 comprises an ultraviolet absorber, e g., a nitride layer Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the sputtering or plasma etching from inducing stress in the polycide structure of polysilicon layer 44 and/or metal silicide film 48, or gate stress in the ONO layer 46. One preferred nitride comprises a silicon-rich silicon nitride alloy, such as Si3+xN4, wherein x>0. The silicon-rich silicon nitride alloy may be hydrogenated and/or amorphous. Tile nitride layer is preferably relatively very thick, such as without limitation, in the range of 50-1000 Å. The nitride layer may be formed using any suitable technique, such as but not limited to, a low pressure chemical vapor deposition technique (LPCVD).
  • Additionally or alternatively, the protective layer 52 may comprise a layer of highly resistive undoped polysilicon The layer of undoped polysilicon may be deposited using any suitable technique, such as but not limited to, CVD methods. The undoped polysilicon layer is preferably relatively very thin, such as without limitation, in the range of 30-600 Å. The undoped polysilicon layer preferably has a high resistance, such as without limitation, at least 1 GΩ.
  • As seen in FIG. 4, if needed, there may be a spacer 49 between protective layer 52 and portions of polysilicon layer 44
  • If the protective layer 52 has been formed over metal silicide film 48, the additional layers 60 and 62 may be formed over protective layer 52, such as but not limited to, by sputtering and etching If the protective layer 52 has been formed over the additional layers 60 and 62, the metal layer 64 may be deposited or etched over protective layer 52, for example. The protective layer 52 may have a high electrical resistivity so as to prevent leakage from one contact to another contact (or from one via to another via) formed in the device 43. The protective layer 52 may thus prevent electrical stress and gate stress problems, as well as prevent leakage between contacts in device 43.
  • It will be appreciated by persons skilled in die art that tile present invention is not limited by what has been particularly shown and described herein above Rather the scope of the invention is defined by the claims that follow:

Claims (34)

1. A method for protecting a non-volatile memory device, the method comprising:
forming a non-volatile memory device comprising a polycide structure formed over a non-conducting charge trapping layer; and
forming a protective layer over at least a portion of said polycide structure, said protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light
2. The method according to claim 1 wherein said forming said protective layer comprises forming an ultraviolet absorber
3. The method according to claim 1 wherein said forming said protective layer comprises forming a nitride layer
4. The method according to claim 3 wherein said forming said nitride layer comprises forming a silicon-rich silicon nitride alloy.
5. The method according to claim 4 wherein said forming said nitride layer comprises forming a nitride layer comprising Si3+xN4, wherein x>0.
6. The method according to claim 3 wherein said forming said nitride layer comprises forming a hydrogenated silicon-rich silicon nitride alloy
7. The method according to claim 3 wherein said forming said nitride layer comprises forming an amorphous silicon-rich silicon nitride alloy
8. The method according to claim 1 wherein said forming said protective layer comprises forming a nitride layer with a thickness of 50-1000 Å.
9. The method according to claim 1 wherein said forming said protective layer comprises forming a layer of resistive undoped polysilicon.
10. The method according to claim 9 wherein said forming said protective layer of undoped polysilicon comprises forming a layer with a resistivity of at least 1 GΩ.
11. The method according to claim 9 wherein said forming said protective layer of undoped polysilicon comprises forming a layer with a thickness of 30-600 Å.
12. The method according to claim 1 and further comprising forming at least one additional layer over said protective layer.
13. The method according to claim 12 wherein said forming said at least one additional layer comprises forming at least one of a layer of undoped glass, a layer of doped glass and a metal layer
14. The method according to claim 12 and further comprising plasma etching said at least one additional layer with said protective layer making at least a portion of said polycide structure.
15. The method according to claim 1 wherein said forming said non-volatile memory device comprises forming said non-volatile memory device with a polycide structure comprising is a polysilicon layer and a metal silicide film.
16. A non-volatile memory device comprising:
a polycide structure formed over a nonconducting charge trapping layer; and
a protective layer formed over at least a portion of said polycide structure, said protective layer being adapted to absorb electromagnetic wave energy leaving a wavelength shorter than visible light.
17. The device according to claim 16 wherein said protective layer comprises an ultraviolet absorber.
18. The device according to claim 16 wherein said protective layer comprises a nitride layer.
19. The device according to claim 18 wherein said nitride layer comprises a silicon-rich silicon nitride alloy
20. The device according to claim 19 wherein said nitride layer comprises Si3+xN4, wherein x>0.
21. The device according to claim 18 wherein said nitride layer comprises a hydrogenated silicon-rich silicon nitride alloy
22. The device according to claim 18 wherein said nitride layer comprises an amorphous silicon-rich silicon nitride alloy.
23. The device according to claim 16 wherein said protective layer comprises a nitride layer with a thickness of 50-1000 Å.
24. The device according to claim 16 wherein said protective layer comprises a layer of resistive undoped polysilicon.
25. The device according to claim 24 wherein said protective layer of undoped polysilicon comprises a resistivity of at least 1 GΩ.
26. The device according to claim 24 wherein said protective layer of undoped polysilicon comprises a thickness of 30-600 Å.
27. The device according to claim 16 and further comprising at least one additional layer formed over said protective layer
28. The device according to claim 27 wherein said at least one additional layer comprises at least one of a layer of undoped glass, a layer of doped glass, and a metal layer
29. The device according to claim 16 wherein said polycide structure comprises a polysilicon layer and a metal silicide film.
30. The device according to claim 29 wherein said polysilicon layer comprises a polycrystalline silicon (polysilicon).
31. The device according to claim 29 wherein said polysilicon layer is doped with a dopant.
32. The device according to claim 29 wherein said polysilicon layer is undoped.
33. The device according to claim 29 wherein said metal silicide film comprises at least one of a tungsten silicide film and a titanium silicide film.
34. The device according to claim 16 wherein said non-volatile memory device comprises a nitride, read only memory (NROM) device, and said non-conducting charge trapping layer comprises a nitride charge trapping layer.
US11/490,483 2001-11-19 2006-07-20 Protective layer in memory device and method therefor Abandoned US20070032016A1 (en)

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