KR20010045232A - Method for manufacturing flash memory cell and the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory cell using a multi level cell technology capable of overcoming an increase in chip size, and a method of manufacturing the same. A flash memory cell comprised of a select transistor and a memory transistor, wherein the select transistor is comprised of an SNOSO nonvolatile memory cell, and the memory transistor is comprised of an ETOX memory cell.

Description

Flash memory cell and method of manufacturing the same {Method for manufacturing flash memory cell and the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor memory device, and more particularly, to a flash memory cell using a multi level cell technology capable of overcoming an increase in chip size and a method of manufacturing the same.

At present, in terms of process technology, Nonvolatile Semiconductor Memories (NVSM) are largely divided into Floating Gate series and MIS (Metal Insulator Semiconductor) series in which two or more dielectric layers are stacked in two or three layers. do.

The floating gate series implements memory characteristics using potential wells, and is representative of the EPROM Tunnel Oxide (ETOX) structure, which is currently widely used as a flash electrically electrically programmable read only memory (EEPROM).

On the other hand, the MIS series performs a memory function by using traps present at the dielectric bulk, the dielectric film-dielectric film interface, and the dielectric film-semiconductor interface. A typical example is the MONOS / SONOS (Metal / polysilicon Oxide Nitride Oxide Semiconductor) structure, which is mainly applied as a flash EEPROM.

Hereinafter, a conventional flash memory cell will be described with reference to the accompanying drawings.

1 is a structural cross-sectional view of a MONOS / SONOS memory device of a conventional MIS series nonvolatile semiconductor memory device.

As shown in FIG. 1, the first oxide film 12, the nitride film 13, the second oxide film 14, and the gate electrode 15 are sequentially stacked in a predetermined region on the P-type semiconductor substrate 11. The source region 16 and the drain region 17 are formed in the surface of the semiconductor substrate 11 on both sides of the structure.

In this case, the first oxide film 12 is used as a tunneling oxide film, and the second oxide film 14 is used as a blocking oxide film.

That is, a first oxide film 12 is formed on the semiconductor substrate 11, and a nitride film 13 and a second oxide film 14 are sequentially formed on the first oxide film 12 to form an oxide nitride oxide (ONO) structure. To form.

Subsequently, polysilicon doped with impurities is formed on the semiconductor substrate 11 on which the ONO structure is formed by chemical vapor deposition (hereinafter, referred to as CVD), and the gate electrode 15 is formed through a photo and etch process. ).

N-type impurity ions are implanted using the selectively removed gate electrode 15 as a mask to form a source region 16 and a drain region 17 on the surface of the semiconductor substrate 11.

2 is a structural cross-sectional view of a memory device having an ETOX structure in a conventional floating gate series nonvolatile semiconductor memory device.

As shown in FIG. 2, the tunneling oxide film 22, the floating gate 23, the dielectric film 24, and the control gate 25 are sequentially stacked in a predetermined region on the p-type semiconductor substrate 21. The source region 26 and the drain region 27 are formed in the surface of the semiconductor substrate 21 on both sides of the stacked structure.

That is, an oxide film having a thickness of 100 mV or less is formed on the semiconductor substrate 21, a first polysilicon layer having a thickness of 2000 mV is formed on the oxide film, and a dielectric film 24 of 200 mV is sequentially formed on the first polysilicon layer. do.

Subsequently, a second polysilicon layer of 2000 microseconds is formed on the dielectric film 24, and then selectively removed in order using a photo and etching process to control the gate 25, the dielectric film 24, and the floating gate 23. ), The tunneling oxide film 22 is formed, and the N-type impurity ions are implanted using the stacked structure as a mask to form the source region 26 and the drain region 27 in the surface of the semiconductor substrate 21. Form.

The first polysilicon layer formed between the tunneling oxide film 22 and the dielectric film 24 is a floating gate 23 because it is electrically isolated, and is formed on the dielectric film 24 on the floating gate 23. The control gate 25 applies a sufficiently large voltage to the second polysilicon layer to switch the storage state.

In addition, the dielectric film 24 existing between the control gate 23 and the floating gate 25 is an IPD (Inter Polysilicon Dielectric), and the oxide film formed on the semiconductor substrate 21 is a tunneling oxide film 22.

When applying a conventional memory cell having the ETOX structure as a flash EEPROM, 1-transistor and 1-cell type, 2-transistor and 1-cell ) There are two types.

The 1-transistor and 1-cell types have a small unit cell area, which facilitates high integration, and the program mechanism is fast due to the Channel Hot Electron (CHE) method. However, the biggest problem is the degradation of reliability due to over-areas and disturbs.

A solution for overcoming the over-area and disturb problem is a flash memory cell having a two-transistor and a one-cell type.

That is, FIG. 3 is a structural cross-sectional view showing a conventional flash memory cell having a 2-transistor and a 1-cell type.

As shown in FIG. 3, the MOS transistor 30a and the ETOX memory cell 30b are connected in series so as to have a predetermined interval on the semiconductor substrate 31.

The MOS transistor 30a is used as a select transistor and the ETOX memory cell 30b is used as a memory transistor.

In the conventional manufacturing process of a flash memory cell having the above structure, a first oxide film 32 is formed on a semiconductor substrate 31, and a polysilicon layer is formed on the first oxide film 32 by CVD. The floating gate 33 is formed through the photolithography and etching processes of the polysilicon layer.

Subsequently, a second oxide layer 34 is simultaneously formed on the semiconductor substrate 31, and a second polysilicon layer is formed on the second oxide layer 34. The gate electrode of the MOS transistor is formed through a photo and etching process. 35a) and the control gate 35b of the ETOX memory cell are formed simultaneously.

Then, impurity ions are implanted into the entire surface using the gate electrode 35a of the MOS transistor and the control gate 35b of the ETOX memory cell as a mask, so that the source region 36 and the drain region 37 are formed in the surface of the semiconductor substrate 31. ), The MOS transistor 30a and the ETOX memory cell 30b are formed in series on the same semiconductor substrate 31.

However, there are the following problems in the conventional flash memory cell as described above.

First, the 1-transistor and 1-cell type flash memory cells have low cell efficiency and complexity due to reliability degradation such as over-area and disturb and additional circuit insertion to solve them.

Second, the two-transistor and one-cell type flash memory cells have a large cell area, which makes high integration difficult.

Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to improve over-area and disturb problems, and to provide a high reliability, high density flash memory cell having a small cell area per bit, and a method of manufacturing the same. .

Another object of the present invention is to provide a flash memory cell employing a select transistor having a simple structure, easy array configuration, excellent performance, and various functions, and a method of manufacturing the same.

1 is a structural cross-sectional view of a MONOS / SONOS memory device of the conventional MIS series nonvolatile semiconductor memory device

2 is a structural cross-sectional view of a memory device having an ETOX structure in a conventional floating gate series nonvolatile semiconductor memory device;

3 is a structural cross-sectional view showing a conventional flash memory cell having a 2-transistor and a 1-cell type;

4 is a structural cross-sectional view showing a flash memory cell according to the present invention having a 2-transistor and a 1-cell type;

5A through 5E are cross-sectional views illustrating a method of manufacturing a flash memory cell according to the present invention having a 2-transistor and a 1-cell type.

Explanation of symbols for main parts of the drawings

41 semiconductor substrate 42 tunneling oxide film

43: floating gate 44,45,46: ONO film

47a: gate electrode 47b: control gate

48: source region 49: drain region

A flash memory cell according to the present invention for achieving the above object is a flash memory cell composed of a select transistor and a memory transistor configured in series at regular intervals on a semiconductor substrate, wherein the select transistor is a SNOSO nonvolatile memory. And a memory transistor comprising an ETOX memory cell.

In addition, a method of manufacturing a flash memory cell according to the present invention for achieving the above object comprises the steps of forming a floating gate through a tunneling oxide film in a predetermined region on the semiconductor substrate, the front surface of the semiconductor substrate including the floating gate Sequentially forming an ONO film and a conductive layer, selectively removing the conductive layer and the ONO film to simultaneously form a control gate and a gate electrode, a source region in the surface of the semiconductor substrate on both sides of the gate electrode and the control gate; And forming a drain region.

Hereinafter, a flash memory cell and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a structural cross-sectional view showing a flash memory cell according to the present invention having a 2-transistor and a 1-cell type.

As shown in FIG. 4, the SONOS nonvolatile memory cell 40a and the ETOX memory cell 40b are configured in series on the semiconductor substrate 41.

The SONOS nonvolatile memory cell 40a is used as a select transistor, and the ETOX memory cell 40b is used as a memory transistor.

That is, in the SONOS nonvolatile memory cell 40a, the first oxide film 44, the nitride film 45, the second oxide film 46, and the gate electrode 47a are sequentially stacked in a predetermined region on the P-type semiconductor substrate 41. The source region 48 and the drain region 49 are formed in the surface of the semiconductor substrate 41 on both sides of the stacked structure.

The ETOX memory cell 40b has a tunneling oxide film 42, a floating gate 43, a first oxide film 44, a nitride film 45, and a second oxide film 46 in a predetermined region on the p-type semiconductor substrate 41. The control gates 47b are sequentially stacked, and a source region 48 and a drain region 49 are formed in the surface of the semiconductor substrate 41 on both sides of the stacked structure.

5A through 5E are cross-sectional views illustrating a method of manufacturing a flash memory cell according to the present invention.

As shown in FIG. 5A, a tunneling oxide film 42 is formed on the semiconductor substrate 41, and a first polysilicon layer 43a doped with impurities by the CVD method is formed on the tunneling oxide film 42. .

As shown in FIG. 5B, the floating gate 43 is formed by selectively removing the first polysilicon layer 43a and the tunneling oxide layer 42 through a photo-etching process.

As shown in FIG. 5C, ONO films 44, 45, and 46 in which an oxide film, a nitride film, and an oxide film are sequentially stacked on the entire surface of the semiconductor substrate 41 including the floating gate 43. ), And a second polysilicon layer 47 is formed on the ONO films 44, 45 and 46.

As shown in FIG. 5D, the control gate 47b of the ETOX cell and the gate of the SONOS nonvolatile memory cell are subjected to the photolithography and etching processes to the second polysilicon layer 47 and the ONO films 44, 45, and 46. The electrode 47a is formed at the same time.

Here, the ONO films 44, 45, and 46 formed on the floating gate 47b and the control gate 47a are used as dielectric films, and ONO formed between the gate electrode 47a and the semiconductor substrate 41. The films 44, 45 and 46 are formed of gate insulating films.

As shown in FIG. 5E, source / drain impurity ions are implanted into the entire surface using the gate electrode 47a and the control gate 47b as a mask, so that the source region 48 is formed in the surface of the semiconductor substrate 41. And drain region 49 is formed.

As described above, the flash memory cell of the present invention having a two-transistor and one-cell type using a SONOS nonvolatile memory cell as a select transistor and a method of manufacturing the same have the following effects.

First, by using a multi-level technique for two-transistor and one-cell type, it is possible to provide a flash memory cell capable of high reliability and high integration without over-area problems and having a small unit cell area.

Second, because the cell structure is simple, the existing CMOS process can be applied as it is without adding a separate process, so it can be used as an embedded product as well as a standalone product.

Claims (5)

A flash memory cell composed of a select transistor and a memory transistor configured in series at regular intervals on a semiconductor substrate, Wherein said select transistor is comprised of an SNOSO nonvolatile memory cell and said memory transistor is comprised of an ETOX memory cell. The semiconductor device of claim 1, wherein the SONOS nonvolatile memory cell comprises a source region and a drain region formed by sequentially stacking ONO films and gate electrodes in a predetermined region on a semiconductor substrate, and formed in a semiconductor substrate surface on both sides of the stacked structure. Flash memory cell, characterized in that. 2. The EATOX memory cell of claim 1, wherein a tunneling oxide film, a floating gate, an ONO film, and a control gate are sequentially stacked in a predetermined region on the semiconductor substrate, and a source region and a drain region formed in the semiconductor substrate surfaces on both sides of the stacked structure. Flash memory cell comprising a. Forming a floating gate through a tunneling oxide film in a predetermined region on the semiconductor substrate; Sequentially forming an ONO film and a conductive layer on the entire surface of the semiconductor substrate including the floating gate; Selectively removing the conductive layer and the ONO film to simultaneously form a control gate and a gate electrode; And forming a source region and a drain region in the surface of the semiconductor substrate on both sides of the gate electrode and the control gate. 2. The method of claim 1, wherein the ONO film between the floating gate and the control gate is used as a dielectric film, and the ONO film between the gate electrode and the semiconductor substrate is used as a gate insulating film.