SU1653167A1 - Device for binary data reception - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve noise immunity. The device contains a decoder 1, low-pass filters 2 and 3, adders 4 and 5, comparison block 6, maximum analyzer 7, clock generator 8, counter 9, permanent memory node 10, elements 11, register 12, element, moment OR 13 and keys 14 and 15. The reception of binary information consists in the logical processing of signals by optimizing on the basis of a comparison of the values of the reception quality criterion for all possible variants. At the same time, the probability of correct reception of the P ,,, signal 1 is maximized, with the probability of false alarms less than the maximum permissible value. 1 il. 3 (I

Description

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The invention relates to radio engineering and can be used in binary data transmission systems.

The purpose of the invention is to improve noise immunity with

The drawing shows a structural electrical circuit of the proposed device with

| The device for receiving binary information contains a decoder 1, the first and second filters 2 and 3 of the lower frequencies, the first and second adders 4 and 5, the comparison unit 6, the maximum analyzer 7, the clock pulse generator 8, the counter 9, the permanent storage node 10, the elements And 11, register 12, the element OR 13 and the first and second keys 14 and 15,

The device works as follows.

Each of the n binary input signals is a sequence of information symbols that are not known in advance, and known symbols O and 1, the arrival times of which are designated by a synchronous pulse (for example, these are pulses intended to provide frame synchronization). Known symbols are used to estimate the parameters characterizing the joint state of all information channels. For this, the probabilities G are estimated.

These occurrences of each of the possible 2 code combinations in transmission 1 and O, respectively: reference pulses (with known amplitude and duration) appear on the outputs of the decoder 1 with average amplitude and duration and are averaged by 2 and 3 lower frequencies, so that at the outputs of the latter, slowly varying voltages are formed, which characterize the values of the probabilities P |, - and P0 ,,, 1 1-2 outputs associated with filters 2 and low frequencies 3 appear only when a sync pulse is present at the control input of the decoder O and 1 respectively .

Low-pass filters 2 are designed to average the input pulse sequences and form slowly varying voltages at the output that serve as an estimate of the probabilities P,; o Filters 2 and T of low frequencies should have a bandwidth of vnaphnch-frequencies, much more

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narrower than the frequency of the symbols O and 1, on the basis of which the training of the entire device is realized. The implementation of filters 2 and 3 of the lower frequencies is possible in the form of integrating KS circuits or the simplest active filters.

The switches 14 and 15, when they appear at the control inputs of logical 1, transmit the input voltage without distortion to the output.

Adders 4 and 5 sum the input voltages "

Comparison unit 6 generates a 1 or O signal at the output if the input voltage from the side of adder 4 is not greater (or more) of the reference voltage UQ proportional to the level of permissible probability of false positives PQ, I Perm,

Analyzer 7 is designed to form at the output of signal 1 at the instant of action at the input of a maximum pulse in a periodic sequence of pulses.

The combination of the decoder 1, the elements And 11 and the element OR 13 allows

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implement any of the 2 possible logical functions and binary variables, supplying the corresponding 2H control signals to the inputs of elements 11 and 11. In order to select the only optimal logical processing option, all signals controlling the type of logical processing and stored in the permanent memory node 10 are alternately extracted from there and connected to the inputs of the voltage adders 4 and 5, corresponding to the probabilities P, tl

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to obtain the values of the reception quality criterion: at the output of the adder 4, a voltage appears proportional to the probability P /, j-ro of the variant of logical processing, and at the output of the adder 5, proportional to the probability ,, j 1-М, constant capacity of the storage node 10 "In this case, the criterion of the optimality of the type of logical processing is the maximum likelihood of correct reception of a logical 1 (-, 1" air) with an acceptable level of false failures due to a distortion of logical O (Oro-mdop) code combination corresponding to all possible logical processing options, a periodic sequence of pulses is formed at the output of adder 5, the maximum of which corresponds to the optimal variant (provided that the corresponding pulse at the output of adder 4 is less than the reference voltage U0 corresponding to the permissible probability).

The maximum analyzer 7 generates at its output a pulse at the moments when the maximum voltage of the optimal logic processing variant appears at the input. The control code combination of this variant from the outputs of the constant memory node 10 is entered into the register 12 and stored there. Thereafter, the type of logical processing does not change until the joint state of the n branches of the receive diversity changes.

Claims (1)

Invention Formula A device for receiving binary information, comprising a decoder, an OR element and a permanent storage node, characterized in that, in order to improve the noise immunity, AND elements are first introduced into it 25 P and second low-pass filters, first and second keys, two adders, comparison unit, maximum analyzer register, counter and clock generator, the output of which through the counter is connected to the inputs of a permanent storage node whose outputs are connected to the first inputs of the first and second keys and with the first inputs of the register, the outputs of which are connected to the first inputs of the elements And, the second inputs of which are connected to the first outputs of the decoder, the second outputs of which are connected through the corresponding first low-pass filters the second inputs of the corresponding first keys, the outputs of which through the first adder are connected to the input of the comparator unit, the output of which is connected to the first input of the maximum analyzer, the output of which is connected to the second input of the register, while the third outputs of the decoder through 5 the corresponding second low-pass filters are connected to the second inputs of the corresponding second keys, the outputs of which are connected to the inputs of the second adder, the output of which is connected to the second input of the maximum analyzer, and the outputs of the elements AND are connected to the input ode element OR. 0