SU1367012A1 - Operational device - Google Patents

Abstract

The invention relates to the field of computing and can be used as part of universal or specialized computers for performing arithmetic logic operations on floating point operations. The purpose of the invention is to expand the functionality of the device in terms of the additional execution of subtraction and division operations on floating-point operands, AND, OR, NOT logical operations, addition modulo two, as well as speeding up due to the asynchronous operation mode. The operating device contains the register 1 of the operation code, the registers 2, 3 of the first and second operands, the first and second combinational shifters 4, 5, the arithmetic logic unit 6 of the mantiss processing, the multiplication multiplier 7, the divisor 8, the first switch 9, the encoder a la zeros , the normalizer 1 1, the arithmetic logic unit 12 for processing the subroutines, the second switch 13, the arithmetic logic unit 14 for correcting the result order, the result register 15 and the control unit 16 with the corresponding connections. Dith arithmetic and logical operations on operands with the plane. comma in asynchronous mode. 4kn. H i (L with Od, i 9utt

Description

The invention relates to computing and can be used as part of universal or specialized computers for performing arithmetic logic operations on floating-point operands.

The purpose of the invention is to expand the functionality of the device in terms of additional performance of subtraction and division operations on floating-point operands, AND, OR, NOT logical operations, modulo-two, as well as speeding up due to the asynchronous execution mode.

Fig, 1 shows a functional diagram of the operating device; Fig. 2 is a functional diagram of the device shifters; FIG. 3 is a functional diagram of the device zero encoder; FIG. A is a functional block diagram of a device control unit.

The operating device contains a register 1 operation code, register 2 of the first operand, register 3 of the second operand, the first and second combination

the second information input of the second switch J3, the third information input of which is connected to the information output of the ALU 52 processing orders and the second information inputs of the shifters 4 and 5, the outputs of the ALU 6 mantiss processing, the multiplier 7 and divider b are connected to the information

of the first switch 9, the information output of which is connected to the input of the encoder 10, the first information input of the normalizer I and the first information input

result register 15, the output of the higher information bit of the first switch 9 is connected to the transfer input of the ALU 14 correction of the result order and the first control input

the normalizer 11, the second control input of the normalizer 11 is connected to the resolution inputs of the shifters 4 and 5 and to the bus 57 of the logical unit of the device, the first information input

8 of the device is connected to the information input of the operation code register 1, the write enable input of which is connected to the first control input 19

shifters 4 and 5, arithmetic-loop devices, information output real device (ALU) 6 of processing About result Gistra 15 is connected to permiss, combinational multiplier 7, register information inputs registrar 8, first switch 9, cipher - Ditch 2 and 3 of the first and second operands, rarator 10 of the number of zeros, the normalizer, the second information input 20 of the device P, the ALU 12 process the order, the second is connected to the second information terminal, the switch 13, the ALU 14 of the correction. 35 of register 2 of the first operand, in the order of the result; register 15 is the result of the first resolution of the entry for recording and the control unit 16, and is connected to input 21 of the resolution

n, - bit outputs of register 2 of the first operand (where n;, is the number of bits of the mantissa of the operand) are connected to the first information input of the first shifter 4, to the first information input of the multiplier 7, to the first information input of the divider 8, n, the first outputs of register 2 of the first operand (where Pr is the number of bits of the order of the operand) are connected to the first information input of the ALU 12 order processing and to the first information input of the second communicator 13, n „-digit outputs of the register 3 of the second operand are connected with the first information in the course of the second shifter 5, with the second information input multiplier 7 and with the second information. the input of the divider 8, P1 (1-bit outputs of the register 3 of the second operand are connected to the second information input of the ALU 12 processing orders and

records on its first information input, second recording permission

40 of the register 2 of the first operand is connected to the input 22 of the recording resolution via its second information input, the third information input 23 of the device is connected to the second information input;

45 of the second operand register 3, the first write enable input of which is connected to the write enable input 24 at its first information input, the second write enable input of the second operand register 3 is connected to the write enable input 25 of its second information input, the control input device 26. - is not connected with the starting input of control unit 16; the decoding input of the operation code of which is connected to the output of register 1 of the operation code; the input of determining the operand sign of control unit 16 is connected to the sign output of ALU 12

processing the orders, the resolution enable input of the result of the control unit 16 is connected to the output of the senior information bit of the first switch 9 and the first information input of the ALU 14 of the result order, the second information input of which is connected to the output of the second switch 13, the third information input The ALU 14 for adjusting the result order is connected to the output of the encoder 10 and, with the second, the information input of the normalizer 1.1, the input of the sign of the loss of significance of the mantissa of the control unit 16 is connected to the output the upper bit of the encoder 10, the control inputs of the first and second shifters 4 and 5 are connected to the first and second outputs of the control unit 16, the third output of which is connected to the control input of the order processing ALU 12, the fourth output of the control unit 16 is connected to the control input ALU 6 processing mantis, whose information inputs are connected to the outputs of the shifters 4 and 5, the control input of the second switch 13 is connected to the fifth output of the control block 16, the sixth output of which is connected to the control input of the first switch 9, t such as are for input of register 15 is connected to a seventh result output control unit 16, the eighth output being connected to house write enable register 15 and result in a yield of 27 the device is ready, the ninth output device 16 connected to the control unit yn

log in

the equalizing input of the ALU 14 adjustment is 40 ches zero, since the third (controlling) input of the ALU 14 receives the code by which the level of the logical zero at its output is generated.

Equal to the input of the ALU 14 enters the code by which the level of the logical zero is formed at its output.

Signal readiness

order of result, the output of the normalizer 1 is connected to the first information input of the result register 15, the output of which is connected to the output 28 of the device result, the output of the higher 45 at the output 27 of the device performs the discharge of the encoder 10 connected to the output as follows. 29 signs of loss of significance of a single signal to the starting input of the mantissa of the device, the first and second control unit 16 start the single outputs of the ALU 14 correcting the result order are connected to the outputs 30 and 31 signs of overflow order roystva, third output adjustment ALU 14 then result order soed1g- nen to a second input of the register 15 informatsionnm result, each of the shifters 4 and 5 comprises a plurality of AND gates 32, NOT element 33, decoder 34, group 35 elements and group OR

in AND OR communications.

4 36

corresponding to 10

g 15 20

The 10 zeros encoder contains a group of elements HE 37, a group of elements AND 38 and a group of elements OR 39 with corresponding links.

The control unit 16 comprises a decoder 40, a group of elements OR 41, a group of elements HE 42, a group of elements AND 43 and a group of one-vibrators 44 with corresponding links.

The device works as follows.

The operation code is recorded in register 1 with a control signal of a logical unit level at input 18, and operands are recorded by supplying them to registers 2 and 3 with device 20 and 23, or from the output of result register 15. The logical operations AND, OR, NOT, addition modulo 2 are performed when writing in register 1 codes 000, 001, 010 and 011, respectively. The control unit 16 forms corresponding output signals, as a result of which the first and second operands are transmitted through shifters 4 and 5 to the information inputs of the ALU 6, the control input of which receives the code of the operation to be performed. At the output of ALU 6, a 3g result is generated, which through switch 9 enters the first input of register 15 and is written to it at the end of the execution of the operation. In the lower order of register 15, logs are written.

thirty

This is a null zero, since the third (, control) input of the ALU 14 receives a code, by which the level of a logical zero is generated at its output.

Signal readiness

at the output 27 of the device performs the following: With the arrival of a single signal at the start input of the control unit 16, a one-shot 44.1 is triggered, the negative pulse at the output of which is equal to the execution time of the logical operation. At the end of this pulse, the result is recorded in register 15, and at output 27, a signal is generated by the level of a logical unit, indicating that the device is ready for the next operation,

Addition and subtraction over operations

A MD-2, MS-2 with a floating comma is executed when writing to register 1 codes 100 and 101, respectively. The control input of the ALU 12 is received from the third output of the control unit 16 of the control, including it in the subtraction mode. At the output of ALU 12, a difference is formed, on the sign of which one of the shifters 4 or 5 is included. If the sign is equal to O (the number Pj (Pv is positive), then O and 1 are formed at the outputs 1 and 2 of the control unit 16, respectively, resulting in a shift Mg,. If the sign is 1, the number of RD-RVs is negative), then at outputs 1 and 2 of control block 16, 1 and O are formed respectively, leading to shift Md, Shift Mg or Md is carried out to the right by the number of bits equal to the value of P -Ro, B

,etc

The ALU 6 is formed, respectively, the sum or difference of the mantis M and Mg, coming from the outputs of the shifters 4 and 5, the result from the output of the ALU 6 through the switch 9 enters the inputs of the encoder 10 of the number of zeros and the normalizer 11, The output of the encoder 10 generates a code equal to the number of consecutive zeros, starting with the most significant bit of the input word.

This code goes to the second input of the normalizer 11, the output of which forms the normalized value of the mantissa (the value of the most significant bit is 1), which is written to.

higher n, register bits 15. When adding, the result of the mantissa is possible (in the higher bit of the ALU, a unit is formed. In this case, the mantissa is normalized by shifting the result of the mantissa by one bit to the right by using the normalizer 11 ,.

The order of result is as follows.

If the RD-RV is O, then at the fifth output of the control block 16 a code 00 is generated and through the switch 13 to the second input of the ALU 14 enters Rd, If

R, -R

-; Oh, then at the fifth exit of the control block 16, a code 10 is formed and through a switch 13 to the second input of the ALU 14 Pg arrives. The first input of the ALU 14 receives the code from the output of the encoder 10 of the number of zeros. The third input of the ALU 14 receives a code that includes it in the subtraction mode, if the value of the Sign of loss of significance of the mantissa, formed on the second output of the cipher

Rattor 10 the number of zeros, not equal to one. If the value of the sign of loss of significance of the mantissa is equal to one, then the input to the ALU 14 is a code by which a signal at the output of the logic zero level is generated. If the result overflows (the unit value at the output of the erased bit of switch 9), then the third input of the ALU 14 receives a code, which in the ALU 14 adds the content of the second input with the unit to the transfer input of the ALU 14, The result from the output of ALU 14 is recorded in. Significant register bits 15, In ALU 14, the formation of signs of negative and positive overflow of the result order is also carried out. The unavailability time of the operations of addition and subtraction is set using the one-shot 44.2 of the control unit 16,

Floating point multiplication over

by operands A

Ml-2

AT

M.-2

Re,

performed when writing to code 1 in register 1; As a result, the mantissa Md, Mj are multiplied by multiplier 7, from the output of which the result goes through the switch 9 to the input of the normalizer 11 and the encoder 10, the number of zeros. Normalization of the mantissa of the product is performed in the same way as when performing addition and subtraction, and is recorded in the upper half of the bits of register 15, the order is defined as follows. The third input of the ALU 12 from the third output of the control block 16 receives a code, including

it is in addition mode P.

0

and Pg. The value of PA + PB through the switch 13 is fed to the second input of ALU 14, which is included in the subtraction mode, if the sign of loss of significance of the mantissa is not equal to 1. Otherwise, the ALU 14 is included in the logical zero mode. The result from the output of the ALU 14 is written to the low-level register bits 15, Time not ready. to perform the operation of multiplication is set using the single-shot 44.3 control unit.

Floating point division over. operands A Md-. In MV; 2, when 111 code is written to register 1, the mantissa M d is divided into mantissa M using divider 8, the result of which is

five

O through the switch Y is fed to the input of the normalizer 11. The normalization of the mantissa quotient is carried out in the same way as when performing addition and subtraction. The normalized mantissa of the quotient is recorded in the oldest bits of the register 15, the order of the quotient is defined as follows. The third input of the ALU 12 receives the code from the third control block 16, including it in the subtraction mode. The difference RD-RV from the output of the ALU 12 through the switch 13 enters the second input of the ALU 14, which functions in the same way as when performing addition and subtraction. From the output of the ALU, the 14th order of the private is recorded in the next 15 bits of the register 15

The details are set by the one-shot 44.4 of the control unit 16.

Thus, the introduction into the device of new elements — the register of the operation code of the second shifter, divider, two switches, the encoder of the number of zeros, the arithmetic logic unit of correction of the result and the distributor of control signals and the organization of new connections between the elements of the device the functionality of the device and increase its speed.

Claims (1)

Invention Formula An operational device containing (pc, + Pr-bit register of the first operand, (n ,, Pr - number of bits device is connected to the start input of the control unit, the decryption input of the operation code of which is connected to the output of the operation code register, the input of the opamp and the order of operands J, () -40 the bit register of the second operand, the first n-bit shifter, the first information input of which is connected respectively to the front, the bit output of the register of the first operand-45, and the inputs of the first group of PD |, -discharge multiplier, bit the first outputs of the first shifter are connected respectively to the inputs of the first group of the arithmetic logic unit processing mantis, the inputs of the second group of the multiplier are connected respectively to the n-digit outputs of the register It is connected to the output of the sign bit of the arithmetic logic order processing device, the input of the resolution resolution correction of the result of the control unit is connected to the output of the senior information bit of the first switch and the first control inputs of the normalizer. And the arithmetic logic correction of the result error , the input of the sign of loss of significance of the mantissa of the control unit is connected to the first output of the encoder of zeros and the output of the sign of the loss of significance of the mantissa of the device, the third output of the block and the control is connected to the control input of the arithmetic logic order processing unit, the fourth output of the control unit is connected to the control 50 the second operand, the pr-bit outputs of the registers of the first and second operands are connected respectively to the inputs of the first and second groups of the arithmetic-logic-order-processing unit, the normalizer, the first five 0 five the information input of which contains n, + 1 bits, and the output is connected to the front, information inputs of the result register, characterized in that, in order to expand the functionality of the device, in part, additional operations of subtraction and division on floating-point operands, logical AND, OR, NOT operations, adding two by one, as well as speeding up due to the asynchronous mode of performing operations, the operation code register is entered into it, information, whose input is the first information The device's input, the second n-bit shifter, the first information input of which is connected to the n-bit outputs of the second operand register, the second information input of the second shifter is connected to the second information input of the first shifter and the information output of the arithmetic logic order processing device , the control- the input of the second shifter is connected to the first step of the control unit, the control input of the first shifter is connected to the second output of the control unit; the discharge outputs of the second shifter are dineny respectively, to data inputs of the second group of arithmetic-logical processing device g, mantissas, the trigger input device is connected to the starting input of the control unit, the decoding input of the operation code of which is connected to the output of the operation code register, the input 0 five It is connected to the output of the sign bit of the arithmetic logic order processing device, the input of the resolution resolution correction of the result of the control unit is connected to the output of the senior information bit of the first switch and the first control inputs of the normalizer. And the arithmetic logic correction of the result error , the input of the sign of loss of significance of the mantissa of the control unit is connected to the first output of the encoder of zeros and the output of the sign of the loss of significance of the mantissa of the device, the third output of the block a control coupled to the control input of the arithmetic-logical processing device then orders of magnitude, the fourth control unit is connected to a control output w0 The mantissa arithmetic logic unit, the fifth output of the control unit is connected to the control input of the second switch, the sixth output of the control unit is connected to the control input of the first switch, the seventh output of the control unit is connected to the clock input of the result register, the eighth output the control unit is connected to the enable input of the record of the result register and to the device ready output the ninth output of the control unit is connected to the control input of the arithmetic logic unit the order of the result, P | ,, is the bit divider, the first and second information inputs of which are connected respectively to the bit outputs of the registers of the first and second operands, the information inputs of the first group of the first switch are connected respectively to the bit outputs of the arithmetic logic unit processing mantis, information inputs of the second group of the first switch are connected respectively to the bit outputs of the multiplier, information inputs of the third group of the first switch are connected respectively but with the bit outputs of the divider, the information output of the first switch is connected to the information input of the zero encoder, the first information input of the normalizer, and the first information input of the result register, the information inputs of the first group of the second switch are connected respectively to the PD output of the register the first operand, the information inputs of the second group of the second switch are connected respectively to the bit outputs of the arithmetic logic order processing device, the information The second inputs of the third group of the second switch are connected respectively to the Pr-bit outputs of the second operand register, the second output of the zero encoder is connected to the second information input of the normalizer, and to the inputs of the first group of the arithmetic logic-logical device for correcting the result; the inputs of the second group of which are connected to the outputs of the second the switch, the first and second outputs of the arithmetic logic device for correcting the order of the result are connected to the outputs of the signs of overflow of the order of the device 5, the third output the arithmetic logic unit of the result correction is connected to the Pr information input of the result register, the output of which is connected to the information output of the device and the first (p) -sized inputs of the registers of the first and second operands, the second (n, + Pr) -discharge the first operand register is connected to the second information device; the first input of the device; the second (p) discharge input of the second operand register is connected to the third information input of the device, which controls the input of the operation code register, is connected to the first control input home device, the second and third control inputs of which are respectively connected with the control inputs of the first operand register, the control inputs of the second operand registers are connected respectively with the fourth and fifth inputs of the gate device.