SU1266002A1 - Multichannel programmable analog-to-digital converter - Google Patents

Abstract

The invention relates to information and measurement technology and can be used in telemetry systems. The invention extends the functionality of the device and improves the measurement accuracy of the slowly varying signals by introducing into the device a control unit, an analog switch, a random access memory, a first analog memory block, a voltage converter — a code and a sync block, a programmable coefficient amplifier. gain, analog adder, summing amplifier, second analog storage unit, inverting divider, code-voltage converter and register. 1 hp f-ly, 3 ill.

Description

Yu

05 05

The invention relates to information measurement technology and can be used in telemetry systems for measurement on moving and rotating objects.

The purpose of the invention is to expand the functionality and improve the accuracy of measurement of slowly changing signals without a significant increase in size and power consumption.

FIG. 1 shows a structural electrical circuit of a multi-channel programmable analog-to-digital converter; in fig. 2 is a functional diagram of one of the possible options for constructing a control unit; in fig. 3 is a functional diagram of one of the possible options for building a communication unit.

Multichannel programmable analog-to-digital converter contains control block 1, input buses 2, analog switch 3, amplify; 1 4 with programmable gain, converter 5 code-for 1 time, summing amplifier 6, register 7, analog adder 8, inverting divider 9 , operational storage unit 10, first

11 and the second 12 analog storage blocks, voltage-code converter 13, synchronization unit 14, buses 15-17, respectively, commands, data and synchronization.

The recursive filter 18 consists of an analog adder 8, an inverting analog divider 9 and the first 11 and second

12 analog storage units, controlled by an opposite phase.

The control unit 1 can be implemented, for example, according to the functional electric circuit (Fig. 2) containing the command register 19, the decryptor 20, the second counter 21 of the number of cycles, the first inverter 22, the first counter 23 of the implementation size, the first 24 and the second 25 triggers, element 2I-OR 26, shaper 27 pulses, multiplexer 28, the second inverter 29 and the element OR 30.

The control and information inputs of the command register 19 are received from the synchronization unit 14 (FIG. 1), respectively, the shift pulses and the command code.

The synchronization unit 14 can be implemented, for example, according to the functional electrical circuit (Fig. 3), containing the first 31 and second 32 receivers, the use of 33 forming the pulses and the transmitter 34.

Multichannel programmable analog-to-digital converter works as follows.

Prior to the post of the first command, the control inputs of the amplifier 4 with programmable gain and register 7 from control unit 1 are supplied with control signals at which the voltage at the outputs of amplifier 4 with programmable gain and converter 5 is code-voltage converting into voltages The output code of register 7 is zero. In this case, the voltage at the output of summing amplifier 6 is also zero. This zero voltage is fed to the input of an analog-to-digital recursive filter 18 of the first order, in which the function of the delay line for one clock cycle is performed by the second analog storage unit 12, which is controlled in antiphase with the first analog storage unit 11, i.e. the first is in sample mode, the second is in storage mode, and vice versa. The zero voltage is memorized in both analog storage units 11 and 12 prior to the measurement. This is necessary to exclude a finite signal for the filter 18, i.e., in the first measurement cycle, the voltage at the output of the second analog storage unit 12 is zero, then a voltage equal to the input voltage is applied to the input of the first analog memory of the block. filter 18.

The team arriving on the line 15 ko-. Mand, in sync block 14, is a binary word. According to the received command, the measurement of input iib x signals arriving on the bus 2 information inputs takes place. Each command indicates the number of the measured droplet, the required gain factor, the size of the realization, the number of recirculation cycles and the operating mode, i.e., either one background or a useful signal is measured.

When the device operates in the background measurement mode, the control inputs of the analog switch 3, amplifier 4 with programmable gain and register 7 from block 1 receive control signals for etching, at which analog switch 3 connects the required channel to the input of amplifier 4 with programmable gain gain dis tom 1, the gain of which is set according to the command, and the output code of register 7 remains such that the voltage at the output of the transducer 5 code - 1 apr) is zero.

The input voltage of amplifier 4 with a programmable coefficient is

UVH b; | - | ODR,

1de / Flu - voltage of the background of the nth channel; f / .ip is the drift of amplifiers 4 and 6, reduced to the input. In turn,

/ 7Ф „Lc 111 ,, -} - (7пом„, 1de (- - initial shear stress

n-th channel;

LnoM ,, is the voltage of the interference occurring on the connecting wires in the nth channel.

The shear stress, in turn, consists of the voltage of the analog switch and the initial bias of the signal source (for strain gauges, for example, it is an imbalance of the strain gauge). The amplified voltage is fed to the input of the recursive filter 18. In the first measurement cycle, when the first analog storage unit 11 takes the first sample of the background signal, the second analog storage unit 12 stores a zero voltage that does not affect the first sample, hereinafter The expression of the recursive filter 18 is determined by the expression. y (pT) x (pT) —yy (), where y (pT) is the voltage of the lth sample at the output of the filter; y (pT-T) is the voltage of (n-1) -th sample at the filter output; x (pT) is the input voltage of the filter for the lth sample; b is the division ratio of the inverting analog divider 9. The voltage from the output of the filter is fed to the information input of the voltage-to-voltage converter 13, converted into a digital code, and written to the first page of the on-line storage unit 10 at the first address. Similarly, a second sample digital code, etc., is recorded at the second address of the first page of block 10, etc. The background in the selected channel is measured several times, while the first page of the operational storage unit 10 records the implementation of a random process, the number of samples in which is determined by the command. When the number of samples is compared with the required number, the control inputs of amplifier 4 with programmable gain and number registers V receive control signals such that the output voltage of amplifier 4 with programmable gain is zero, and write register 7 goes to number 7. information from the output of the operational storage unit 10. The voltage from the output of the converter 5 is a code-voltage that converts a digital code read from the operational storage unit 10 and recorded then in page 7, into the voltage, is fed to the first input of the summing amplifier 6. Thus, the feedback circuit closes: the analog signal from the output of the summing amplifier 6 passes through a recursive filter 18, is converted into a digital code, then returns to the voltage and input to summing amplifier 6, i.e., information is recirculated. The information stored at the first address in the operational storage unit 10 is rewritten into a number register 7, is converted into analog voltage by a code-voltage converter 5, amplified by a summing amplifier 6 and fed to the input of a recursive filter 18, the output voltage of which is converted into the digital code of the voltage-to-voltage converter 13 is again recorded at the first address on the first page of the on-line storage unit 10. In this mode, the on-line storage unit 10 operates in read mode when first analog memory unit 11 operates in the sampling mode, the second analog memory unit 12 - in the storage mode, the voltage converter 13 code - in the increment mode, ie the output register cleaning and preparation for the next conversion cycle... At this time, the source of information is the operational storage unit 10. When the first analog storage unit AND goes into storage mode, it already becomes the source of information. In this case, the second analog storage unit 12 switches to the sampling mode, the voltage-code converter 13 to the conversion mode, and the online digital storage unit 10 to the recording mode. Thus, after the end of the first conversion cycle, a new number is recorded at the first address of the first page of the operational digital storage unit 10, which differs from the previous one in that the analog signal, the digital equivalent of which it is, passes through the recursive filter 18 twice. For information recorded at other addresses of the operational digital storage unit 10, the recirculation process is similar. After the end of the first recirculation cycle, the first page of the operative storage unit 10 is recorded with the implementation of a random process, all samples of which were twice passed through a recursive filter 18. The number of recirculation cycles is indicated in the control word, and the recirculation continues until the number of recirculation cycles tion does not coincide with the specified. The number of recycle cycles depends on the cut-off frequency of the recursive filter 18, which for frequencies in the range (where T is the duration of the sample conversion cycle of the analog signal to the digital equivalent), is a low-pass filter. The amplitude-frequency characteristic of the first-order recursive filter 18 is determined by the expression K (.. Vl-ffr-26co5a) 7 where b is the division factor of the divider 9; T is the duration of the conversion cycle. For N recirculation cycles, the transfer coefficient is KN (") - (. J + b -2bcosu T) the condition should be met that the total transfer coefficient in the recirculation ring should be i at a) 0 for any value V. - From this expression we can determine. What is the cutoff frequency of the filter for the number of recirculation cycles (./- V + B 2H Cfl l + bMl-bf-2 arccosr 2b or the required number of recirculation cycles to obtain the required center frequency for 1 + g -26Co5 (2 /, : p7) M (1-b) / J After the recirculation process is completed, the operational storage unit 10 is switched to the second page for one conversion cycle and the background signal information of the measured channel is written to the second page at the address equal to the number of the measured channel. in the background voltage of the measured channel recorded on the first countries After the filtering, the high-frequency components are missing or significantly weakened, its samples are slightly different from each other, and any of them can be used to compensate for the low-frequency components of the additive error in measuring the useful signal. Thus, after measuring the background in all channels The second page of the operational storage unit 10 records information about the background voltages in all channels, and the number dripped is equal to the address at which the info about its background information is recorded. prine. Upon completion of the "Measurement of the background for each drip" command after the end of the recirculation process and re-recording of information on the second memory page, before the arrival of the code on which the background measurement in the next channel is generated, a control signal is applied to the register 7, in which The signal at the output of the converter 5 is a code-voltage and, therefore, the finite filter signal is zero. The signal is measured as follows. When the "Measurement of the signal before the measurement process" command is received, the analog switch 3 selects the required channel number, and the on-line storage unit 10 switches to the second page to the address equal to the number of the measured channel to the read mode. The background voltage information in the measured channel is rewritten into the 7th number register and stored in it for the entire measurement time. The control input PA of the amplifier 4 with a programmable gain factor is supplied by the control sigal, according to which the required gain factor is selected. In the same way as when measuring the background, the first page of the operational storage unit 10 records the implementation of a random process, which is a collection of samples of the total sigpal coming from the output of summing amplifier 6 to the input of the recursive filter 18. When the code is converted into voltage by converter 5, the code - voltage is inverted, therefore the sigal at the output of summing amplifier 6 is proportional to the voltage difference at its outputs, i.e. (UC-U). where K is the gain of the summing amplifier 6. When the number of samples in the implementation is compared with a given one, the PA control inputs of amplifier 4 with programmable gain and register 7 are supplied with control signals at which the transfer ratio of amplifier 4 is zero and register 7 goes from snoring mode in recording mode. In this case, the recirculation ring closes, which occurs in the same way as when measuring the background. With the fourth cycle number of recirculation cycles, the inversion of information occurring in the recirculation ring does not affect the measurement result. The gain, the size of the realization, and the number of recirculation cycles must be chosen for each channel exactly as heavy as when measuring the background in this channel, and the additive component of the measurement error accumulated during recirculation is fully compensated. After the end of the recirculation process, on the first page of the operational storage unit 10 there is a recorded signal measured in the selected channel during the recording time of the realization, with the high-frequency components of the additive signal and sound mixture. The device input is filtered out by the recursive filter 18, and the low-frequency additive noise and the initial shift are eliminated by algebraically summing the useful signal with the background in the summing amplifier 6. The measurement of the signal in each channel is completed by outputting information from the operational storage unit 10 through register 7 to unit 14 synchronization and to the data bus 16 by the signal entering block 14 of control block 1. Moreover, it can be deduced as the entire implementation of signal 1a, as well as one, on its last sample.

Measurement of the signal in other channels is similar.

The size of the implementation is chosen based on the duration of the input signal and the required measurement rate.

The use of an analog-digital programmable recursive filter 18 with a controlled number of recirculation cycles allows you to quickly rearrange the amplitude-frequency characteristic of the measuring path depending on the amplitude-frequency characteristic of the input source, while increasing the signal-to-noise ratio at the information input of the converter 13, the voltage code, and thereby improved measurement accuracy.

The operation of blocks 1 and 14, respectively, of control and synchronization occurs in the following way (Fig. 1-3).

When a command word in a sequential code is received on bus 15, and on clock synchronization bus 17, the command passed through the first receiver 31 serving to match the input of control block I with command bus 15 is written to command register 19. Here, the pulse burst generation unit 33 produces a burst of pulses, the number of which is equal to the number of binary bits of the control word. These pulses are the shift pulses of the register of 19 commands. The pulse burst formation unit 33 is started by the starting parcel arriving before the first discharge of the control word. After the arrival of the stop sending, the shift pulses cease to arrive at the control input of the register 19 of the command, and the signal "The received command is generated, which is a short positive pulse.

Before the signal is received, the received command both triggers 24 and 25 and both counters 21 and 23 are in the zero state. In this case, the register 7 is reset by a logical "1" signal coming from the output of the second trigger 25, and the decoder 20 is blocked by a logical signal "1 coming from the output of the first trigger 24, the gain of the amplifier 4 with a programmable gain is zero.

In the Background measurement mode, the control unit 1 operates as follows.

From the fifth output of the register 19 of the command to the information input of the second trigger 25 and the second input of the first circuit AND element 2I-OR 26 enters a logical "O, while the first input of the second circuit AND element 2I-OR 26 enters a logical" 1, while the output has a logical "O until the overflow signal of the counter 21 appears, while for this overflow pulse the page of the on-line storage unit 10 switches from the first to the second, and the multiplexer sends signals to the address bus of the on-line storage unit 10 from the counter outputs 23. The overflow signals of the meters 21 and 23 are short negative pulses.

When the signal received, the command received the first trigger 24 changes its state to the opposite, the decoder 20 is unlocked, the second trigger 25 does not change its state and the register 7 remains zero. When the counter 23 overflows, the first trigger 24 again switches to the zero state, the decoder 20 is blocked, and the write enable signal is sent to the control input of the register 7. In this case, the second trigger 25 also changes its state to the opposite and zeroing is removed from register 7. In such a state, the triggers 24 and 25 are before the occurrence of the overrun signal, the counter 21, which sets the second trigger 25 to the initial zero state and, arriving at the third input of the pulse former, enables the output of information to the data bus 16 via block 14.

In the Signal measurement mode, the control unit 1 operates as follows.

From the fifth output of the register 19 of the command to the information input of the second trigger 25 and the second input of the first circuit AND element 2I-OR 26 enters the logic "1.

At the same time, the received command command goes to the output of element 2I-OR 26, switches multiplexer 28 and the page of the operational storage unit 10 and, in addition, allows writing to register 7. After the end of the signal, the command received register 7 goes into storage mode. Both triggers 24 and 25, when the received command receives a command, change their state to the opposite, unlocking the decoder 20 and unsetting the register 7. After the counter 23 is full, the first trigger 24 changes its state to the opposite, blocking a decoder 20 and writing into the register of the 7th number is permitted, and the second trigger 25 of its state does not change. The overflow signal of the counter 21 sets the second trigger 25 to the initial zero state and allows the output of information to the data bus 16.

Pulse generator 27 forms, from a sequence of clock pulses, control pulses of the first and second analog storage units 11 and 12, digital operation unit 10, voltage-code converter 13, number register 7 and implementation size counter 23.

Claims (2)

1. A multi-channel programmable analog-to-digital converter, containing a control unit, the first, second, third and fourth outputs of which are connected respectively to the first inputs of the analog switch, the operational storage unit, the voltage-code converter and the synchronization unit, the second and third inputs of which are respectively, the command bus and the synchronization bus, and the first and second outputs are connected to the first input of the control unit and the output bus, the first analogue storage unit, the output of which The voltage-code converter is connected to the second inputs of the random access memory block, characterized in that, in order to expand the functionality and increase the measurement accuracy of the slow: changing signals, a programmable gain amplifier is inserted into it, an analog adder, summing amplifier, the second analog storage unit, the inverting divider, the code-voltage converter and the register, the fifth, sixth, seventh and eighth outputs of the control unit are connected respectively with the first inputs of a programmable gain amplifier, register, first and second analog storage units, the second inputs of the analog switch being input buses, and the output through a programmable gain amplifier connected to the first input of a summing amplifier, the second input of which is through a converter the code-voltage is connected to the outputs of the register, the second inputs of which are connected to the outputs of the operational storage unit, the second input of the second analog storage unit ka connected to the output of the first analog storage unit, the output of which through an inverting divider is connected to the first input of an analog adder, the second input of which is connected to the output of the summing amplifier, the output to the second input of the first analog storage unit connected to the outputs of the register. 2. The converter according to claim I, characterized in that the control unit is executed on the command register, decipher, two counters, two inverters, two triggers, element 2I-OR, pulse shaper, multiplexer, element OR, the output of which is the sixth output of the block control, the third, fourth, sixth, seventh and eighth outputs of which are the first to fifth outputs of the pulse former, the sixth output of which is connected to the first input of the first counter, the second inputs of which are connected to the first group of outputs by the register Handles, the second group of outputs of which are connected to the first inputs of the multiplexer and are the first outputs of the control unit, the second outputs of which are the outputs of the multiplexer, the second input of which is connected to the output of element II-OR and is the second output of the control unit, and the third inputs are connected to the first outputs of the first counter, the second output of which is connected to the first input of the second counter, / -input the first trigger and the S-input of the second trigger, the D-input of which is combined with the first input of the element 2И-OR and the input of the first and and connected to the third output of the command register, the output of the first inverter is connected to the second input of element 2И-OR, the third input of which is combined with the C inputs of the flip-flops, the first input of the OR element, the first input of the pulse shaper and the sixth output which is the output of the second trigger, the / input of which is combined with the first input of the second inverter, the second input of the pulse generator and connected to the output of the second counter, the inputs of which are connected to the fourth group of outputs command, the fifth group of outputs of which are connected to the first inputs of the decoder, the second input of which is combined with the second input of the OR element and connected to the output of the first trigger, the S and O inputs of which are connected to the positive potential bus, the first and second inputs of the command register and the third input of the pulse generator are the first inputs of the control unit, the pilot outputs of which are the outputs of the decoder, and the fourth input of the element 2I-OR is connected to the output of the second inverter. R Impulses sd & yoke Team Coesrcicent. enhance syncroimpersa 1 / Y2 channel Recording resolution in a number register Resetting a number register Page Sampling I tap Recording / reading / Gamen1 conversion / conversion Writing into a register Output insr1 and FIG. 2 Inermation Mine data