RU2811324C1 - Heterogeneous computing module and embedded heterogeneous computing device based on it - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention is intended to work in devices of the Internet of Things (IoT), Edge Intelligence (EDGE AI) and other compact computing systems for processing information using classical and artificial intelligence algorithms. The effect is achieved through the use of a trusted circuit block, consisting of a separate processor with built-in memory that controls operation of other elements. The design of the final product is made in the form of a “sandwich” from a mounted printed circuit board, which is mechanically connected to a cooling radiator, which directly touches the most heat-loaded elements and which is an element of the body of the final product where this device is integrated. At the same time, the heatsink can limit physical access to the trusted circuit and device memory.

EFFECT: increased level of cyber security of a heterogeneous computing module, as well as simplified final product based on an embedded device using the claimed module while simultaneously reducing the dimensions of the device and increasing its reliability.

5 cl, 3 dwg

Description

The declared group of inventions relates to embedded computing systems and is intended to work in devices of the Internet of Things (IoT), Edge Intelligence (EDGE AI) and other compact computing systems for processing information using classical and artificial intelligence algorithms.

In the modern world, compact computing devices of the IoT and EDGE AI class are in demand, which must solve several diverse tasks in parallel in real time, for example, pattern recognition using artificial intelligence algorithms, performing general calculations using traditional algorithms, and transferring information to external systems. To solve this problem, in recent years, heterogeneous computing modules have begun to be created, incorporating various highly specialized microprocessor circuits, controllers or cores, each of which deals with its own class of tasks.

Until recently, embedded computing modules were built on the basis of “lightweight” classic processor cores X86, RISC, ARM. Moreover, the cores were, as a rule, of the same type, thus, a relatively universal homogeneous computing system was obtained, which showed good performance for classical algorithms, but insufficient, for example, for the operation of artificial intelligence algorithms in real time.

The design of such devices was dominated by the classic server layout with forced air cooling. This solution did not allow the creation of compact and, at the same time, high-performance devices in terms of the speed of calculation of the solution.

A high-performance computing platform based on processors with heterogeneous architecture is known [invention patent RU 2635896, publ. 11/16/2017], made on the basis of processors with heterogeneous architecture, containing a 4U high mounting block, designed for installation in a telecommunications rack and made in the form of a housing divided into two sections. In one of the sections the power supply system is mounted, and in the second there is a backplane with slots for placing switching modules and computing modules based on heterogeneous processors placed through the indicated opening, united through a high-speed bus of the CompactPCI Serial standard to form a multiprocessor configuration.

The disadvantage of this device is its significant dimensions: height 4U 18 cm, width 49 cm, which precludes their use in compact IoT and Edge AI devices. The use of a common Compact PCI serial bus, to which all microprocessors are connected, makes the device cyber vulnerable due to access to this bus through existing switching modules. In addition, the device has forced cooling using fans, this makes it difficult to cool the device as a whole, since heated air is thrown into the inside of the device, and also increases the dimensions of the device, so this device cannot fundamentally be used in compact devices for IoT and Edge AI.

There is a known method for creating a reconfigurable structure of connections in an integrated circuit [invention patent US 10,872,186, publ. 12/22/2020], including access to a configuration template aimed at a reconfigurable connection structure, editing configuration template parameters, functionally combining the configuration template with multiple modules from the IP library to create a register transfer level (RTL) circuit model, generating at least one automated test bench function and creation of at least one logic synthesis scenario. Editing configuration template parameters includes confirming a first number of output ports of the reconfigurable flow switch and confirming a second number of input ports of the reconfigurable flow switch. Each output port and each input port have a corresponding architectural composition. The output port architecture is defined by a plurality of N data paths, including A data outputs and B control outputs. The input port architecture is defined by a plurality of M data paths, including A data inputs and B control inputs.

The disadvantage of this device is the low level of cyber security due to unprotected access to the device through input ports and the ability to change the template or its parameters.

The technical result of the claimed group of inventions is to increase the level of cyber security of a heterogeneous computing module, as well as to simplify the final product based on an embedded device based on the claimed module while simultaneously reducing the dimensions of the device and increasing its reliability.

The claimed technical result in terms of cybersecurity of a heterogeneous computing module is achieved due to the fact that it consists of a processing unit for artificial intelligence algorithms, an ARM controller, a trusted circuit unit on a dedicated architecture processor with built-in memory, a power controller, an interface unit containing data transfer interfaces, a permanent storage device and random access memory, according to the present invention, the artificial intelligence algorithm processing unit, the interface unit, the ARM controller, the read-only memory and the random access memory are connected to a common data bus, and the trusted loop unit is connected to the ARM controller and to the power controller, The power controller is connected via power buses to the artificial intelligence algorithm processing unit, interface unit, ARM controller, read-only memory and random access memory, and the artificial intelligence algorithm processing unit is additionally directly connected to the interface unit.

Possible options for the development of the main technical solution are that the processing unit for artificial intelligence algorithms is implemented on FPGA technology or DSP technology.

The claimed technical result in terms of increasing the reliability and reducing the size of an embedded heterogeneous computing device based on a heterogeneous computing module is achieved due to the fact that it consists of a printed circuit board and a cooling radiator connected to each other, while all the elements of the heterogeneous computing module are placed on the printed circuit board Using surface mounting and subsequent soldering to its current-carrying lines, the cooling radiator is attached to the printed circuit board ensuring thermal contact with the artificial intelligence algorithm processing unit, power controller and ARM controller of the computing module.

A possible development option for the main technical solution is that the radiator blocks access to the trusted circuit block of the computing module.

Thus, due to the combination of essential features, it was possible to increase the level of cyber security of the module and the entire device, thanks to the use of a trusted circuit unit, consisting of a separate processor with built-in memory that controls the operation of other elements. At the same time, the design of the final product is simplified, the dimensions are reduced and the reliability of the device based on the computing module is increased due to its special design in the form of a “sandwich” of a mounted printed circuit board, which is mechanically connected to a cooling radiator, which directly touches the most heat-loaded elements and which is an element the housing of the final product where this device is built. At the same time, the heatsink can limit physical access to the trusted circuit and device memory, which also increases the level of cyber security of the device.

The essence of the proposed technical solution is illustrated by the figures and the following description.

In FIG. 1 shows a block diagram of the proposed computing module.

In FIG. Figure 2 shows the design of the device.

In FIG. Figure 3 shows an illustration of the integration of the proposed device into the final product - a Smart Camera.

The heterogeneous embedded computing module (Fig. 1) consists of block 1 for processing artificial intelligence algorithms (hereinafter referred to as Block 1 AI), controller 2 ARM, block 3 of the trusted circuit (hereinafter referred to as Block 3 DC) on a dedicated architecture processor with built-in memory, controller 4 power supply, interface block 5 containing data transfer interfaces, read-only memory 6 (hereinafter referred to as ROM 6) and random access memory 7 (hereinafter referred to as RAM 7).

AI block 1, interface block 5, ARM controller 2, ROM 6 and RAM 7 are connected to a common data bus 8.

In this case, the DC block 3 is connected to the ARM controller 2 and to the power supply controller 4.

Power controller 4 is connected via power buses to AI block 1, interface block 5, ARM controller 2, ROM 6 and RAM 7.

Block 1 AI is additionally directly connected to block 5 interfaces.

Block 1 AI is designed to speed up the execution of artificial intelligence algorithms, including neural network algorithms. Block 1 AI must have a computing performance of at least 0.5 TOPs (0.5x10^12 operations per second) and is implemented either on specialized processor DSP (another name for NPU or TPU processors) cores, for example Elcore from the company SPC Elvis or Amper, Volta from Nvidia, initially optimized for working with artificial intelligence algorithms, or on integrated FPGA circuits, for example, from Xilinx, Lattice, with a structure programmed for artificial intelligence algorithms. The use of FPGA circuits is possible if they contain at least 100,000 programmable gate elements, which allows obtaining a performance of at least 0.5 TOPs. This performance of AI Block 1 allows, for example, to process a video stream at a speed of 10-15 frames per second. A special feature of connecting AI Block 1 is its direct connection to interface Block 5, bypassing the common data bus 8 and ARM Controller 2, which speeds up the output of information from the device when processing information in it in real time. For example, when using the traditional method of outputting the result from Block 1 AI to Block 5 of the interface via a common data bus 8 under the control of Controller 2 ARM, the response time to the event takes 80-120 ms, when directly outputting from Block 1 AI to Block 5 of the interface this time is 15-25 ms.

The 2 ARM controller contains at least one ARM Cortex-A core of at least 32 bits. Controller 2 is designed to execute an application program recorded in ROM 6. This program is determined by the functionality of the final product and determines what data and in which block of the device will be processed.

Block 3 DC is a dedicated microprocessor based on RISC architecture. It has built-in memory containing immutable code for booting and initializing the device as a whole. Since the trusted circuit processor is not connected to the common bus 8 and does not have external memory that can be changed by attackers, high resistance to malicious code and resistance to external changes in the control program are achieved. In the inventive device, a trusted circuit is used to initialize the system and control power through the Power Controller 4.

The power controller 4 generates the necessary supply voltages for the elements of the computing device connected to it via the power bus. It is controlled from Block 3 of the DC and, thereby, minimizing the potential impact of malicious code that potentially got into Controller 2 ARM on the operation of other elements of the device along the power circuits.

Interface block 5 is designed for exchanging information with external systems. The composition of block 5 is determined by the functionality of the final product assembled on the basis of the device. This block 5 contains any combination of the following interfaces: HDMI and/or MIPI and/or Ethernet and/or Wi-Fi and/or DIO and/or AIO and/or Audio. A distinctive feature of the inclusion of Interface Block 5 is its direct connection to AI Block 1, which makes it possible to significantly reduce the transmission time of the control signal from AI Block 1 to Interface Block 5 and its output to the outside, compared to the traditional way, via the common data bus 8 through Controller 2 ARM.

ROM 6 is designed to store application programs that ARM Controller 2 executes. The volume of ROM 6 for the devices to function must be from 4 to 64 GB.

RAM 7 is designed to store intermediate data and calculation results. The amount of RAM 7 for the devices to function must be from 1 to 16 GB.

The proposed module works as follows.

When supply voltage is applied, if it meets the necessary criteria, the Power Controller 4 initially supplies power only to DC Unit 3. He, in turn, begins executing the program located in his own memory, not connected to the common data bus 8. This ensures physical isolation of the element - Block 3 DC from the common data bus 8, which makes it fundamentally impossible to run malicious code on it from Interface Block 5, ROM 6 and RAM 7 when replacing the latter, thereby increasing the cyber security of the device.

After startup, DC Block 3, controlling Power Controller 4, supplies power via dedicated bus lines only to those devices that are needed to solve the problem at a given time. Next, DC Block 3 launches ARM Controller 2, which begins executing the application program recorded in ROM 6. RAM 7 is used to store intermediate results. The application program distributes data streams across computing units, optimizing device performance. For example, neural network algorithms, as a rule, are performed in Block 1 of the AI, general-purpose algorithms on ARM controller 2, and safety-critical calculations in Block 3 of the DC. Interface block 5 is designed to exchange information between the device and the “outside world”. The peculiarity of connecting this block 5 is that in addition to connecting to the common data bus 8, the interface Block 5 can receive information directly from the AI Block 1, bypassing the common bus 8 and the ARM Controller 2. Thanks to this, the response time to an event is significantly reduced, on average from approximately 100 ms to 20 ms.

An embedded heterogeneous computing device (Fig. 2) based on a heterogeneous computing module consists of a mounted printed circuit board 9 and a cooling radiator 10 connected to each other.

In this case, all the elements of the heterogeneous computing module are placed on the printed circuit board 9 using surface mounting and subsequent soldering to its current-carrying lines.

The cooling radiator 10 is attached to the printed circuit board 9 to provide thermal contact with the AI Unit 1, the Power Controller 4 and the Compute Module ARM Controller 2, since these elements are the most heat-generating. They provide up to 70-80% of the total heat release of the module, so sufficient heat removal from these elements is a necessary condition for the reliability of the module as a whole.

To increase the compactness of the device, it is advisable to implement module elements 1, 3, 4, 5 on a single silicon crystal and in one integrated circuit package. Examples of such integrated circuits are the SKIF integrated circuit from SPC Elvis, in which Block 1 AI is implemented on ELcore-50 DSP cores with a performance of 1.2 TOPs (1.2*10^12 operations per second), or the Kria integrated circuit from the company Xilinx, in which AI Block 1 is implemented on an FPGA circuit with a number of gates of more than 200,000 and a performance of 1.35 TOPs (1.35*10^12 operations per second).

To ensure additional compactness of the device design, it is advisable to use a printed circuit board measuring 122x122 mm (Nano-ITX format), no more. It is considered justified to use boards of smaller formats Pico-ITX, Mobile-ITX, SBC 3.5” or SBC 2.5” if it is necessary to obtain a module volume of 0.2-0.3 liters.

The main idea of the device design is to constructively combine two elements into a single whole: 1) a mounted printed circuit board 9 containing module elements pos. 1-7 (Fig. 1), installed on it by surface mounting followed by soldering to its current-carrying tracks, including the common data bus 8 and the power bus, and 2) a passive cooling radiator 10. With this combination, the radiator 10 performs two roles: 1) a passive cooler for the most heat-producing elements: AI Block 1, Power Controller 4, ARM Controller 2, and 2) a structural element that provides the function of a cover or wall of the final product and physical protection for DC Block 3 .

To achieve these goals, the printed circuit board 9 is designed in such a way that its “hottest” elements 1, 2, 4 are mounted on the first side, and the remaining elements 3, 5, 6, 7 can be located on both sides in an arbitrary manner. In this case, the board 9 is pressed against the surface of the cooling radiator 10 and ensures thermal contact of board elements 1, 2, 4 with it and protection of element 3. The board 9 is pressed to the radiator 10 by means of fastening elements such as screws, rivets, threaded bushings, etc.

In this solution, the other side of the radiator 10 is the outer wall of the device and borders the external environment, providing sufficient heat removal from these elements without the use of a fan for forced airflow. In addition, the use of the radiator as the outer wall of the final product and the arbitrary relief of its (radiator) surface, from smooth to significantly ribbed, made it possible to make its area variable from 150 to 300 cm2, thereby providing sufficient passive cooling of the most thermally loaded elements of the module 1 circuit, 2, 4. Any metal that can withstand the required structural loads during operation of the final product can be used as the material of the radiator 10.

It is possible to develop the main technical solution in which the dimensions of the radiator 10 exceed the dimensions of the board 9. In this case, parts of its contour protruding beyond the perimeter of the board 9 can be used to fix the device along this contour to the body of the final product.

If it is necessary to ensure dust and moisture protection of the final product, sealing occurs along this protruding contour of the radiator 10. With this design of the device, its radiator 10, in addition to cooling and physical protection of element 3, acts as a load-bearing wall or part thereof for the final product.

As an example, in FIG. Figure 2 shows that the excess of the dimensions of the radiator 10 in width relative to board 9 was 10%, in length - 20%, which provided an effective cooling area of 200 cm2, while the temperature of elements 1, 2, 4 did not rise above 76 degrees. C, which is an acceptable value. Further modeling showed the possibility of exceeding the dimensions of the radiator 10 relative to the board 9 from 10 to 40%. The effective cooling area of the radiator 10 in this case will be up to 300 cm2, which is enough to dissipate up to 10 W of thermal power.

In FIG. Figure 3 shows, as an example, a view of the final product of the Edge AI class - a smart camera - which includes the claimed embedded device. The device is installed as an assembly and fixed to the body 11 of the final product along the protruding part of the radiator 10 using a screw, glue, rivet or latches method, providing the required degree of sealing of the final product. In this case, the radiator 10 acts as part of the upper cover of the device, thereby providing a significant simplification of the design of the latter and good heat transfer, since it (the radiator) is in contact with the external environment, which has a lower temperature, unlike the traditional layout, when the radiator of the electronic module is located inside the device .

Elements 1, 2, 3, 4, 5 are installed on the first side of the board 9, to which the radiator 10 is attached.

This device is made of a mounted printed circuit board 9 in the Pico-ITX form factor measuring 100x75 mm and a cooling radiator 10 pressed with screws to the first side of the board 9, and the most heat-generating elements 1, 2, 4 located on this side of the board 9 have thermal contact with radiator 10, actually touch it. To eliminate the possible gap between elements 1, 2, 4 and the radiator 10, due to the different heights of elements 1, 2, 4 relative to the surface of the board 9, heat-conducting pads, gels, and pastes are used. Also, to level out the difference in height of elements 1, 2, 4, the radiator 10 can be made with variable thickness, ensuring a gap-free connection to these elements. In this case, a variant of the device is possible when element 3 is located on the same side of the board 9 as elements 1, 2, 4, and the radiator 10 covers element 3, limiting physical access to it, thereby further increasing the cybersecurity of the device.

Other examples of end products of the IoT and EDGE AI classes, where the claimed device can be used, can be: driver assistance devices (ADAS), ATMs, access control systems, and information terminals where biometric recognition of an individual is required and similar products and systems where a combination of general information processing algorithms in conjunction with artificial intelligence algorithms, small size, simplicity, cyber security and reliability is required.

Thus, the proposed device circuit allows us to achieve the following results: in terms of high computing performance due to the combination of Controller 2 Arm on one or more ARM processor cores, Block 1 AI based on DSP processor cores or FPGA circuits, direct connection of Block 5 interface with Block 1 AI ; high cyber security due to the use of Block 3 DC on a specialized processor with built-in memory and which is not physically connected to the common bus and device memory, into which malicious code can be inserted; in terms of the compact dimensions of the device and simplifying the design of the final products and increasing their reliability due to the special design of the device in the form of a “sandwich” from a mounted printed circuit board connected mechanically to a cooling radiator, which directly touches the most heat-loaded elements and which is the wall of the final products and the physical protection Block 3 DC.

Claims (5)

1. A heterogeneous computing module, consisting of a processing unit for artificial intelligence algorithms, an ARM controller, a trusted circuit unit on a dedicated architecture processor with built-in memory, a power controller, an interface unit containing data transfer interfaces, a permanent storage device and a random access memory device, characterized by: that the artificial intelligence algorithm processing unit, interface unit, ARM controller, read-only memory and random access memory are connected to a common data bus, while the trusted circuit unit is a dedicated microprocessor having built-in memory containing immutable boot and initialization code for the device as a whole, and is connected to the ARM controller and to the power controller, the power controller is connected via power buses to the artificial intelligence algorithm processing unit, interface unit, ARM controller, read-only memory and random access memory, and the artificial intelligence algorithm processing unit is additionally directly connected to the interface unit. 2. The heterogeneous computing module according to claim 1, characterized in that the processing unit for artificial intelligence algorithms is implemented on FPGA technology. 3. The heterogeneous computing module according to claim 1, characterized in that the processing unit for artificial intelligence algorithms is implemented on DSP technology. 4. An embedded heterogeneous computing device based on a heterogeneous computing module according to claim 1 consists of a mounted printed circuit board and a cooling radiator connected to each other, while all elements of the heterogeneous computing module are placed on the printed circuit board using surface mounting and subsequent soldering to its current-carrying lines , the cooling radiator is attached to the printed circuit board to ensure thermal contact with the artificial intelligence algorithm processing unit, the power controller and the ARM controller of the computing module. 5. An embedded heterogeneous computing device according to claim 4, characterized in that the heatsink blocks access to the trusted circuit block of the computing module.