RU2451327C1 - Apparatus for forming spoofing resistant systems of discrete-frequency signals with information time-division multiplexing - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device includes: a counter, a remainder generator, a register, a multiplier generator, a unit for generating systems of composite discrete-frequency signals, the first inputs of which are connected to the remainder code outputs of the multiplier generator, and the input for writing the number of elements of the multiplier generator is combined with the second input of the unit for generating systems of composite discrete-frequency signals, and the computation start input of the multiplier generator is combined with the third input of the unit for generating systems of composite discrete-frequency signals, and the first output of the unit for generating systems of composite discrete-frequency signals is the clock control input of the multiplier generator, the counter and the register, and the second output of the unit for generating systems of composite discrete-frequency signals is the data output.

EFFECT: wider range of solved tasks for forming spoofing resistant systems of discrete-frequency signals and high spoofing resistant of communication systems.

2 cl, 11 dwg

Description

The device relates to the field of computer engineering and applied mathematics and can be used in the technique of generating complex waveforms. In modern communication systems for special purposes with temporary compaction of information using complex signals, there is a need to use imitation-resistant systems of complex signals that carry a large degree of uncertainty in their structure regarding the type, shape, duration of signals and their ensemble characteristics.

Currently, linear recurrence sequences (LRS) and three-level sequences (TP), as well as a number of derivatives from them: segment sequences, sequences of non-maximum length, are widely used as complex signals [1, 2]. However, the use of these types of complex signals does not provide the necessary resistance and stealth signals for special systems, since for these sequences there are highly effective methods for revealing their structure and simulation [3]. In addition, these sequences have not very high ensemble characteristics, which does not allow for their use to provide high noise immunity from mutual interference [4].

The widespread occurrence of LRS and TP is due to the fact that a convenient method of forming by means of shift registers with linear feedbacks (with VOCs) was found for them, while the formation of a separate LRS requires the development of a separate autonomous register machine with linear feedbacks. Therefore, to create a large ensemble of LRS, it is necessary to create a large fleet of automatic machines, which complicates the equipment for forming a complex signal system. In addition, LRS and TP exist for a limited number of durations l = 2 ^n-1 , n = 1, 2, 3 ..., which significantly reduces the functionality of their use in practice. For example, when adapting to interference, it is required to vary the duration of the LRS over a wide range, which is not provided when using the LRS and TP. Therefore, at present, in special systems with complex signals with temporary compression of discrete information from an N-channel information source, the task is to create devices that provide the formation of wide classes and large volumes of ensembles of imitation-resistant systems of complex signals, which also have high ensemble characteristics. In this regard, one of the promising imitation-resistant systems of complex signals, as well-known studies [4, 5] show, is primarily a system of discrete frequency signals, the potential of which is to increase the imitability of complex signal systems with high noise immunity. However, to date, as the patent search shows, there are no theoretical and practical samples of technical solutions that provide the formation of imitation-resistant systems of discrete frequency signals (DFS) with temporary compression of discrete information from an N-channel information source. DFS are signals consisting of N radio pulses with the same envelope Uc (t), which are offset from each other in frequency by an amount F ₀ equal to the effective width of the spectrum of the radio pulse, and are emitted in accordance with the code sequence of the signal {a _n }.

DES have the following advantages:

, а не базе В, как в случае дискретных сигналов.1. They allow you to more easily implement a large base of the signal, since the number of channels is proportional

rather than base B, as in the case of discrete signals.

2. They allow one to obtain better noise immunity with respect to certain types of organized interference and significantly weaken the effect of interfering signals.

3. DFS have the property of minimal mutual correlation and, therefore, give a minimum level of noise of non-orthogonality during asynchronous operation, which is especially important.

Figure 1, a-d shows discrete frequency elements - time-shifted radio pulses with different carrier frequencies, i.e. there is a shift in frequency, as in frequency signals, and in time, as in discrete signals. Amplitudes and initial phases can be different. The figure 1, e shows the signal U (t), which is the sum of discrete frequency elements. Such signals are DFS.

The energy distribution of the DFS on the time-frequency plane is shown in Figure 2. Each element occupies its own part of the plane in the form of a hatched square.

DFS have (in addition to the above properties) and a great potential for creating imitation-resistant systems of complex signals, which is of particular importance for special communication systems.

As is known, imitability is understood to mean the ability of the system to resist the imposition of false information, while it is characterized by imitostability (I) of volume V of an ensemble of complex signals V _asp formed on the basis of identical elements, as well as the ability of the system to modify the vocabulary of complex signals in various parameters: I = log ₂ V _asp [6]. From this point of view, DFS are indispensable. So, for example, the volume (V) of the dictionary of DFS formed from n identical elements (frequencies) is the number of placements of n, i.e. V _n = n. If we now suppose possible changes in the composition of the elements, their quality and quantity, their duration, as well as the duration of the DPS itself, etc. etc., the volume of complex signals (DFS), possibly used in a communication system, increases significantly (it is not even possible to assume a specific V figure, since V can be extremely large and may depend on those specifically implemented in a particular system the possibilities for the formation of DFS). The type (or type), shape and composition of the DFS, as a rule, is characterized by the form of the so-called manipulating function, which is directly responsible for the properties of the DFS [5]. DFS can have the following types of manipulating functions:

1. Providing a change in the set of frequencies, ie their quality from the volume of removable frequencies V _f .

2. Providing a change in the number N _f frequencies from the volume V _Nf .

.3. Providing a change in the quantity and quality of elements (frequencies) from the volume

.

.4. Providing a change in the number and duration Δt _{i of} frequencies from the volume

.

5. Providing a change in the duration of the entire DFS with a fixed composition of its elements, ie frequencies from the volume V _Ti .

Consequently, the volume of the arsenal of interchangeable parameters of DFS at n = const is V _asp = V _f · V _Nf · V _Δti · n, from which we can conclude that the potential is very high and impervious, as И = f (V _asp ) = log ₂ V _Asp .

Thus, for the formation of imitation resistant systems of emergency situations with temporary information compaction it is necessary:

1. To provide the possibility of synthesis of an extensive ensemble (set) of highly stable frequencies.

2. To ensure the formation (according to a specific program) of the laws of frequency generation, having a certain regularity, easily restored on the receiving side of the system, and directly reflecting the shape and duration of the RF signals, ie types and types of functions indicated earlier.

3. To ensure pseudo-random correspondence of information packages of various channels with temporary compaction to the code forms (types) of the emergency situations.

However, to date, as shown by a patent search, devices (technical solutions) that together provide these functions (or close to them) are not available. In this regard, the task is to synthesize such devices using technical solutions that perform data (or similar functions) separately. So, for example, there are frequency synthesis devices - frequency synthesizers [7]. Regular cryptographic laws related to the use of the theory and properties of finite Galois fields GF (p ⁿ ) [8] can be attributed to the previously mentioned regular laws of frequency generation, as analysis of the theory and technique of applied mathematics shows. As is known, the properties and laws of finite fields, as well as their elements, have a number of necessary original features, in particular, the cyclic sequence of field elements, the dependence of the structure of field elements on the selected antiderivative, etc., which can be directly used to generate regular cryptographic generation laws, those. types and types of manipulating cryptographic functions. Thus, devices, blocks and nodes are needed to ensure the formation of all possible sequences of elements of all possible final Galois fields GF (p ⁿ ). There are a number of technical solutions that are close in their functions to similar nodes and devices.

One of the analogues, close in technical essence to the proposed device, is a device for calculating the remainder modulo of a number according to USSR author's certificate No. 407313 "Device for calculating the remainder modulo of a number", class G06F 11/08 of 11/21/1973, which allows calculate the remainder modulo of the number received at its input from the outside. This device is universal in the sense that it implements the ideology of working to find the remainder modulo of a number, suitable for any modules, and also discloses the general principle of constructing such devices for finding the remainder of a number by any other module. Thus, the device in the General case allows you to find the remainder of the incoming numbers on any module. However, this device, along with the fact that it opens up possibilities for realizing the idea of forming Galois field element elements GF (p ⁿ ), does not allow to output to its output at certain times a code of the remainder modulo the number received at that moment at its input, as well as it does not allow multiplying a given remainder by a fixed factor and further finding the remainder modulo this product.

The closest in technical essence to the claimed and adopted as a prototype is a device for forming elements of multiplicative groups of Galois fields according to USSR author's certificate No. 849895 "Device for forming elements of multiplicative groups of Galois fields", class ³ G06F 15/20 of 04/02/1979, containing a counter whose outputs are connected to the first group of inputs of the residual shaper, the outputs of which are connected to the inputs of the register, the outputs of which are connected to the second group of inputs of the residual shaper and with inputs s of elements of the forming multiplier, the control input of which is combined with the control inputs of the counter and the register and is the device’s clock input, and the output of the generator to the initial zero state of the forming multiplier is the corresponding input of the counter and the register, and the forming multiplier also has a recording input of the antiderivative element, the recording input units, the input of the start of calculation, the input of the record of the number of elements, the output of the end of the calculation, the output of the number record, which is the input of the residual shaper, and the outputs residual codes, and the forming multiplier contains a multiplication block, a shift register, an element number counter, an AND element group, three AND-NOT elements, an OR element, an AND element and five delay elements, recording entries of the forming multiplier elements are the first inputs of the AND elements of the group, the outputs of which are connected respectively to the inputs of the multiplication block and are the outputs of the codes of the remainder of the device, the outputs of the multiplication block are connected to the inputs of the shift register, the outputs of which are connected to the corresponding inputs of the first of the first AND-NOT element, the output of which is connected to the first input of the second AND-NOT element, the first input of the OR element and the input of the first delay element, the output of which is connected to the second inputs of the AND elements of the group, the input of the second delay element and the inputs of the counter of the number of elements, the output of which is connected to the input of the third delay element, the second input of the OR element and is the output of the end of the device’s calculations, the output of the OR element is connected to the first input of the multiplication unit, the second input of which is the input of the number of elements nt device, the output of the second delay element is connected to the first input of the third AND-NOT element, the output of which is combined with the input of the device’s computing channel and connected to the third input of the multiplication unit, the output of which is the output of the installation to its initial zero state and connected to the input of the fourth element delay, the output of which is connected to the output of the fifth delay element and is connected to the first input of the element "And", the output of which is connected to the input of the fifth delay element and the input of the shift register, the output of which is connected about the input of the residual shaper, the output of the third delay element is connected to the second input of the third AND-NOT element, the second input of the AND element is connected to the output of the second AND-NOT element, the second input of which is the clock input of the device, and the fourth input of the block Multiplication is the input of a unit device record.

This prototype device allows you to:

1. Generate any length L = p ⁿ -1 the sequence of codes of the elements of the multiplicative groups of the field GF (p ⁿ ), where n = var;

2. Generate automorphic sequences of codes of elements of the multiplicative group of the field GF (p ⁿ ) by changing the antiderivative element Q = var, with p ⁿ = const;

), где p_i=var.3. By structurally changing the residual shaper in order to form residuals modulo p _i, generate sequences of codes of elements of multiplicative groups of other fields GF (

), where p _i = var.

However, this device does not provide the formation of imitation resistant systems of emergency situations with temporary information compression.

The aim of the invention is to expand the class of problems to be solved for the formation of imitation resistant systems of emergency situations with temporary information compaction.

The goal is achieved by the fact that in the device for forming elements of multiplicative groups of Galois fields GF (p ⁿ ), containing a counter, a residual shaper, a register forming a multiplier with the corresponding above relations and the composition of the generating multiplier, an additional block for generating systems of complex discrete frequency signals is additionally introduced, the first inputs of which are connected to the outputs of the codes of the residues of the generating multiplier, and the input recording the number of elements of the forming multiplier is combined with the second input of the block formation of complex systems of discrete-frequency signals, and the input of the beginning of calculation of the generator of the multiplier is combined with the third input of the unit of formation of systems of complex discrete-frequency signals, and the first output of the unit of formation of systems of complex discrete-frequency signals is a clock control input of the generator of the multiplier, counter and register, and the second output of the block forming systems of complex digital-frequency signals is the information output of the device.

In the known technical solution there are signs inherent in the claimed solution. This is the presence of a counter, a shaper of residues, a register, a forming multiplier and corresponding common connections both between these blocks, as well as for the device as a whole, inputs and outputs, as well as the presence of the composition of the forming multiplier with the corresponding connections.

However, the properties of the claimed solution differ from the properties of the known solution in that, in order to expand the class of problems to be solved for the formation of simulated resistant systems of emergency situations with temporary information compression, the following are introduced: the unit for generating complex discrete frequency signal systems and its corresponding connections with the generating multiplier, counter and register and the output, which is the information output of the device, which corresponds to the signs of "significant differences" and ensures the achievement of a positive effect, moreover, the unit for generating systems of complex discrete-frequency signals contains: a decoder, the "K" inputs of which are the first inputs of the unit for forming systems of complex discrete-frequency signals, a "N" outputs are connected to the first "N" inputs of the distributor and "N" inputs of the circuit OR ”, the output of which is connected to the first input of the“ AND ”circuit, and the“ n ”outputs of the distributor are connected to the first inputs of the group of key circuits, the second inputs of which are connected to the“ n ”outputs of the frequency synthesizer, the third inputs are connected to the outputs of the discrete info source rations, and the outputs through the multi-input OR circuit are connected to the output of the device, and the output of the discrete information source is connected to the input of an analog-to-digital converter, the outputs of which are connected to the third inputs of the divider with a variable division ratio, the second input of which is the input for recording the number of elements, and the first input is the output of the clock generator, and the output of the divider with a variable division coefficient is the clock control input of the counter, residual shaper and forming the multiplier and a second input circuit "I", the output of which is the clock input of the distributor.

The invention is illustrated in Fig.9, Fig.10, Fig.11. The structural diagram of the proposed device is presented in Fig.9.

The device in Fig. 9 contains: a counter 1, a residual shaper 2, a register 3 forming a multiplier 4, a block for generating complex DFS systems 5, outputs 6 residual codes, an output 7 of the initial zero state, an output 8 of a number record, which is an input of the residual shaper , input 10 records the number of elements, input 11 records of the unit, input 12 of the beginning of calculation, input 13 of the record of the antiderivative element, output 14 of the end of the calculations of the forming multiplier, input 9 of the records of the elements, output 15 of the block for the formation of complex DFS systems, which is a clock control by the input of the generatrix of the multiplier, counter, register, information output 16 of the block for the formation of complex DFS systems.

Functional diagram of the generating multiplier is presented in figure 10. The forming multiplier 4 contains: a multiplication block 4-12, a shift register 4-3, the first, second and third elements “AND-NOT” 4-2, 4-4 and 4-11, element 4-5 “AND”, a group of elements 4-14 “And”, the first, second, third, fourth and fifth elements 4-1, 4-13, 4-10, 4-7, 4-6 delays, the counter 4-9 of the number of elements and the element “OR” 4 -8 with corresponding links.

The functional block diagram of the formation of complex systems of emergency (BFSS emergency) is presented in Fig.11. BFSS DCHS 5 contains: a decoder 5-1, a distributor 5-2, a clock pulse generator (GTI) 5-3, a group of 5-4 key circuits, a frequency synthesizer 5-5, an I circuit 5-6, a divider with a variable coefficient division (DPKD) 5-7, analog-to-digital converter (ADC) 5-8, containing: pulse generator (GI) 5-8.1, valve 5-8.2 and counter 5-8.3, "OR" 5-9, discrete source information (IDN) 5-10, the scheme "OR" 5-11 with the corresponding links.

The device as a whole works as follows.

Before you begin: the binary code of the number of the antiderivative element Q _{i of the} corresponding field GF (p ⁿ ) is written to input 4-12 of the multiplication of the generator of the multiplier 4 and, by input 11, is written “1”, and also to the counter of the number of elements 4–9 of the generator the multiplier and the divider 5-7 with a variable division factor BOSS DFS comes by input 10 code number p ⁿ elements of the field GF (p ⁿ ). By applying a pulse “beginning of calculation” at input 12, the device is turned on and, based on this pulse, the GTI 5-3 is started. The pulses from the output of the GTI 5-3 pass through the DPKD 5-7 to the output 15 and the BFSS DCHS will start to issue clock pulses on its first output 15. Based on the data of the clock pulses, the forming multiplier 4 multiplies Q _i by 1 by the multiplication unit 4-12, and upon completion of this multiplication, it generates, on its first output 7, an impulse of “reset to initial zero state” to counter 1 and register 3; writes the multiplication result to the 4–3 shift register with a parallel code and then starts at each subsequent clock moment to output from the first output of the 4–3 shift register by the second output of the “number record” 8 the parallel code of the multiplication result to the residual generator 2.

Эта последовательность параллельных двоичных кодов остатков a₁, а₂,…, а_j представляет собой последовательность элементов мультипликативной группы поля GF(pⁿ). Последовательность параллельных двоичных кодов остатков по выходам 6 поступает на БФСС ДЧС, где происходит образование сложных ДЧС в соответствии с информацией о числе элементов

, поступающей на второй вход 10 в БФСС ДЧС 5, и длительности Т_i информационного импульса информационной посылки (ИП). По окончании формирования элементов мультипликативной группы поля GF(pⁿ) счетчик 4-9 числа элементов выдает импульс «конец вычисления» и к выходу 14 образующего мультипликатора поступает импульс «конец вычисления». БФСС ДЧС 5, в котором с приходом последнего элемента мультипликативной группы поля GF(pⁿ) сформировался сложный сигнал, выдает в соответствии с тактовыми импульсами этот сложный сигнал по 16 выходу.And the residual generator 2, which is a number decoder in the residual classes, in turn generates the remainder of the number modulo p _i and outputs the result to register 3. Register 3 outputs the remainder of the number modulo p _i to the second inputs 9 of the “element record” of the generator multiplier 4 and the second group of inputs of the residual generator 2. This element is the remainder of the result of multiplying the unit by Q _i modulo p _i and is the first element a _{1 of the} multiplicative group of the Galois field GF (p ⁿ ). Generating multiplier 4 through the group of elements “AND” 4-14 generates on its third outputs 6 residual codes this first element a ₁ to the inputs of the BFSS DCHS and, in addition, the code of the residual element is recorded in the multiplier 4-12 of the generating multiplier 4, where the process of multiplying a ₁ on Q _i occurs. Then, the cycle of operations described earlier is repeated, and on the third outputs of 6 residual codes, the second element a _{2 of the} multiplicative group of the field GF (p ⁿ ) appears, etc. Thus, at the third outputs 6 residual codes of the multiplier 4, a sequence of residual codes appears, a ₁ ≡ Q _i (mod р _i ),

This sequence of parallel binary codes of residues a ₁ , ₂ , ..., and _j is a sequence of elements of the multiplicative group of the field GF (p ⁿ ). The sequence of parallel binary codes of residues at outputs 6 goes to the BFSS DES, where the formation of complex DFS occurs in accordance with information on the number of elements

arriving at the second input 10 in BFSS DCHS 5, and the duration T _{i of the} information pulse of the information package (IP). At the end of the formation of the elements of the multiplicative group of the field GF (p ⁿ ), the counter 4–9 of the number of elements gives an impulse “end of calculation” and to the output 14 of the forming multiplier an impulse “end of calculation” is received. BFSS DCHS 5, in which with the arrival of the last element of the multiplicative group of the field GF (p ⁿ ) a complex signal has been generated, this complex signal is generated in accordance with the clock pulses at the 16th output.

The device for generating RF signals has the following operating modes:

1. For a fixed duration of information sending T = const:

1.1 With the change of the antiderivative Q;

1.2 With a change in the module p _i .

2. When changing the duration of the information package T = var:

2.1 With a change in the antiderivative Q _i ;

2.2 With a change in the module p _i .

записывается в регистр 4-3 сдвига.The formation of the elements of the multiplicative groups of Galois fields GF (p ⁿ ) is provided by the generating multiplier 4. Its functional diagram is presented in FIG. 10. The forming multiplier works as follows. Before starting work, the multiplication block 4-12 is written respectively: by input 13, the binary code of the number of the antiderivative element Q _{i of the} corresponding field GF (p ⁿ ) in the multiplier register, by input 11, the binary code of the unit in the register of the multiplicative multiplication block 4-12 and by input 10 code the number of elements in the field GF (p ⁿ ) in the counter 4-9 number of elements. By applying a pulse "beginning of calculation" at the input 12 of the multiplication block 4-12, the device is turned on. The multiplication unit 4-12 multiplies the unit by Q _i and writes the result of the multiplication to the shift register 4-3 and, upon completion of the multiplication, generates an “end of multiplication” pulse to output 7 according to its output, bringing counter 1 and register 3 to the initial state, and on delay element 4-7. At the next clock moment, the pulse from the output of the delay element 4-7 opens the element 4-5 "AND", allowing the clock pulse from the output of the element 4-4 "AND-NOT" to go to the clock input of the shift register 4-3 and the delay element 4-6 , which ensures the opening of the element 4-5 "And" in subsequent clock moments and the passage of pulses to the clock input of the shift register. Thus, the number A ₁ = Q _i * 1 read from the register 4-3 in the binary code is received, starting from the least significant bit, to the output of the number 8 record and the corresponding input of the residual shaper 3, which is a logical node consisting of AND elements and "OR". The clock pulses arriving at clock input 15 accompany the pulses of the code read from register 4-3 of the number A ₁ and go to counter 1. The number of states of the counter 1 is determined by considering the remainder of dividing the weight of each bit of the read number A _i by the selected field module p _i GF (p ⁿ ). If the resulting sequence of digits has a repetition period, then the number of counter states 1 is equal to the number of digits in the period. If the result of the division represents a sequence of digits without a period, then the number of counter states 1 is equal to the number of bits in the transmitted number. The outputs of the counter 1 are connected to the inputs of the residual shaper 2 in such a way that the presence of each element “And” of the latter is determined by a certain correspondence between the state of the counter 1 and the subsequent discharge of the number. The output signals of the residual shaper 2 in the presence of clock pulses at the input 15 are stored in the register 3, which has the number of bits necessary to represent the smallest remainder modulo P _i . In this case, each trigger of register 3 corresponds to two “OR” elements of the residual shaper 2 (for setting to 0 or 1), and each “OR” element of the last corresponds to as many “And” elements of the latter as many possible situations lead to the translation of the trigger into the corresponding state. Thus, at the output buses of register 3, at each clock moment, a binary remainder code appears modulo p _i from the binary number received by this moment at the input of the residual generator 2. At the moment of reading the last (highest) digit of the number, the remainder code modulo p _i of the number a ₁ = A ₁ (mod p _i ) appears on the output buses of register 3. At the same moment, the register 4-3 is reset, and at the output of the multi-way element 4-2 AND-NOT appears the pulse "end of reading", which is fed to the other input of element 4-4 "NAND", thereby stopping the passage of clock pulses to the clock input of the register 4-3 and through the element 4-8 "OR" to the corresponding input of the block 4-12, bringing to the zero state its register of the multiplicable. At the next moment, having passed the delay element 4-1, this pulse goes to the counting input of the counter 4-9 of the number of elements and to the other inputs of the elements 4-14 "And", opening them and reading from the output buses of register 3 in the parallel code of the remainder a _i-1 modulo p _i from the number A ₁ to the outputs of 6 remainder codes and to the inputs of the record of the multiplicative number in the register of the multiplicative block 4-12 at the next clock moment. After passing through the delay element 4-13, this pulse passes through the AND-NOT element 4-11 to the start of multiplication input of block 4-12, ensuring the multiplication of the multiplier a ₁ = Q ₁ (mod p _i ) by the factor Q _i . Multiplication Result - Number

written to the shift register 4-3.

Then the cycle of operations described earlier for the number A _{2 is} repeated, and the remainder code appears on the output buses of the device, which is multiplied by Q _i in block 4-12, and the following result A ₃ = a ₂ * Q _{i is} written in register 4-3. Then the cycle of operations is repeated, etc. Thus, at the output 6 of the generating multiplier, a sequence of residual codes a _i appears. The process of generating this sequence of residual codes continues until the counter 4-9 of the number of elements, to the counting input of which the impulses “read moment a _j ” are received, overflows and generates an overflow pulse “end of formation”, which is output 14 and through element 4-8 "OR" to the corresponding input of device 4-12, resetting its register of the multiplicand, in which the code of the last remainder was recorded by this moment, and also through element 4-10 of the delay to another input of element 4-11 "AND NOT ", Prohibiting the passage of momentum from the output and 4-13 delay element to the input of the "beginning multiplication" block 4-12. In this case, the device is prepared for a new cycle of calculations and the formation of a sequence of codes of residual elements a _j .

Thus, at the outputs of 6 residual codes, a sequence of parallel binary residual codes a ₁ , ₂ , a ₃ , ..., and _{j is formed} , which is a sequence of elements of the multiplicative group of the Galois field GF (p ⁿ ), which are fed to the first inputs of the BFSS DES 5 BFSS DES 5 works as follows. The remainder-element a _j in the parallel code comes from the outputs of the codes of residues 6 of the generating multiplier 4 to the inputs of the decoder 5-1. Decoder 5-1 converts the binary code of a number into a signal (pulse) at only one of its outputs. This signal (impulse) is supplied to the control inputs of the distributor 5-2 and through the "OR" 5-9 circuit to the first input of the "And" circuit 5-6. The input of the analog-to-digital converter 5-8 from the output of the discrete information source 5-10 receives a sequence of information pulses from N-message sources, time-compressed (figure 4).

The main structural elements of an analog-to-digital converter (ADC) 5–8 are a pulse generator 5–8.1, a valve 5–8.2, and a counter 5–8.3 [10]. The ADC 5-8 converts the duration of the information pulse T into a digital code. The operation of the ADC 5-8 is as follows: for the time being, the information pulse opens the valve 5-8.2, the second input of which receives pulses from the pulse generator 5-8.1, from the output of the valve 5-8.2 these pulses are fed to the input of the counter 5-8.3. The counter reads the number n of incoming pulses, the number of which depends on the interval T (figure 5).

A parallel code corresponding to the number of pulses K is taken from the outputs of the counter 5-8.3. Thus, the analog-to-digital converter 5-8 converts the duration of the information pulse into a digital code, which is fed to the control inputs of the divider with a variable division ratio (DPD) 5-7. The pulses generator 5-3 are supplied to the first input of the DPKD 5-7, and the module code of the number p _{i is} sent to the second input. DPKD 5-7 in accordance with the digital code received at its inputs from the output of the ADC 5-8 and the module code of the number p _i changes the division coefficient and issues a sequence of pulses with a period following them changed in accordance with the code p _i . DPKD 5-7 can be performed as indicated, for example [11]. The sequence of pulses from the output 15 of the DPKD 5-7 is fed to the first inputs of the counter 1, register 3 and the generating multiplier 4 and will be a clock pulse sequence for them, as well as these pulses pass through the "I" circuit 5-6, opened by the signal from the output of the circuit "OR" 5-9, to the outputs of the distributor 5-2 through its second input in such a sequence, which is determined by the number of the input of the distributor 5-2, on which there is a signal from the decoder 5-1. From the corresponding outputs of the distributor 5-2, the pulses in the sequence corresponding to the element a _j are fed to the first inputs of the group of key circuits 5-4, to the second inputs of which the signals from elements 5-5.1 of the frequency synthesizer 5-5 are constantly fed, to the third - the signal from output of the source of discrete information 5-10.

A frequency synthesizer 5-5 is a collection of highly stable frequency generators 5-5.1.

Each information pulse at the output of the source of discrete information 5-10 corresponds to a certain remainder a _j at the input of the decoder 5-1, and therefore, as mentioned above, and a certain order of distribution of pulses from the output of the DPKD 5-7 to the outputs of the distributor 2, this can be traced as an example in figure 6.

Thus, the key circuits 5-4 will be opened alternately in the order defined for each information pulse and corresponding to a specific a _j , passing one of the harmonic frequencies of the frequency synthesizer 5-5 in the corresponding a to output 16 through the "OR" 5-11 element _j sequences. The sequence of opening the key circuits 5-4 determines the structure of the RF signal corresponding to a _j , and this order is determined by both the value of a _j and the antiderivative element of the field Q _i , and the module p _i , and the duration of the information transmission T. Thus, Each specific information package IP _{i of a} certain subscriber set i _k will correspond to its specific complex RF signal. Thus, at the output 16 of the block 5 for the formation of complex DFS systems, a sequence of DFS is formed in accordance with a sequence of parallel binary residual codes (a ₁ , a ₂ , ..., a _j ) at the output of generating multiplier 4, which is a sequence of elements of the multiplicative group of Galois fields GF (p ⁿ ). The operation of block 5 of the formation of complex RF signal systems in various modes is almost the same. In mode 1.1 (for a fixed duration T of information sending with a change in the antiderivative Q _i ), as a result of the change in the antiderivative Q _i , the sequence of element codes {a _j } of the same field GF (p ⁿ ) at the inputs of the decoder 5-1 changes. This leads to the fact that the signal (pulse) controlling the operation of the distributor 5-2 appears on the other output of the decoder 5-1, that is, on the other input of the distributor, and this changes the operating mode of the distributor 5-2, which will distribute the pulses in a different sequence, and therefore, to switch the group of circuits 5-4 "And" in a different sequence, which will lead to a change in the frequency and time position of the elements of the RF signal on the time-frequency matrix (see figa). In mode 1.2 (for a fixed duration T of the information packet with a change in the module code p _i ), as a result of a change in the code of the module p _i , the dividing factor of the 5-7 divider with a variable division coefficient changes, the output pulses of which are clock pulses for the generating multiplier 4, counter 1, register 3 and distributor 5-2. DPKD 5-7 changes the frequency of these clock pulses, and therefore, the distributor 5-2 will connect more or less (depending on p _i ) the number of “I” circuits from the group of 5-4 key circuits during a fixed duration T of information sending and, consequently, there is a change in the number of frequency intervals and elements of the DFS on the time-frequency matrix (see figb).

In mode 2.1 (with a change in the duration T of the information packet with a change in the antiderivative Q _i ), as a result of a change in the duration T of the information packet, the digital code at the outputs of the analog-to-digital converter 5-8 changes, and this code, which is the control code for the DPKD 5-7, changes the coefficient dividing the DPKD 5-7, therefore, will change the repetition rate of the output pulses of the DPKD 5-7, which are clock pulses for the forming multiplier 4, counter 1, register 3 and the distributor 5-2. Therefore, this will change the actual connection time of the group of key circuits 5-4, and therefore the actual time of frequency generation by the frequency synthesizer. As a result of the change in the antiderivative Q _i , the processes described in mode 1.1 occur. Therefore, in mode 2.1, there is a change in the frequency and time position of the elements of the DFD on the time-frequency matrix and the duration of the DFD (see Fig. 3c). In mode 2.2 (with a change in the duration T of the information packet with a change in the module p _i ), the duration of the information packet T changes, and therefore, the code on the outputs of the ADC 5-8 and the code of the module p _i . These codes are the control codes for the 5-7 DPKD and, as a result of the double control, the 5-7 DPKD changes the division ratio - the repetition rate of its output pulses, and this will change the actual connection time of the “I” circuit group 5-4, and therefore the actual generation time frequencies and will change the number of connected "I" circuits 5-4, i.e. number of frequency intervals. Therefore, in mode 2.2, there is a change in both the number of frequency intervals and the duration of the RF signal (see Fig. 3d).

можно сформировать любые другие последовательности сложных ДЧ сигналов. Изменяя структуру формирователя остатков 2 с целью формирования остатков по иному модулю Р_i, можно сформировать последовательности сложных сигналов других полей GF(p_i ⁿ), где p_i=var.Writing to the device codes of other primitive elements Q _i , other numbers of elements

any other sequences of complex RF signals can be generated. By changing the structure of the residual shaper 2 in order to form residues modulo P _i , one can form sequences of complex signals of other fields GF (p _i ⁿ ), where p _i = var.

Thus, the device allows you to implement:

Mode 1.1 - the formation of complex RF signals with the duration of the information sending T = const and the antiderivative Q _i = var (figa).

Mode 1.2 - the formation of complex RF signals with the duration of the information sending T = const, and the module p _i = var (fig.3b).

Mode 2.1 - the formation of complex RF signals with the duration of the information sending T = var and the antiderivative Q = var (Fig.3c).

Mode 2.2 - the formation of complex RF signals with the duration of the information sending T = var and the module p _i = var (Fig. 3d).

, где К_в можно трактовать как «ключевое число» для каждого режима. К_в тем самым регулируется как числом каналов N_к, так и

т.е. увеличивая только число каналов N_к, уже можно повышать имитостойкость информационной системы, приходящейся на 1 канал (фигура 7).Therefore, the proposed device can significantly increase the imitability of communication systems for special purposes, since it is possible to change the type (or type), shape and composition of the RF signals, which is provided by changing the form of the manipulating function that is directly responsible for the properties of the AFS. In addition, in any fixed mode, the informational messages of the IP of each i specific channel in each subsequent group time interval T _rpi will change the structure of the DFS, which ensures guaranteed "randomness" for an unauthorized observer of belonging of a specific type (structure) of DFS to a particular information channel. So in a fixed mode, the number of possible options for belonging to a particular type of DFS - the information package of a particular channel is equal to K _in = N _to × p ⁿ , hence the number

, where K _in can be interpreted as a “key number” for each mode. K _in this way is regulated by both the number of channels N _k and

those. by increasing only the number of channels N _k , it is already possible to increase the imitability of the information system per channel 1 (figure 7).

Figures 7a and b show that with the number of channels equal to three (Fig.7a) and the number of code residues equal to five (Fig.7b), the "key number" is fifteen. For example, the same channel will correspond to the first channel with an interval of K _in = 15. With an increase in the number of code residues (an increase in the number of possible DFS) in figures 7c and d, it is shown that with an increase in the number of code residues from five to seven, the “key number" K _b = 21. But the equality K _in = N _to × p ^{n is} not always fulfilled with the number of channels equal to the number of code residues (the number of DFS), each channel always has the same DFS. For example, figure 8a and b shows that with the number of channels equal to three, and the number of code residues equal to three, K _in ≠ N _to × p ⁿ ≠ 9.

где

Тем самым имитостойкость регулируется как числом каналов N_к, так и

т.е. увеличивая только число каналов N_K уже можно повышать имитостойскость информационной системы.Thus, the proposed device allows you to achieve the next level of resistance and stealth information transfer. As

Where

Thus, the imitation resistance is regulated by both the number of channels N _k and

those. by increasing only the number of channels N _{K it is} already possible to increase the imitability of the information system.

The proposed device can find application in applied computer technology, communication technology, in communication systems for special purposes with complex signals.

Claims (2)

1. The device for generating imitation-resistant systems of discrete-frequency signals with temporary information compression, containing a counter, the outputs of which are connected to the first group of inputs of the residual conditioner, the outputs of which are connected to the inputs of the register, the outputs of which are connected to the second group of inputs of the residual conditioner and with the recording inputs of the elements of the generator a multiplier, the control input of which is combined with the control inputs of the counter and register and is the clock input of the device, and the output of the installation to the initial zero The state of the generating multiplier is the corresponding counter and register input, and the generating multiplier also has: input of the antiderivative element record, input of the unit record, input of the start of calculation, input of recording the number of elements, output of the end of calculation, output of the number record, which is the input of the residual generator and outputs residual codes, and the forming multiplier contains: a multiplication block, a shift register, an element number counter, an AND element group, three AND-NOT elements, an OR element, an AND element, and five elements delays, the recording inputs of the elements of the forming multiplier are the first inputs of the AND elements of the group, the outputs of which are connected respectively to the inputs of the multiplication block and are the outputs of the remainder codes of the device, the outputs of the multiplication block are connected to the inputs of the shift register, the outputs of which are connected to the corresponding inputs of the first element AND-NOT, the output of which is connected to the first input of the second AND-NOT element, the first input of the OR element and the input of the first delay element, the output of which is connected to the second inputs of the element ntents of the group, the input of the second delay element and the inputs of the counter of the number of elements, the output of which is connected to the input of the third delay element, the second input of the OR element and is the output of the end of the device’s calculations, the output of the OR element is connected to the first input of the multiplication unit, the second input of which is an input for recording the number of elements of the device, the output of the second delay element is connected to the first input of the third AND-NOT element, the output of which is combined with the input of the device’s computing channel and the unit is connected to the third input and multiplication, the output of which is the output of the installation to its initial zero state and is connected to the input of the fourth delay element, the output of which is connected to the output of the fifth delay element and is connected to the first input of the "And" element, the output of which is connected to the input of the fifth delay element and the input of the shift register the output of which is connected to the input of the residual shaper, the output of the third delay element is connected to the second input of the third AND-NOT element, the second input of the AND element is connected to the output of the second AND-NOT element, the second One of which is the clock input of the device, and the fourth input of the multiplication block is the input of the recording unit of the device, characterized in that, in order to expand the class of tasks to form imitation-resistant systems of discrete-frequency signals with temporary compression of information, a unit for forming complex discrete systems is introduced into the device -frequency signals, the first inputs of which are connected to the outputs of the codes of the residuals of the forming multiplier, and the input recording the number of elements of the forming multiplier is combined with a second m input of the unit for generating systems of complex discrete-frequency signals, and the input of the beginning of calculation of the generator of the multiplier is combined with the third input of the unit for generating systems of complex discrete-frequency signals, and the first output of the unit for generating systems of complex discrete-frequency signals is a clock control input of the forming multiplier, counter, and register, and the second output of the unit for forming systems of complex discrete-frequency signals is the information output of the device. 2. The device according to claim 1, characterized in that the unit for generating systems of complex discrete-frequency signals contains: a decoder, “K” of inputs of which are the first inputs of the unit for forming systems of complex discrete-frequency signals, a “N” of outputs connected to the first “ N ”inputs of the distributor and“ N ”inputs of the“ OR ”circuit, the output of which is connected to the first input of the“ AND ”circuit, and“ n ”of the outputs of the distributor are connected to the first inputs of the group of key circuits, the second inputs of which are connected to the“ n ”outputs of the frequency synthesizer third inputs connected to you the steps of the source of discrete information, and the outputs through the multi-input circuit "OR" are connected to the output of the device, and the output of the source of discrete information is connected to the input of an analog-to-digital converter, the outputs of which are connected to the third inputs of the divider with a variable division ratio, the second input of which is the input of the number record elements, and the first input is the output of the clock generator, and the output of the divider with a variable division coefficient is the first input of the counter, the shaper of residues and formatively th multiplier and is the second input of the “AND” circuit, the output of which is the clock input of the distributor.

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