RU2012994C1 - Device for automatic control of level of signal - Google Patents

Abstract

FIELD: radio engineering. SUBSTANCE: device for automatic control of level of signal has controlled amplifier 1, reversible counter 2, comparators 3, 4, 5, AND gates 6, 7, 14, clock pulse generators 8, 9, delay elements 10, flip-flops 12, 13, register 14 of sequential approximation. EFFECT: increased speed of response in operation with radio pulses with keeping of smoothness of amplification control under condition of maintenance of radio pulse amplitude at required level. 2 dwg

Description

 The invention relates to radio engineering and can be used in amplifiers of electrical signals, the frequency of which varies widely according to complex laws, as well as in amplifiers of radio pulses.

 The aim of the invention is to increase performance.

 In FIG. 1 is a structural electrical diagram of a device for automatically adjusting the signal level; in FIG. 2 are diagrams illustrating the operation of the device.

 The device for automatically adjusting the signal level contains an adjustable amplifier 1, a reversible counter 2, the first, second and third comparators 3, 4 and 5, the first and second elements 6 and 7, the first and second clock generators 8 and 9, the delay element 10, RS -trigger 11, register 12 sequential approximation, D-trigger 13 and the third element And 14.

 The device operates as follows.

The signal is fed to the input of an adjustable amplifier 1 and from its output goes to the inputs of comparators 3-5. In the second comparator 4, the maximum threshold level U _{max is set} and the maximum signal value is monitored, in the first comparator 3, the minimum threshold level U _min is controlled and the minimum signal value is monitored. The threshold of the third comparator 5 is set at the minimum threshold of detection of the useful signal against the background of noise with a given probability.

 Suppose at the initial time, the signal at the input of amplifier 1 is absent. In this case, the generators 9, 8 will not be triggered by pulses from the third comparator 5, and the first generator 8 will go into auto-generation mode. At the same time, in the first generator 8 there is an output of the operation mode indication signal: auto-generation or external start (for example, during auto-generation the level is “log. 1” in the external start mode - “log. 0”). Thus, in the absence of a signal at the input of the adjustable amplifier 1, at this output of the first generator 8 there will be a level of “log. 1”, which, coming to the S-input of the D-trigger 13, will switch it to the state of “log. 1”, and entering The S-input of register 12, will transfer it to its initial state with the levels of "log. 1" on all binary outputs. The level of "log. 1" from the output of the S-flip-flop 13 will put the reversible counter 2 into the pre-recording mode, the levels of "log. 1" from the register 12 will be transferred to the counter 2 and, as a result, the gain of the amplifier 1 will become maximum.

 For a better understanding of the principle of operation of the device, we explain the essence of the sequential approximation register, which consists in changing each bit (starting from the highest) bit of the binary code at the output of the register and, depending on the logical level at the D-input, introducing corrections to the corresponding bit. The D-input of the register must receive information characterizing more or less the value of the binary code at the output of the register of the required value. In the device, the value of the binary code at the output of the register determines the gain of amplifier 1, and the criterion that determines which logic level to set at the corresponding bit is the signal from the second comparator 4, fed to the register D-input. If the signal at the output of the adjustable amplifier 1 exceeds the threshold of the second comparator 4 (on the D-input - “log. 1”), then the logic zero level is set on this bit (the gain of the adjustable amplifier 1 decreases), if the signal from the adjustable amplifier 1 is lower than the threshold of the second comparator 4 (on the D-input - “log. 0”), then “log. 1” should be set on this category (the gain of the adjustable amplifier 1 will increase). All changes in the register state occur at the clock pulses at the C-input from the first generator 8. Thus, sequentially sorting through all the bits, the required gain of the adjustable amplifier 1 will be set in no more than n steps, where n is the number of bits of the reversible counter 2.

 We continue to consider the operation of the proposed device. Suppose that a sufficiently large amplitude radio pulse arrives at the input of an adjustable amplifier 1 (see Fig. 2, a). Pulses from the output of the third comparator 5 will trigger the generators 8, 9; the first generator 8 will go into external start-up mode and at its output an indication signal of the operating mode, and therefore at the S-inputs of trigger 13 and register 12, the level “log. 0” will be set. At the output of the trigger 13 (the input of the preliminary installation of the reversible counter 2) the level “log. 1” will be saved, and therefore, the reversible counter 2 will not be controlled by the counting inputs. In the first period of the input signal, the signal from the first generator 8 (see Fig. 2, b) the senior (first) bit of the register 12 will be set to "log. 0" (ie, the gain of the adjustable amplifier 1 will be reduced by half). This happened due to the fact that at the D-input of register 12 there was a “log. 1” level, characterizing that the signal from the adjustable amplifier 1 exceeded the maximum threshold of the second comparator 4 (see Fig. 2, c). The pulse received at the C-input of the D-flip-flop 13 (see Fig. 2, e) will not change the state of the trigger, since at this moment in time there will be a “log. 1” level on the D-input (see Fig. 2, c ), and therefore the reversible counter 2 will remain in the pre-recording mode. If in the second period of the signal its amplitude again exceeds the maximum threshold level of the second comparator 4, then in the next (second) category of register 12 the level “log. 0” will be set, and the gain of the adjustable amplifier 1 will again decrease by 1.5 times, and the reversible counter 2 will remain in pre-recording mode. Suppose, in the third period of the signal, its amplitude dropped below the minimum threshold of the first comparator 3. At the same time, at the moment the pulse 12 from the first generator 8 appears at the C-input of register 12, the “log. 0” level from the second comparator 4 will be at the D-input of register 12 , and the code at the output of register 12 will increase by half of the corresponding category (in this case, the second), that is, in the second category, “log. 1” will be set, and in the third, “log. 0”. There will be no pulse to the C-input of trigger 13, since the level “log. 0” from the first comparator 3 will be present at the other input of the third AND element 14, and therefore, the state of the D-trigger 13 will remain the same. If in the fourth period of the signal its amplitude falls within the limits between the maximum and minimum thresholds of the comparators 4, 3, then the pulse from the third element And 14 (see Fig. 2, e) will switch the D-trigger 13 at the C-input to the "log" state. 0 "(since at that moment the D-input will have a level of" log. 0 "from the second comparator 4), the reverse counter 2 will switch to the counting mode and will be controlled by the inputs of the direct and reverse counts from the outputs of the elements And 6, 7. B In this mode, the gain of the adjustable amplifier is adjusted continuously with 1 binary code. reverse counter stroke 2.

 If the amplitude of the input signal is below the maximum threshold level, but above the minimum, the device operates as follows. From the second comparator 4 there is no signal opening the second element And 7 and the pulses from the second generator 9 do not pass to the subtraction input of the reverse counter 2. When the amplitude of the input signal exceeds the minimum threshold level, the pulses from the first comparator 3 are fed to the R-input of the RS flip-flop 11, which is in the state "log. 0" and the first element And 6 is locked. The delay element 10 as which can be used, for example, a counter that generates a delay by counting a certain number of pulses from the first generator 8, with each pulse from the first comparator 3 fed to the reset input, comes to its initial state and the pulses to the S-input RS- trigger 11 is not served. Therefore, the first element And 6 is constantly locked and the signal from the first generator 8 does not pass to the input of the addition of the reversible counter 2. Thus, in this mode, the gain of the adjustable amplifier 1 does not change. If in steady state the signal amplitude exceeds the maximum threshold level, pulses appear at the output of the second comparator 4, opening the second element And 7. Pulses from the second generator 9 through the second element And 7 are fed to the input of the reversible counter 2, which reduces the gain of the adjustable amplifier 1 to as long as the amplitude of the input signal does not decrease below the threshold of the second comparator 4. The signal at the output of the second comparator 4 disappears, the second element And 7 is closed and does not pass pulses from of the second generator 9. The state of the reverse counter 2 does not change and the process of decreasing the gain stops. If in one period of the input signal its amplitude has not decreased below the maximum threshold, then the described process continues in subsequent periods until the amplitude reaches the desired level.

 When the amplitude of the input signal in the steady state decreases below the minimum threshold of the first comparator 3, the device operates as follows. The pulses from the third comparator 5 start the first generator 8, so that its frequency is equal to the frequency of the input signal. If during the delay time of the delay element 10, the amplitude of the input signal never exceeds the minimum threshold, the pulses from the first comparator 3 do not go to the reset input of the delay element 10, and an output appears that is applied to the S-input of the RS-trigger 11 and transferring it to logical state "1". In this case, the first element And 6 opens, and the pulses from the first generator 8 pass to the input of the reverse counter 2, which increases the gain of the adjustable amplifier 1 until the input signal exceeds the minimum holding threshold. When the amplitude of the input signal exceeds the threshold of the first comparator 3, the pulse from the first comparator 3, applied to the R-input of the RS-trigger 11, transfers the RS-trigger to the logical "0" state, and the delay element 10 to its initial state, the first element And 6 it closes, the state of the reverse counter 2 does not change, and the process of increasing the gain stops. (56) Copyright certificate of the USSR N 1425811, cl. H 03 G 3/20, 1987.

Claims (1)

 AUTOMATIC SIGNAL LEVEL CONTROL DEVICE, comprising an adjustable amplifier, to the control input of which a reversible counter is connected, a first clock pulse generator and a first element And connected in series, a second counter clock input and a second clock pulse generator and a second AND element are connected in series which is connected to the subtraction input of the reverse counter, RS-trigger, the output of which is connected to another input of the first element And, the delay element and, connected between the output of the first clock generator and the S-input of the RS-flip-flop, as well as the first comparator, connected between the output of the adjustable amplifier and the combined R-input of the RS-flip-flop, and the reset input of the delay element, the second comparator, connected between the output of the adjustable amplifier and another input of the second element And, and a third comparator connected between the output of the adjustable amplifier and the start inputs of the first and second clock generators, characterized in that, in order to improve performance, it a D-flip-flop, the output of which is connected to the preliminary recording input of the reverse counter, a third AND element, the inputs of which are connected respectively to the outputs of the D-flip-flop, the first comparator and the first clock generator, and the output - to the C-input of the D-flip-flop, and register sequential approach, the outputs of the discharges of which are connected to the inputs of the preset counter-clock, the D- and C-inputs of the sequential approximation register are connected respectively to the outputs of the second comparator and the first clock generator x pulses, and S-inputs of the successive approximation register and the D-flip-flop connected to the output signal indicating the operating mode of the first clock pulse generator.

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