KR20220074700A - Gate driving circuit and electroluminescence display device using the same - Google Patents

Abstract

An electroluminescent display device according to an embodiment of the present specification includes a display panel divided into a display area including a plurality of pixel lines and a non-display area including a gate driving circuit providing gate signals to the plurality of pixel lines. In addition, each of the plurality of pixel lines includes a plurality of pixels, each of the plurality of pixels includes a pixel driving circuit and a light emitting device, and the pixel driving circuit and the gate driving circuit are implemented with a p-type transistor and an n-type transistor, respectively, The gate driving circuit provides a gate signal to the n-type transistor of the pixel driving circuit. Accordingly, a stable output may be provided and a non-display area of the display panel may be reduced.

Description

GATE DRIVING CIRCUIT AND ELECTROLUMINESCENCE DISPLAY DEVICE USING THE SAME

The present specification relates to a gate driving circuit with improved driving capability and an electroluminescent display device using the same.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of various types of display devices such as an electroluminescent display device, a liquid crystal display device, an organic light emitting display device, and a quantum dot display device is increasing.

Among them, the electroluminescent display device has advantages of fast response speed, high luminous efficiency, and a large viewing angle. In general, an electroluminescent display device applies a data voltage to a gate electrode of a driving transistor using a transistor turned on by a scan signal, and charges a data voltage supplied to the driving transistor to a storage capacitor. Then, the light emitting device emits light by outputting the data voltage charged in the storage capacitor using the light emission control signal. The light emitting device may include an organic light emitting device, an inorganic light emitting device, and a quantum dot device.

A gate signal and a data signal are supplied to the electroluminescent display device, and the gate signal includes a scan signal and an emission signal. The electroluminescent display device is driven using an emission signal and one or more scan signals. In general, a gate driving circuit generating a scan signal may include a shift register for sequentially outputting the gate signal.

A display panel, which is a minimum device for displaying an image, has a pixel array disposed therein, and may be divided into a display area for displaying an image and a non-display area for not displaying an image. The gate driving circuit is attached to a display panel in the form of a chip on film or chip on glass, or a gate-in-panel formed by a combination of thin film transistors in a bezel area that is a non-display area of the display panel. It is sometimes implemented in the form of (Gate In Panel, hereinafter GIP). The GIP type gate driving circuit has stages corresponding to the number of gate lines, and each stage outputs gate pulses supplied to the corresponding gate lines on a one-to-one basis. The gate line supplies a gate signal to the pixel array disposed in the display area so that the light emitting device can emit light.

Accordingly, in order to transmit an accurate signal to the pixel array, a method for improving the driving capability and reliability of the gate driving circuit is being sought.

As mentioned above, the electroluminescent display includes a pixel array and a gate driving circuit for providing at least one emission signal and a scan signal to the pixel array.

Each pixel constituting the pixel array includes a light emitting device and a pixel driving circuit providing a driving current to the light emitting device. The pixel driving circuit may be implemented in various forms to provide an accurate current to the light emitting device. Attempts have been made to reduce the leakage current of the transistor by using an n-type transistor in order to ensure reliability of the pixel driving circuit. Accordingly, a gate driving circuit for stably providing a gate signal to such an n-type transistor is required.

An object to be solved according to an embodiment of the present specification is to provide a gate driving circuit for outputting a gate signal to be provided to an n-type transistor and an electroluminescent display device using the same.

SUMMARY An object of the present specification is to provide a gate driving circuit capable of reducing a non-display area of a display panel and an electroluminescent display device using the same.

An object to be solved according to an embodiment of the present specification is to provide a gate driving circuit capable of maintaining a stable output even when driving at a low speed, and an electroluminescent display device using the same.

The tasks of the present specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In the gate driving circuit according to an embodiment of the present specification, the gate driving circuit is controlled by a Q node and is controlled by a pull-down unit that transfers a low voltage to an output node, a QB node and a high voltage of the third clock signal to the output node. A pull-up unit transferring a level voltage, a Q node controller controlled by the first clock signal and transferring a start signal to the Q node, a QB node controller controlled by the Q node to transfer a high voltage to the QB node, and a Q node and a Q node holding unit including a second capacitor controlled by the fourth clock signal and connected to the Q node. In addition, the QB node controller includes an n-type transistor and a p-type transistor connected to the Q node. Accordingly, it is possible to provide a stable output even during low-frequency driving.

In the electroluminescent display device according to the exemplary embodiment of the present specification, the electroluminescent display device includes a display region including a plurality of pixel lines and a non-display region including a gate driving circuit providing gate signals to the plurality of pixel lines. A separate display panel is included. In addition, each of the plurality of pixel lines includes a plurality of pixels, each of the plurality of pixels includes a pixel driving circuit and a light emitting device, and the pixel driving circuit and the gate driving circuit are implemented with a p-type transistor and an n-type transistor, respectively, The gate driving circuit provides a gate signal to the n-type transistor of the pixel driving circuit. Accordingly, a stable output may be provided and a non-display area of the display panel may be reduced.

Details of other embodiments are included in the detailed description and drawings.

According to the exemplary embodiments of the present specification, by using a gate signal generating circuit including a pull-down unit, a pull-up unit, a Q node control unit, and a QB node control unit, image quality of a display panel may be improved and power consumption may be reduced.

And, according to the embodiments of the present specification, by using the gate signal generating circuit including both the n-type transistor and the p-type transistor, the bezel area of the display panel can be reduced and the reliability of the gate signal generating circuit can be secured.

And, according to the exemplary embodiments of the present specification, reliability of a signal output from the gate signal generating circuit may be improved by using the gate signal generating circuit including the Q node holding unit for maintaining the Q node voltage.

Since the contents of the specification described in the problems, problem solving means, and effects to be solved above do not specify essential features of the claims, the scope of the claims is not limited by the matters described in the contents of the specification.

1 is a block diagram of an electroluminescent display device according to an exemplary embodiment of the present specification.
2 is a block diagram of a gate driving circuit according to a first embodiment of the present specification.
3 is a circuit diagram of a gate driving circuit according to the first embodiment of the present specification.
4 is a waveform diagram of gate signals input to the gate driving circuit according to the first embodiment of the present specification.
5 is a block diagram of a gate driving circuit according to a second embodiment of the present specification.
6 is a circuit diagram of a gate driving circuit according to a second embodiment of the present specification.
7 is a waveform diagram of gate signals input to a gate driving circuit according to a second exemplary embodiment of the present specification.
8 is a circuit diagram of a gate driving circuit according to a third embodiment of the present specification.
9 is a waveform diagram of gate signals input to a gate driving circuit according to a third exemplary embodiment of the present specification.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, when the temporal relationship is described as 'after', 'following', 'after', 'before', etc., 'immediately' or 'directly' Unless ' is used, cases that are not continuous may be included.

Each feature of the various embodiments of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

In the present specification, the gate driving circuit formed on the substrate of the display panel may be implemented as an n-type or p-type transistor. For example, the transistor may be implemented as a transistor having a metal oxide semiconductor field effect transistor (MOSFET) structure. A transistor is a three-electrode device including a gate electrode, a source electrode, and a drain electrode. The source electrode supplies a carrier to the transistor. In the transistor, carriers begin to migrate from the source. The drain electrode is an electrode through which carriers exit the transistor. The source electrode and the drain electrode of the transistor are not fixed, and the source electrode and the drain electrode of the transistor may be changed according to an applied voltage.

Hereinafter, the gate on voltage is the voltage of the gate signal at which the transistor can be turned on, and the gate off voltage is the voltage at which the transistor is turned off. voltage that can be

Hereinafter, a gate driving circuit according to an embodiment of the present specification and an electroluminescent display device using the same will be described with reference to the accompanying drawings.

1 is a block diagram of an electroluminescent display device 100 according to an exemplary embodiment of the present specification.

Referring to FIG. 1 , in an electroluminescent display device 100 according to an exemplary embodiment of the present specification, a plurality of data lines DL and a plurality of gate lines GL are disposed, and a plurality of data lines DL and a plurality of data lines DL are disposed. The display panel 110 may include a display panel 110 in which a plurality of sub-pixels PX connected to the gate line GL are arranged, and a driving circuit providing a driving signal to the display panel 110 .

The sub-pixels PX are arranged in a matrix form and are illustrated as constituting a pixel array, but the present invention is not limited thereto and may be arranged in various forms.

The driving circuit includes a data driving circuit 120 providing a data signal to the plurality of data lines DL, a gate driving circuit GD providing a gate signal to the plurality of gate lines GL, a data driving circuit 120 and The controller 130 for controlling the gate driving circuit GD may be included.

The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA that is an outer area of the display area DA. A plurality of sub-pixels PX may be disposed in the display area DA. A data line DL providing a data signal to the plurality of subpixels PX and a gate line GL providing a gate signal may be disposed.

The plurality of data lines DL disposed in the display area DA may extend to the non-display area NDA and may be electrically connected to the data driving circuit 120 . The data line DL electrically connects the sub-pixel PX and the data driving circuit 120 and may be implemented as a single wire, or may be implemented by connecting a plurality of wires through a contact hole using a link wire. may be

The plurality of gate lines GL disposed in the display area DA may extend to the non-display area NDA and may be electrically connected to the gate driving circuit GD. The gate line GL electrically connects the subpixel PX and the gate driving circuit GD. Additionally, gate driving related lines necessary for the gate driving circuit GD to generate or drive gate signals may be disposed in the non-display area DA. For example, the gate driving-related wirings include one or more high-level gate voltages for supplying a high-level gate voltage to the gate driving circuit GD, and one or more low-level gates for supplying a low-level gate voltage to the gate driving circuit GD. It may include a voltage line, a plurality of clock lines supplying a plurality of clock signals to the gate driving circuit GD, and one or more start wirings supplying one or more start signals to the gate driving circuit GD, and the like.

In the display panel 110 , the plurality of data lines DL and the plurality of gate lines GL are disposed in the subpixels PX. For example, the plurality of data lines DL and the plurality of gate lines GL may be arranged in rows or columns, respectively. For convenience of description, the plurality of data lines DL are arranged in columns, and the plurality of gate lines (GL) is assumed to be arranged in rows.

The controller 130 starts scanning according to the timing implemented in each frame, converts the input image data input from the outside to match the data signal format used by the data driving circuit 120, and outputs the converted image data, Controls the data drive at an appropriate time according to the scan.

The controller 130 receives, from the outside, timing signals including a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a clock signal together with the input image data. The controller 130 receiving the timing signals generates and outputs control signals for controlling the data driving circuit 120 and the gate driving circuit GD.

For example, the controller 130 outputs various data control signals including a source start pulse, a source sampling clock, and a source output enable signal to control the data driving circuit 130 . The source start pulse controls the data sampling start timing of one or more data signal generating circuits constituting the data driving circuit 120 . The source sampling clock is a clock signal that controls the sampling timing of data in each of the data signal generating circuits. The source output enable signal controls the output timing of the data driving circuit 120 .

In addition, the controller 130 outputs a gate control signal including a gate start pulse, a gate shift clock, and a gate output enable signal to control the gate driving circuit GD. The gate start pulse controls the operation start timing of one or more gate signal generating circuits constituting the gate driving circuit GD. The gate shift clock is a clock signal commonly input to one or more gate signal generating circuits, and controls shift timing of a scan signal (or gate pulse). The gate output enable signal specifies timing information of one or more gate signal generating circuits.

The controller 130 may be a timing controller used in a conventional display device technology or a control device capable of further performing other control functions including the timing controller.

The controller 130 may be implemented as a separate component from the data driving circuit 120 , or may be integrated with the data driving circuit 120 and implemented as a single integrated circuit.

The data driving circuit 120 may be implemented by including one or more data signal generating circuits. The data signal generating circuit may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like. The data signal generating circuit may further include an analog-to-digital converter in some cases.

The data signal generating circuit is configured to bond the display panel 110 by a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP) method. It may be connected to the pad, may be directly disposed on the display panel 110 , or may be disposed integratedly on the display panel 110 . In addition, the plurality of data signal generating circuits may be implemented in a chip on film (COF) method mounted on a source-circuit film connected to the display panel 110 .

The gate driving circuit GD sequentially supplies a scan signal to the plurality of gate lines GL to drive the subpixels PX connected to the plurality of gate lines GL. The gate driving circuit GD may include a shift register, a level shifter, and the like.

The gate driving circuit GD is a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP, Chip on panel) method for the display panel 110 . It may be connected to a bonding pad of the , or may be implemented as a GIP type and integrated in the display panel 110 . In addition, the plurality of gate signal generating circuits may be implemented in a chip on film (COF) method mounted on a gate-circuit film connected to the display panel 110 . Hereinafter, for convenience of description, the gate driving circuit GD includes a plurality of gate signal generating circuits, and the plurality of gate signal generating circuits are implemented in a GIP type to be disposed in the non-display area NDA of the display panel 110 . For example, when it is placed

The gate driving circuit GD sequentially supplies a scan signal of a transistor turn-on voltage or a transistor turn-off voltage to the plurality of gate lines GL under the control of the controller 130 . When a specific gate line is opened by the gate driving circuit GD, the data driving circuit 120 converts the image data received from the controller 130 into an analog data signal and supplies it to the plurality of data lines DL.

The data driving circuit 120 may be located on one side of the display panel 110 . For example, it may be an upper side, a lower side, a left side, or a right side of the display panel 110 . Also, the data driving circuit 120 may be located on both sides of the display panel 110 according to a driving method, a panel design method, and the like. For example, it may be upper and lower sides, or left and right sides of the display panel 110 .

The gate driving circuit GD may be located on one side of the display panel 110 . For example, it may be an upper side, a lower side, a left side, or a right side of the display panel 110 . Also, the data driving circuit 120 may be located on both sides of the display panel 110 according to a driving method, a panel design method, and the like. For example, it may be upper and lower sides, or left and right sides of the display panel 110 .

Hereinafter, the data driving circuit 120 is positioned above the display panel 110 and the gate driving circuit GD is positioned on both the left and right sides of the display panel 110 as an example. In this case, the width W of the region occupied by the gate driving circuit GD of the display panel 110 may be referred to as a bezel, and since the smaller the bezel has an aesthetic effect of the electroluminescent display 100 , the bezel may be reduced. There is a demand to simplify the gate driving circuit GD in order to reduce the size.

The plurality of gate lines GL disposed on the display panel 110 may include a plurality of scan lines and a plurality of light emission control lines. The plurality of scan lines and the plurality of emission control lines are wirings that transmit different types of gate signals to gate nodes of different transistors.

Accordingly, the gate driving circuit GD outputs light emission control signals to a plurality of scan driving circuits that output scan signals to a plurality of scan lines that are one type of the gate line GL and a plurality of light emission control lines that are another type of the gate line GL. It may include a plurality of light emitting driving circuits.

2 is a block diagram of the gate driving circuit GD according to the first embodiment of the present specification. Specifically, FIG. 2 illustrates a gate driving circuit GD and a pixel line PG to which a signal output from the gate driving circuit GD is applied according to an exemplary embodiment of the present specification.

The display area DA includes a plurality of sub-pixels PX, and displays an image based on a gray level displayed by each of the sub-pixels PX. As mentioned above, for example, each sub-pixel PX is connected to a data line DL arranged along a column line, and a gate line GL is arranged along a pixel line. is connected with In this case, the subpixels PX located on the same row line are referred to as pixel lines PG, and the subpixels PX located on the same pixel line share the same gate line GL and simultaneously provide a gate signal. receive Accordingly, the subpixels PX connected to the first gate line are referred to as a first pixel line PG(1), and the subpixels PX connected to the nth gate line are referred to as the nth pixel line PG(n). )) can be referred to as When the number of pixel lines disposed in the display area DA is p, the first pixel line to the p-th pixel line are sequentially driven in synchronization with the gate signal generating circuit.

As mentioned above, the display panel 110 includes a display area DA displaying an image based on the sub-pixels PX and a non-display area NDA in which a signal line or a driver is located and not displaying an image. includes

The sub-pixel PX includes a light emitting device and a pixel driving circuit that controls the amount of current applied to the anode of the light emitting device. The pixel driving circuit may include a driving transistor for controlling the amount of current so that a constant current can flow through the light emitting device. The light emitting element emits light during the light emission period, and does not emit light during periods other than the light emission period. In a period other than the light emission period, the pixel driving circuit may be initialized, a scan signal may be input to the pixel driving circuit, and a programming and pixel driving circuit compensation period may be performed. For example, the pixel driving circuit compensation may be a threshold voltage compensation of the driving transistor. In a period other than the light-emitting period, the light-emitting element must not emit light because a current capable of emitting light with a specific luminance is not constantly supplied to the light-emitting element. For example, in a way that the light emitting device does not emit light, an emission transistor may be connected between the anode of the light emitting device and the driving transistor. The emission transistor is connected to the emission line and controlled by the emission signal output from the emission driver. In the emission period, the emission signal may be a turn-on voltage, and in periods other than the emission period, the emission signal may be a turn-off voltage.

The gate signal for driving the sub-pixels PX included in the display panel 110 includes a scan signal and an emission signal. Accordingly, the gate driving circuit GD may separately include a driver applying a scan signal and a driver applying an emission signal. The scan signal is applied to the pixel line PG through the scan line, and the emission signal is applied to the pixel line PG through the emission line.

The gate driving circuit GD of FIG. 2 displays only a driver that applies a scan signal. When the number of pixel lines included in the display area DA is p, the gate driving circuit GD according to the exemplary embodiment of the present specification generates the first gate signal generating circuit SGD( 1 ) to the pth gate signal. circuit SGD(p). FIG. 2 shows only the nth gate signal generating circuits SGD(n) to (n+3)th gate signal generating circuits SGD(n+3) among them. In this case, p and n are natural numbers, and 1≤n≤p.

The gate driving circuit GD includes a first clock signal GCLK1 , a second clock signal GCLK2 , a low voltage VGL, a high voltage VGH, a first start signal Vst1 , and a second start signal Vst2 . ) to which the wires are applied. For example, the low voltage VGL may be -4.5V to -6.5V, and the high voltage VGH may be 12V to 13V. The n-th gate signal generating circuit SGD(n) provides the scan signal to the n-th pixel line PG(n) while shifting the first start signal Vst1 in response to the first clock signal GCLK1 .

The first start signal Vst1 is input to the first gate signal generating circuit SGD(1), and the second start signal Vst2 is input to the second gate signal generating circuit SGD(2). Each of the three gate generating circuits SGD( 3 ) to the pth gate generating circuit SGD(p) operates by receiving a scan signal output from the previous gate generating circuit of the previous gate generating circuit as a start signal. , the nth output signal Vgout(n) of the nth gate signal generating circuit SGD(n) is input as a start signal of the (n+2)th gate signal generating circuit SGD(n+2), It is input to the nth pixel line PG(n).

The first clock signal GCLK1 and the second clock signal GCLK2 swing between a high level voltage and a low level voltage, respectively, and have the same period. However, the first clock signal GCLK1 and the second clock signal GCLK2 have different phases. Specifically, the second clock signal GCLK2 is a signal in which the phase of the first clock signal GCLK1 is shifted by 180 degrees.

In FIG. 2 , the first clock signal GCLK1 is input to the nth gate signal generating circuit SGD(n) and the (n+2)th gate signal generating circuit SGD(n+2), and the (n+)th gate signal generating circuit SGD(n+2) 1) The second clock signal GCLK2 is input to the gate signal generating circuit SGD(n+1) and the (n+3)th gate signal generating circuit SGD(n+3). That is, the first clock signal GCLK1 is input to the odd-numbered gate signal generating circuit included in the gate driving circuit GD according to the first embodiment of the present specification, and the second clock signal GCLK1 is input to the even-numbered gate signal generating circuit. GCLK2) is input. Although the first clock signal GCLK1 and the second clock signal GCLK2 are alternately connected to the plurality of gate signal generating circuits in sequence, the order is not limited thereto.

3 is a circuit diagram of a gate signal generating circuit according to the first embodiment of the present specification. 3 illustrates an n-th gate signal generating circuit SGD(n) constituting the gate driving circuit GD as an example.

Referring to FIG. 3 , the n-th gate signal generating circuit SGD(n) includes a pull-down unit PD, a pull-up unit PU, a Q node control unit CQ, and a QB node control unit CQB.

The pull-down unit PD outputs the n-th output signal Vgout(n) as a turn-off voltage in response to the voltage of the Q node, and the pull-up unit PU responds to the voltage of the QB node and outputs the n-th output signal ( Vgout(n)) is output as a turn-on voltage. The n-th output signal Vgout(n) determined by the pull-down unit PD and the pull-up unit PU is applied to the n-th pixel line PG(n).

The Q node controller CQ is a component for charging or discharging the Q node, and applies a turn-on voltage or a turn-off voltage to the Q node using the first start signal Vst1. When n is a natural number equal to or greater than 3, the (n-2)th output signal Vgout(n-2) of the (n-2)th gate signal generation circuit SGD(n-2) can be used as a start signal.

The QB node controller CQB is a component for charging or discharging the QB node, and applies a turn-on voltage or a turn-off voltage to the QB node according to the Q node voltage applied by the Q node controller CQ.

The turn-off voltage varies depending on the type of transistor to which the turn-off voltage is applied. The turn-off voltage is a high voltage for a p-type transistor and a low voltage for an n-type transistor. In addition, the turn-on voltage is a low voltage in the case of a p-type transistor and a high voltage in the case of an n-type transistor. The n-th gate signal generation circuit SGD(n) according to the exemplary embodiment of the present specification includes both an n-type transistor and a p-type transistor. The n-th output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) is provided to a pixel driving circuit included in the n-th pixel line PG(n). In particular, when the pixel driving circuit is implemented with an n-type transistor and a p-type transistor, the n-th output signal Vgout(n) may control turn-on and turn-off of the n-type transistor, but is not limited thereto. .

A specific circuit structure and operation of the n-th gate signal generating circuit SGD(n) will be described below.

4 is a waveform diagram of gate signals input to the gate signal generating circuit according to the first embodiment of the present specification.

3 and 4 , the first start signal Vst1 and the second start signal Vst2 each have a high-level pulse of 4 horizontal periods 4H, and the second start signal Vst2 has a first start It is a signal shifted by two horizontal periods (2H) from the signal Vst1. Each of the first clock signal GCLK1 and the second clock signal GCLK2 has a period of 4 horizontal periods 4H. Each of the first clock signal GCLK1 and the second clock signal GCLK2 has a low-level pulse corresponding to a period shorter than two horizontal periods 2H and a high-level pulse corresponding to a period longer than two horizontal periods 2H. . Accordingly, each of the first clock signal GCLK1 and the second clock signal GCLK2 has a low level pulse shorter than half a period and a high level pulse longer than half a period. For example, when the time point at which the low-level voltage of the first start signal Vst1 is converted to the high-level voltage overlaps the low-level pulse of the first clock signal GCLK1, an output signal may not be generated. To solve this problem, the length of the low level pulse of the first clock signal GCLK1 may be shorter than the length of the high level pulse. In the second clock signal GCLK2 , like the first clock signal GCLK1 , the length of the low-level pulse is shorter than the length of the high-level pulse.

The high-level pulse of the first start signal Vst1 applied to the n-th gate signal generating circuit SGD(n) overlaps the high-level pulse and the low-level pulse of the first clock signal GCLK1 .

First, the first cycle (1) of the first clock signal GCLK1 that starts before the first start signal Vst1 is input to the n-th gate signal generating circuit SGD(n) will be described.

The Q node controller CQ is implemented with a first transistor T1 and a second transistor T2 . The first transistor T1 and the second transistor T2 are connected in series, and both are implemented as p-type transistors. The first transistor T1 is controlled by the first clock signal GCLK1 to provide the first start signal Vst1 to the second transistor T2 . In addition, the second transistor T2 is controlled by the low voltage VGL to provide the first start signal Vst1 received from the first transistor T1 to the Q node. The second transistor T2 is always turned on by the low voltage VGL. The second transistor T2 is connected between the Q node and the first transistor T1 to serve as a buffer for the Q node voltage. The first period 1 of the first clock signal GCLK1 starts with the low level voltage of the first clock signal GCLK1 , and the first start signal Vst1 also has a low level voltage. Accordingly, the Q node controller CQ provides a low level voltage to the Q node.

In the low-level pulse period of the first clock signal GCLK1 , the first start signal Vst1 provided to the Q node is a low-level voltage, and the low-level voltage is provided to the pull-down unit PD. The pull-down unit PD is implemented with the seventh transistor T7 and the first capacitor Cq1. The seventh transistor T7 is implemented as a p-type transistor. The seventh transistor T7 is controlled by the Q node to output the low voltage VGL. The first capacitor Cq1 is connected to the gate node of the seventh transistor T7 and the output node VO to which the n-th output signal Vgout(n) is output. The first capacitor Cq1 bootstraps the voltage of the Q node in a lowering direction so that the n-th output signal Vgout(n) can maintain the low voltage VGL, and the n-th output signal Vgout(n) ), the Q node is maintained at a low level voltage after the low voltage VGL is output.

The Q node controls the QB node control unit (CQB). The QB node controller CQB is implemented with a third transistor T3 and a fourth transistor T4 . The third transistor T3 and the fourth transistor T4 are connected in series through a QB node, and both are controlled by the Q node. Since the third transistor T3 is implemented as an n-type transistor and the fourth transistor T4 is implemented as a p-type transistor, the third transistor T3 and the fourth transistor T4 are turned on or turned on in the same period. The -off state is opposite to each other. Accordingly, the third transistor T3 is turned off by the low level voltage of the Q node, and the fourth transistor T4 is turned on by the low level voltage of the Q node. The high voltage VGH is provided to the QB node by the turned-on fourth transistor T4 . Since circuit connection is simplified by implementing the third transistor T3 as an n-type transistor, the width W of the gate driving circuit GD may be reduced. In addition, by implementing the active layer of the n-type transistor as an oxide, the threshold voltage margin of the third transistor T3 may be secured and the voltage provided to the third transistor T3 may be normally transmitted.

The high voltage VGH provided to the QB node during the low-level pulse period of the first clock signal GCLK1 is provided to the pull-up unit PU. The pull-up unit PU is implemented with the eighth transistor T8. And, the eighth transistor T8 is implemented as a p-type transistor. The eighth transistor T8 is turned off by being controlled by the QB node.

Subsequently, during the first period (1) of the first clock signal GCLK1, the first clock signal GCLK1 is converted from a low level voltage to a high level voltage, and the first start signal Vst1 also has a low level voltage converted to a high level voltage. The first clock signal GCLK1 of the high level voltage turns off the first transistor T1.

A second transistor T2 is connected between the first transistor T1 and the Q node, and the first transistor T1 is turned off so that the Q node floats but does not significantly shake. In addition, the Q node and the nth output signal Vgout(n) are maintained at the low voltage VGL by the first capacitor Cq1.

Accordingly, during the first period 1 of the first clock signal GCLK1 , the output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) is the low voltage VGL.

Second, the second period (2) of the first clock signal GCLK1 will be described. The second period 2 of the first clock signal GCLK1 starts with a low-level voltage, and the first start signal Vst1 has a high-level voltage.

The first transistor T1 is controlled by the first clock signal GCLK1 to provide the first start signal Vst1 to the second transistor T2 . In addition, the second transistor T2 is controlled by the low voltage VGL to provide the first start signal Vst1 received from the first transistor T1 to the Q node. That is, the Q node controller CQ provides a high level voltage to the Q node.

In the low-level pulse period of the first clock signal GCLK1 , the first start signal Vst1 provided to the Q node is a high-level voltage, and the high-level voltage is provided to the pull-down unit PD. Accordingly, the seventh transistor T7 is turned off by being controlled by the Q node.

And, since the Q node controls the QB node controller CQB, the third transistor T3 is turned on by the high-level voltage of the Q node, and the fourth transistor T4 has the high-level voltage of the Q node. turned off by The turned-on third transistor T3 provides the low voltage VGL to the QB node.

The low voltage VGL provided to the QB node during the low level pulse period of the first clock signal GCLK1 is provided to the pull-up unit PU. The eighth transistor T8 is turned on by the QB node to output the high voltage VGH to the output node VO.

Subsequently, during the second period (2) of the first clock signal GCLK1, the first clock signal GCLK1 is converted from a low level voltage to a high level voltage, and the first start signal Vst1 is changed from a high level voltage to a high level voltage. It is converted to a low level voltage. There is a slight difference between a time point at which the voltage of the low level of the first clock signal GCLK1 is converted to a voltage of a high level and a time point at which the voltage of the high level of the first start signal Vst1 is converted into a voltage of a low level. The first clock signal GCLK1 of the high level voltage turns off the first transistor T1. The Q node maintains a high level voltage, and the QB node maintains a low level voltage.

Accordingly, during the second period 2 of the first clock signal GCLK1 , the output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) is the high voltage VGH. The output signal Vgout(n) of the high voltage VGH is maintained for 4 horizontal periods 4H, and is provided to the n-th pixel line to turn on the n-type transistor.

5 is a block diagram of a gate driving circuit GD according to a second exemplary embodiment of the present specification. Specifically, FIG. 5 illustrates a gate driving circuit GD and a pixel line PG to which a signal output from the gate driving circuit GD is applied according to an exemplary embodiment of the present specification.

In the second embodiment to be described below, descriptions of components overlapping those of the first embodiment described above may be omitted.

In FIG. 5 , similarly to FIG. 2 , the gate driving circuit GD displays only a driver that applies a scan signal. When the number of pixel lines included in the display area DA is p, the gate driving circuit GD according to the exemplary embodiment of the present specification generates the first gate signal generating circuit SGD(n) to the pth gate signal. circuit SGD(p). FIG. 2 shows only the nth gate signal generating circuits SGD(n) to (n+3)th gate signal generating circuits SGD(n+3) among them. In this case, p and n are natural numbers, and 1≤n≤p.

The gate driving circuit GD includes a first clock signal GCLK1 , a second clock signal GCLK2 , a low voltage VGL, a high voltage VGH, a third clock signal OCLK1 , and a fourth clock signal OCLK2 . , and wires to which the start signal Vst is applied. The n-th gate signal generating circuit SGD(n) provides the scan signal to the n-th pixel line PG(n) while shifting the start signal Vst in response to the first clock signal GCLK1 .

The start signal Vst is input to the first gate signal generating circuit SGD( 1 ), and the second gate generating circuit SGD( 2 ) to the p-th gate generating circuit SGD(p) generate previous gates, respectively. It operates by receiving the scan signal output from the circuit as the start signal. Specifically, the n-th output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) is input as a start signal of the (n+1)-th gate signal generating circuit SGD(n+1). and is input to the n-th pixel line PG(n).

The first clock signal GCLK1 and the second clock signal GCLK2 swing between a high level voltage and a low level voltage, respectively, and have the same period. However, the second clock signal GCLK2 and the first clock signal GCLK1 have different phases. Specifically, the second clock signal GCLK2 is a signal in which the phase of the first clock signal GCLK1 is shifted by 180 degrees.

In FIG. 5 , the first clock signal GCLK1 is input to the nth gate signal generating circuit SGD(n) and the (n+2)th gate signal generating circuit SGD(n+2), and the (n+)th gate signal generating circuit SGD(n+2) 1) The second clock signal GCLK2 is input to the gate signal generating circuit SGD(n+1) and the (n+3)th gate signal generating circuit SGD(n+3). That is, the first clock signal GCLK1 is input to the odd-numbered gate signal generating circuit included in the gate driving circuit GD according to the second exemplary embodiment of the present specification, and the second clock signal GCLK1 is input to the even-numbered gate signal generating circuit. GCLK2) is input. Although the first clock signal GCLK1 and the second clock signal GCLK2 are alternately connected to the plurality of gate signal generating circuits in sequence, the order is not limited thereto.

The third clock signal OCLK1 and the fourth clock signal OCLK2 swing between a high level voltage and a low level voltage, respectively, and have the same period. However, the third clock signal OCLK1 and the fourth clock signal OCLK2 have different phases. Specifically, the fourth clock signal OCLK2 is a signal in which the phase of the third clock signal OCLK1 is shifted by 180 degrees.

6 is a circuit diagram of a gate signal generating circuit according to a second embodiment of the present specification. 6 illustrates an n-th gate signal generating circuit SGD(n) constituting the gate driving circuit GD as an example.

Referring to FIG. 6 , the n-th gate signal generating circuit SGD(n) includes a pull-down unit PD, a pull-up unit PU, a Q node control unit CQ, a QB node control unit CQB, and a Q node holding unit. (KQ).

The pull-down unit PD outputs the n-th output signal Vgout(n) as a turn-off voltage in response to the voltage of the Q node, and the pull-up unit PU responds to the voltage of the QB node and outputs the n-th output signal ( Vgout(n)) is output as a turn-on voltage. The n-th output signal Vgout(n) determined by the pull-down unit PD and the pull-up unit PU is applied to the n-th pixel line PG(n).

The Q node controller CQ is a component for charging or discharging the Q node, and applies a turn-on voltage or a turn-off voltage to the Q node using the start signal Vst. A start signal Vst is input to the first gate signal generation circuit SGD1 , and a previous output signal is used as a start signal from the second gate signal generation circuit SGD2 . When n is a natural number equal to or greater than 2, the (n-1)th output signal Vgout of the nth gate signal generation circuit SGD(n) is the (n-1)th gate signal generation circuit SGD(n-1). (n-1)) can be used as a start signal.

The QB node controller CQB is a component for charging or discharging the QB node, and applies a turn-on voltage or a turn-off voltage to the QB node according to the Q node voltage applied by the Q node controller CQ.

The electroluminescent display device 100 according to the exemplary embodiment of the present specification may be driven while changing a frequency to reduce power consumption. For example, it may be driven at a low frequency of about 1 Hz in a section displaying a still image, picture, or text rather than playing a video. Although there is an advantage in that power consumption is reduced when driving at a low frequency, on the contrary, since a slight change in luminance may be perceived as flickering due to slow motion of the screen, the output signal of the gate driving circuit GD must be kept constant. The Q node holding unit KQ included in the gate signal generating circuit according to the second exemplary embodiment of the present specification turns on the pull-down unit PD when the output signal of the gate signal generating circuit is the low voltage VGL. It maintains the voltage to make it happen at the Q node.

The n-th gate signal generating circuit SGD(n) according to the second exemplary embodiment of the present specification includes both an n-type transistor and a p-type transistor. The n-th output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) is provided to a pixel driving circuit included in the n-th pixel line PG(n), in particular, a turn of the n-th transistor -On and turn-off can be controlled, but not limited thereto.

A specific circuit structure and operation of the n-th gate signal generating circuit SGD(n) will be described below.

7 is a waveform diagram of gate signals input to a gate signal generating circuit according to a second exemplary embodiment of the present specification.

6 and 7 , the start signal Vst is implemented as a high-level pulse of one horizontal period (1H). Each of the first clock signal GCLK1 and the second clock signal GCLK2 has a period of 2 horizontal periods 2H. Each of the first clock signal GCLK1 and the second clock signal GCLK2 has a low-level pulse corresponding to a period shorter than one horizontal period 1H and a high-level pulse corresponding to a period longer than one horizontal period 1H. . Accordingly, each of the first clock signal GCLK1 and the second clock signal GCLK2 has a low level pulse shorter than half a period and a high level pulse longer than half a period. For example, when a point in time when the low-level voltage of the start signal Vst is converted to the high-level voltage overlaps with the low-level pulse of the first clock signal GCLK1, an output signal may not be generated. To solve this problem, the length of the low level pulse of the first clock signal GCLK1 may be shorter than the length of the high level pulse. In the second clock signal GCLK2 , like the first clock signal GCLK1 , the length of the low-level pulse is shorter than the length of the high-level pulse.

The third clock signal OCLK1 and the fourth clock signal OCLK2 each have a period of 2 horizontal periods 2H. Each of the third clock signal OCLK1 and the fourth clock signal OCLK2 has a low-level pulse and a high-level pulse of one horizontal period (1H). Referring to FIG. 6 , the third clock signal OCLK1 and the fourth clock signal OCLK2 are connected to the output signal, unlike the first clock signal GCLK1 , and thus do not affect the generation of the output signal. Accordingly, the low-level pulses and the high-level pulses of the third clock signal OCLK1 and the fourth clock signal OCLK2 may have the same length.

The high-level pulse of the start signal Vst applied to the n-th gate signal generating circuit SGD(n) overlaps the low-level pulse of the first clock signal GCLK1 .

First, the first cycle (1) of the first clock signal GCLK1 that starts before the start signal Vst is input to the n-th gate signal generating circuit SGD(n) will be described.

The Q node controller CQ is implemented with a first transistor T1 and a second transistor T2 . The first transistor T1 and the second transistor T2 are connected in series, and both are implemented as p-type transistors. The first transistor T1 is controlled by the first clock signal GCLK1 to provide the start signal Vst to the second transistor T2 . In addition, the second transistor T2 is controlled by the low voltage VGL to provide the start signal Vst received from the first transistor T1 to the Q node. The second transistor T2 is always turned on by the low voltage VGL. The first period 1 of the first clock signal GCLK1 starts with the low level voltage of the first clock signal GCLK1 , and the start signal Vst also has a low level voltage. Accordingly, the Q node controller CQ provides a low level voltage to the Q node.

In the low-level pulse period of the first clock signal GCLK1 , the start signal Vst provided to the Q node is a low-level voltage, and the low-level voltage is provided to the pull-down unit PD. The pull-down unit PD is implemented as a seventh transistor T7. The seventh transistor T7 is implemented as a p-type transistor. The seventh transistor T7 is controlled by the Q node to output the low voltage VGL.

And, the Q node controls the QB node controller (CQB). The QB node controller CQB is implemented with a third transistor T3 and a fourth transistor T4 . The gate electrode of the third transistor T3 and the gate electrode of the fourth transistor T4 are both connected to the Q node. Since the third transistor T3 is implemented as an n-type transistor and the fourth transistor T4 is implemented as a p-type transistor, the third transistor T3 and the fourth transistor T4 are turned on or turned on in the same period. The -off state is opposite to each other. Accordingly, the third transistor T3 is turned off by the low level voltage of the Q node, and the fourth transistor T4 is turned on by the low level voltage of the Q node. The high voltage VGH is provided to the QB node by the turned-on fourth transistor T4 . Since circuit connection is simplified by implementing the third transistor T3 as an n-type transistor, the width W of the gate driving circuit GD may be reduced. In addition, by implementing the active layer of the n-type transistor as an oxide, the threshold voltage margin of the third transistor T3 may be secured and the voltage provided to the third transistor T3 may be normally transmitted.

The high voltage VGH provided to the QB node during the low-level pulse period of the first clock signal GCLK1 is provided to the pull-up unit PU. The pull-up unit PU is implemented with the eighth transistor T8 and the third capacitor Cqb. The eighth transistor T8 is implemented as a p-type transistor. The third capacitor Cqb is connected to the output node VO and the QB node, and is charged with the low voltage VGL of the output node VO and the high voltage VGH of the QB node. The eighth transistor T8 is turned off by being controlled by the QB node.

In addition, the Q node and the fourth clock signal OCLK2 control the Q node holding unit KQ. The Q node holding part KQ is implemented with a fifth transistor T5 , a sixth transistor T6 , and a second capacitor Cq2 . Both the fifth transistor T5 and the sixth transistor T6 are implemented as p-type transistors. The fifth transistor T5 is turned on by the low level voltage of the fourth clock signal OCLK2 , and the sixth transistor T6 is turned on by the low level voltage of the Q node to turn on the fourth clock signal A low level voltage of (OCLK2) is provided to node A. The second capacitor Cq2 is connected to the A node and the Q node, and is charged with a voltage provided to the A node and the Q node, respectively.

Subsequently, during the first period 1 of the first clock signal GCLK1 , the first clock signal GCLK1 is converted from a low level voltage to a high level voltage to turn off the first transistor T1 .

A second transistor T2 is connected between the first transistor T1 and the Q node, and the first transistor T1 is turned off so that the Q node floats, but the Q node is held by the Q node holding unit KQ. The voltage may be maintained at a low level voltage. The seventh transistor T7 maintains a turned-on state and the nth output signal Vgout(n) is maintained at the low voltage VGL.

Accordingly, the output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) maintains the low voltage VGL during the first period 1 of the first clock signal GCLK1 . When the electroluminescent display device 100 according to an embodiment of the present specification is driven at a low frequency, the voltage of the Q node is constantly maintained through the Q node holding unit KQ, so that the nth gate signal generating circuit can be stably driven. .

Second, the second period (2) of the first clock signal GCLK1 will be described. The second period 2 of the first clock signal GCLK1 starts with a low-level voltage, and the start signal Vst changes from a low-level voltage to a high level before the first period 1 of the first clock signal GCLK1 ends. It is a state in which it is converted to a high-level voltage and is a high-level voltage.

The first transistor T1 is controlled by the first clock signal GCLK1 to provide the start signal Vst to the second transistor T2 . In addition, the second transistor T2 is controlled by the low voltage VGL to provide the start signal Vst received from the first transistor T1 to the Q node. That is, the Q node controller CQ provides a high level voltage to the Q node.

In the low-level pulse period of the first clock signal GCLK1 , the start signal Vst provided to the Q node is a high-level voltage, and the high-level voltage is provided to the pull-down unit PD. Accordingly, the seventh transistor T7 is turned off by being controlled by the Q node.

And, since the Q node controls the QB node controller CQB, the third transistor T3 is turned on by the high level voltage of the Q node to provide the low voltage VGL to the B node, and the fourth transistor (T4) is turned off by the high level voltage of the Q node to cut off the high voltage VGH provided to the QB node.

In addition, the fifth transistor T5 is turned off by the high level voltage of the fourth clock signal OCLK2 to cut off the B node and the QB node, and the sixth transistor T6 also has the high level voltage of the Q node. turned off by

During the low-level pulse period of the first clock signal GCLK1, the QB node maintains the high voltage VGH by the third capacitor Cqb of the pull-up unit PU and turns off the turn-off state of the eighth transistor T8. keep it

Subsequently, during the second period 2 of the first clock signal GCLK1 , the first clock signal GCLK1 is converted from a low level voltage to a high level voltage, and the start signal Vst is changed from a high level voltage to a low level voltage. is converted to a voltage of The first clock signal GCLK1 of the high level voltage turns off the first transistor T1. However, the Q node maintains a high level voltage by the Q node holding unit KQ.

The third transistor T3 of the QB node controller CQB is turned on by the high-level voltage of the Q node to apply the low voltage VGL to the B node, and the fourth transistor T4 is the high-level voltage of the Q node. It is turned off by the level voltage.

The fifth transistor T5 of the Q node holding unit KQ is turned on by the low level voltage of the fourth clock signal OCLK2 to transfer the low voltage VGL of the B node to the QB node. The sixth transistor T6 is turned off by the high level voltage of the Q node. And, the voltage of the Q node is maintained by the second capacitor Cq2.

Meanwhile, the low voltage VGL transferred to the QB node controls the pull-up unit PU. Specifically, the eighth transistor T8 is turned on by the low voltage VGL of the QB node, and outputs the high level voltage of the third clock signal OCLK1 as the nth output signal Vgout(n). do. The nth output signal Vgout(n) maintains a high level voltage during one horizontal period 1H during which the third clock signal OCLK1 maintains a high level voltage.

In addition, before the second period 2 of the first clock signal GCLK1 ends, the third clock signal OCLK1 is converted from a high level voltage to a low level voltage, and the fourth clock signal OCLK2 is a low level voltage. voltage is converted to a high level voltage. In this case, although the fifth transistor T5 is turned off by the fourth clock signal OCLK2, the voltage of the Q node is not affected. And, the low level voltage of the third clock signal OCLK1 is transferred to the output node VO through the turned-on eighth transistor T8, and the voltage change at the output node VO is applied to the third capacitor Cqb. affects the QB node due to the coupling effect of The QB node decreases the voltage by the difference between the high level and the low level voltage of the third clock signal OCLK1 while simultaneously reducing the falling time of the output node VO voltage.

Accordingly, during the second period 2 of the first clock signal GCLK1 , the n-th output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) is high corresponding to one horizontal period 1H. Output the voltage (VGH). In this case, the n-th gate signal generating circuit SGD(n) reduces the polling time of the n-th output signal Vgou(n) by disposing the third capacitor Cqb in the pull-up unit PU, and Reliability can be improved.

8 is a circuit diagram of a gate signal generating circuit according to a third embodiment of the present specification. 8 illustrates an n-th gate signal generating circuit SGD(n) constituting the gate driving circuit GD as an example.

In the third embodiment to be described below, descriptions of components overlapping with those of the first embodiment described above may be omitted. Also, the third embodiment may be applied to a block diagram of the gate driving circuit GD of FIG. 2 .

Referring to FIG. 8 , the n-th gate signal generating circuit SGD(n) includes a pull-down unit PD, a pull-up unit PU, a Q node control unit CQ, and a QB node control unit CQB.

The pull-down unit PD outputs the n-th output signal Vgout(n) as a turn-off voltage in response to the voltage of the Q node, and the pull-up unit PU responds to the voltage of the QB node and outputs the n-th output signal ( Vgout(n)) is output as a turn-on voltage. The pull-down unit PD and the pull-up unit PU are connected in series and share the output node VO. The n-th output signal Vgout(n) determined by the pull-down unit PD and the pull-up unit PU is applied to the n-th pixel line PG(n).

The Q node controller CQ is a component for charging or discharging the Q node, and applies a turn-on voltage or a turn-off voltage to the Q node using the start signal Vst. When n is a natural number equal to or greater than 3, the (n-2)th output signal Vgout(n-2) of the (n-2)th gate signal generation circuit SGD(n-2) can be used as a start signal.

The QB node controller CQB is a component for charging or discharging the QB node, and applies a turn-on voltage or a turn-off voltage to the QB node according to the Q node voltage applied by the Q node controller CQ.

The n-th gate signal generation circuit SGD(n) according to the exemplary embodiment of the present specification includes both an n-type transistor and a p-type transistor. The n-th output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) is provided to a pixel driving circuit included in the n-th pixel line PG(n). In particular, when the pixel driving circuit is implemented with an n-type transistor and a p-type transistor, the n-th output signal Vgout(n) may control turn-on and turn-off of the n-type transistor, but is not limited thereto. .

A specific circuit structure and operation of the n-th gate signal generating circuit SGD(n) according to the third embodiment of the present specification will be described below.

9 is a waveform diagram of gate signals input to a gate signal generating circuit according to a third embodiment of the present specification.

8 and 9 , the start signal Vst has a high-level pulse of 2 horizontal periods 2H, and the first clock signal GCLK1 has a period of 2 horizontal periods 2H. The first clock signal GCLK1 has a high-level pulse corresponding to a period shorter than one horizontal period 1H and a low-level pulse corresponding to a period longer than one horizontal period 1H. For example, when a point in time when the low-level voltage of the start signal Vst is converted to the high-level voltage overlaps with the high-level pulse of the first clock signal GCLK1, an output signal may not be generated. To solve this problem, the length of the high level pulse of the first clock signal GCLK1 may be shorter than the length of the low level pulse.

The high-level pulse of the start signal Vst applied to the n-th gate signal generating circuit SGD(n) overlaps the high-level pulse and the low-level pulse of the first clock signal GCLK1 .

First, the first cycle (1) of the first clock signal GCLK1 that starts before the start signal Vst is input to the n-th gate signal generating circuit SGD(n) will be described.

The Q node controller CQ is implemented with a first transistor T1 and a second transistor T2 . The first transistor T1 and the second transistor T2 are connected in series, the first transistor T1 is implemented as an n-type transistor, and the second transistor T2 is implemented as a p-type transistor. The first transistor T1 may be controlled by the first clock signal GCLK1 to provide the start signal Vst to the second transistor T2 . In addition, the second transistor T2 is controlled by the low voltage VGL to provide the start signal Vst received from the first transistor T1 to the Q node. The second transistor T2 is always turned on by the low voltage VGL. The second transistor T2 is connected between the Q node and the first transistor T1 to serve as a buffer for the Q node voltage.

The first period 1 of the first clock signal GCLK1 starts with the low level voltage of the first clock signal GCLK1 , and the start signal Vst also has a low level voltage. Subsequently, while the first clock signal GCLK1 is a low-level voltage, the start signal Vst is converted to a high-level voltage. While the first clock signal GCLK1 is a low-level voltage, the first transistor T1 is in a turned-off state.

During the first period 1 of the first clock signal GCLK1 , when the first clock signal GCLK1 has a high level voltage, the start signal Vst also maintains a high level voltage.

Since the first transistor T1 is turned on by the high-level pulse of the first clock signal GCLK1 , the Q node controller CQ provides the high level voltage of the start signal Vst to the Q node.

In the high-level pulse period of the first clock signal GCLK1 , the start signal Vst provided to the Q node is a high-level voltage, and the high-level voltage is provided to the pull-down unit PD. The pull-down unit PD is implemented with the seventh transistor T7 and the first capacitor Cq1 connected to the line to which the low voltage VGL is provided. Since the seventh transistor T7 is implemented as a p-type transistor, the seventh transistor T7 is turned off by the high-level voltage of the Q node.

The Q node controls the QB node control unit (CQB). The QB node controller CQB is implemented with a third transistor T3 and a fourth transistor T4 . The third transistor T3 and the fourth transistor T4 are connected in series through a QB node, and both are implemented as n-type transistors. The gate electrode of the third transistor T3 is connected to the Q node, the first electrode is connected to the wiring to which the low voltage VGL is provided, and the second electrode is connected to the QB node. The gate electrode and the first electrode of the fourth transistor T4 are connected to a wiring to which the high voltage VGH is provided, thereby making diode contact, and the second electrode is connected to the QB node. Accordingly, the third transistor T3 is controlled by the Q node, and the fourth transistor T4 is controlled by the high voltage VGH. The fourth transistor T4 basically maintains the state of the QB node at the high voltage VGH by always maintaining the turned-on state by the high voltage VGH. In this case, the third transistor T3 is turned on by the high level voltage of the Q node to provide the low voltage VGL to the QB node.

The low voltage VGL provided to the QB node during the high-level pulse period of the first clock signal GCLK1 is provided to the pull-up unit PU. The pull-up unit PU is implemented as an eighth transistor T8 connected to a line to which the high voltage VGH is provided. And, the eighth transistor T8 is implemented as a p-type transistor. The eighth transistor T8 is turned on by the low voltage VGL provided to the QB node to provide the high voltage VGH as the nth output signal Vgout(n). Accordingly, during the first period (1) of the first clock signal GCLK1, the first clock signal GCLK1 is the output signal Vgout(n) of the n-th gate signal generation circuit SGD(n) during the low-level pulse period. is the low voltage VGL, and the output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) is the high voltage VGH during the high-level pulse period of the first clock signal GCLK1 .

Second, the second period (2) of the first clock signal GCLK1 will be described. The second period 2 of the first clock signal GCLK1 starts with a low-level voltage, and the start signal Vst starts with a high-level voltage. The start signal Vst is converted from a high level voltage to a low level voltage while the first clock signal GCLK1 is a low level voltage.

In the low-level pulse period of the first clock signal GCLK1 , the first transistor T1 is turned off and the Q node maintains a high-level voltage. A second transistor T2 is connected between the first transistor T1 and the Q node, and the first transistor T1 is turned off so that the Q node is floated, but the voltage of the Q node is caused by the second transistor T2 does not vibrate much. The high level voltage maintains the seventh transistor T7 in a turned-off state.

And, since the Q node controls the QB node controller CQB, the third transistor T3 maintains a turn-on state by the high-level voltage of the Q node and provides the low voltage VGL to the QB node.

The low voltage VGL provided to the QB node during the low level pulse period of the first clock signal GCLK1 is provided to the pull-up unit PU. The eighth transistor T8 is turned on by the QB node to output the high voltage VGH to the output node VO. The output node VO is a node shared by serially connected to the pull-down unit PD and the pull-up unit PU, and is a node to which the output signal Vgout(n) is provided.

Subsequently, during the second period 2 of the first clock signal GCLK1 , the first clock signal GCLK1 is converted from a low level voltage to a high level voltage, and the start signal Vst is a low level voltage. The time when the first clock signal GCLK1 is converted from the low level voltage to the high level voltage is after the start signal Vst is converted from the high level voltage to the low level voltage.

The first clock signal GCLK1 of the high level voltage turns on the first transistor T1. The Q node controller CQ transfers the low-level voltage of the start signal Vst to the Q node. Since the Q node controls the pull-down unit PD, the seventh transistor T7 outputs the low voltage VGL by the Q node. The first capacitor Cq1 is implemented as a first electrode connected to the Q node and a second electrode connected to the output node VO from which the n-th output signal Vgout(n) is output. The first capacitor Cq1 bootstraps the voltage of the Q node in a lowering direction so that the n-th output signal Vgout(n) can maintain the low voltage VGL, and the n-th output signal Vgout(n) ), the Q node is maintained at a low level voltage after the low voltage VGL is output.

In addition, the third transistor T3 is turned off by the low level voltage of the Q node, and the QB node is converted to the high voltage VGH by the fourth transistor T4 .

Accordingly, during the second period 2 of the first clock signal GCLK1 , the output signal Vgout(n) of the n-th gate signal generating circuit SGD(n) maintains the high voltage VGH and the low voltage VGL ) is converted to The output signal Vgout(n) of the high voltage VGH is maintained for two horizontal periods 2H and is provided to the n-th pixel line to turn on the n-type transistor. However, the present invention is not limited thereto and may be connected to the p-type transistor to turn off the p-type transistor.

The n-th gate signal generating circuit SGD(n) includes a first transistor T1 , a third transistor T3 , and a fourth transistor T4 implemented as an n-type transistor, and the fourth transistor T4 . Since the circuit connection is simplified by making the diode contact, the width W of the gate driving circuit GD can be reduced. In addition, by implementing the active layer of the n-type transistor as an oxide, the leakage current of the first transistor T1 and the third transistor T3 is reduced and the threshold voltage margin is secured, so that the voltage provided to each transistor can be normally transmitted. .

The gate driving circuit and the electroluminescent display device 100 using the same according to the embodiment of the present specification may be described as follows.

In the gate driving circuit GD according to an embodiment of the present specification, the gate driving circuit GD is controlled by the Q node and includes a pull-down unit PD that transfers the low voltage VGL to the output node VO; The pull-up unit PU, which is controlled by the QB node and transfers the high level voltage of the third clock signal OCLK1 to the output node VO, is controlled by the first clock signal GCLK1 and generates the start signal Vst. The Q node controller CQ transmitted to the Q node, the QB node controller CQB controlled by the Q node to transfer a high voltage to the QB node, and the Q node and the fourth clock signal OCLK2 controlled by the Q node and a Q node holding part KQ including a second capacitor Cq2 connected to . In addition, the QB node controller CQB is connected including an n-type transistor and a p-type transistor connected to the Q node. Accordingly, it is possible to provide a stable output even during low-frequency driving.

According to another feature of the present specification, the pull-down unit PD and the pull-up unit PU may be connected in series to the output node VO, and the pull-up unit PU includes a third capacitor Cqb, and the third The capacitor Cqb may be connected to the output node VO and the QB node.

According to another feature of the present specification, the start signal Vst may have a high level voltage with a period of one horizontal period (1H).

According to another feature of the present specification, the third clock signal OCLK1 and the fourth clock signal OCLK2 may have a phase difference of 180 degrees with a period of 2 horizontal periods 2H.

According to another feature of the present specification, the high-level voltage of the third clock signal OCLK1 transmitted to the output node VO through the pull-up unit PU may be synchronized with the third clock signal OCLK1.

According to another feature of the present specification, in the first clock signal GCLK1 , the length of the low level voltage may be shorter than the length of the high level voltage in two horizontal periods 2H.

According to another feature of the present specification, the Q node controller CQ may include a transistor connected to the low voltage VGL and always in a turned-on state, and the transistor may be connected to the Q node.

In the electroluminescent display device 100 according to the exemplary embodiment of the present specification, the electroluminescent display device 100 includes a display area DA including a plurality of pixel lines and a gate providing a gate signal to the plurality of pixel lines. The display panel 110 is divided into a non-display area NDA including the driving circuit GD. In addition, each of the plurality of pixel lines includes a plurality of pixels PX, each of the plurality of pixels PX includes a pixel driving circuit and a light emitting device EL, and the pixel driving circuit and the gate driving circuit GD are Each is implemented with a p-type transistor and an n-type transistor, and the gate driving circuit GD provides a gate signal to the n-type transistor of the pixel driving circuit. Accordingly, a stable output may be provided and a non-display area of the display panel may be reduced.

According to another feature of the present specification, the gate driving circuit GD includes a pull-down unit PD controlled by a Q node and a pull-up unit PU controlled by a QB node, and a pull-down unit PD and a pull-up unit (PU) may be connected in series to provide a low voltage VGL or a high voltage VGH as a gate signal to the n-ton transistor of the pixel driving circuit.

Also, the pull-down unit PD may be connected to a line provided with the low voltage VGL, and the pull-up unit PU may be connected to a line provided with the high voltage VGH. Also, the pull-down unit PD may include a first capacitor Cq1 including a first electrode connected to the Q node and a second electrode connected to a node shared by the pull-up unit PU and the pull-down unit PD. . In addition, the gate driving circuit GD includes a Q node controller CQ that is controlled by the first clock signal GCLK1 and the low voltage VGL to transfer the start signal Vst to the Q node, and the Q node controller (CQ) may include two transistors of different types. Also, the gate driving circuit GD includes a QB node controller CQB implemented with two transistors controlled by the Q node, and the two transistors may be n-type transistors.

According to another feature of the present specification, the QB node controller CQB is controlled by the Q node, and a transistor connected to a wiring to which the low voltage VGL is provided, and a wiring to which both the gate electrode and one electrode are provided with the high voltage VGH. It may include a transistor connected to the. Also, the two transistors can be connected in series with each other and share a QB node.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: electroluminescence display device
110: display panel
120: data driving circuit
130: controller

Claims (15)

a pull-down unit controlled by the Q node and transferring a low voltage to the output node;
a pull-up unit controlled by the QB node and configured to transmit a high-level voltage of a third clock signal to the output node;
a Q node control unit controlled by a first clock signal and transmitting a start signal to the Q node;
a QB node controller controlled by the Q node to transfer a high voltage to the QB node; and
a Q node holding unit controlled by the Q node and a fourth clock signal and including a second capacitor connected to the Q node;
The QB node control unit includes an n-type transistor and a p-type transistor connected to the Q node, the gate driving circuit. According to claim 1,
The pull-down unit and the pull-up unit are connected in series to the output node,
The pull-up unit includes a third capacitor,
and the third capacitor is coupled to the output node and the QB node. According to claim 1,
and the start signal has a high level voltage with a period of one horizontal period. According to claim 1,
and the third clock signal and the fourth clock signal have a phase difference of 180 degrees with a period of 2 horizontal periods. According to claim 1,
The high level voltage of the third clock signal transmitted to the output node through the pull-up unit is synchronized with the third clock signal. According to claim 1,
and the length of the low level voltage is shorter than the length of the high level voltage in the first clock signal with a period of 2 horizontal periods. According to claim 1,
wherein the Q node controller includes a transistor connected to a low voltage to be always in a turned-on state, wherein the transistor is connected to the Q node. a display area including a plurality of pixel lines; and
a display panel divided into a non-display area including a gate driving circuit providing a gate signal to the plurality of pixel lines;
Each of the plurality of pixel lines includes a plurality of pixels,
Each of the plurality of pixels includes a pixel driving circuit and a light emitting device,
The pixel driving circuit and the gate driving circuit are implemented with a p-type transistor and an n-type transistor, respectively,
and the gate driving circuit provides a gate signal to the n-type transistor of the pixel driving circuit. 9. The method of claim 8,
The gate driving circuit includes a pull-down unit controlled by a Q node and a pull-up unit controlled by a QB node,
The pull-down unit and the pull-up unit are connected in series to provide a low voltage or a high voltage to the n-type transistor of the pixel driving circuit as a gate signal. 10. The method of claim 9,
The pull-down unit is connected to a line to which a low voltage is provided, and the pull-up unit is connected to a line to which a high voltage is provided. 10. The method of claim 9,
The pull-down unit includes a first capacitor including a first electrode connected to the Q node and a second electrode connected to a node shared by the pull-up unit and the pull-down unit. 10. The method of claim 9,
The gate driving circuit includes a Q node controller that is controlled by a first clock signal and a low voltage to transmit a start signal to the Q node, wherein the Q node controller includes two transistors of different types. display device. 10. The method of claim 9,
The gate driving circuit includes a QB node controller controlled by the Q node, and the QB node controller includes two n-type transistors. 14. The method of claim 13,
The two transistors are
a transistor controlled by the Q node and connected to a wiring to which a low voltage is provided; and
An electroluminescent display device comprising a transistor in which both a gate electrode and one electrode are connected to a wiring to which a high voltage is provided. 14. The method of claim 13,
and the two transistors are connected in series with each other and share the QB node.

Images