KR20210052145A - Silicon backside protection device and operation method thereof - Google Patents

Abstract

According to an embodiment of the present invention, a silicon backside protection device comprises: a clock generating unit configured to generate a detection clock by using a capacitance change of a plurality of capacitor patterns disposed on a silicon substrate; a counter unit for counting the detection clock and outputting detection count information; and an attack response unit configured to perform a preset security operation on a semiconductor chip based on a difference between the detection count information and reference count information. Therefore, the silicon backside protection device can determine whether a rear surface of the semiconductor chip is attacked based on the capacitance change of the capacitor patterns disposed on a silicon protection substrate.

Description

Silicon backside protection device and its operation method {SILICON BACKSIDE PROTECTION DEVICE AND OPERATION METHOD THEREOF}

The present application relates to a silicon back surface protection device and an operation method thereof, and in particular, to a silicon back surface protection device capable of protecting a back surface attack on a semiconductor chip and minimizing the size of the protection device, and an operation method thereof.

Recently, a potential attacker is information obtained by performing an analysis of a semiconductor chip, so-called reverse engineering, and can change an operation mode of a circuit or manipulate data in the memory. Such attack behavior can have undesirable consequences, especially in security-related circuits with cash card functions or access authorization functions.

In particular, the potential attacker uses a FIB (Focused Ion Beam) method, a probing method, and a forcing method to prevent a relatively weak back side attack of a silicon substrate rather than an attack on the surface of the silicon substrate. I'm taking it. This is because security-related block engines such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA are located on the low metal layer of the silicon substrate.

However, it is very difficult to design a protective layer on the rear surface of the semiconductor chip because the rear surface of the semiconductor chip is cut off during the semiconductor process. Also. Since designing a new protective layer on the back side of the semiconductor chip can increase the overall production cost, the manufacturer is burdened with a cost for the implementation of an additional silicon layer, and there is a problem that the overall chip size is increased.

An object of the present application is to provide a silicon backside protection device capable of determining whether a backside attack on a semiconductor chip is based on a change in capacitance of a capacitor pattern disposed on a substrate protection layer, and a method of operating the same.

The silicon back surface protection device according to the exemplary embodiment of the present application includes a clock generator that generates a sense clock using a change in capacitance of a plurality of capacitor patterns disposed on a silicon substrate, and calculates the sense clock to obtain sense count information. And an attack counter to perform a predetermined security operation on the semiconductor chip based on a difference between the output counter unit and the detection count information and the reference count information.

In an embodiment, each of the plurality of capacitor patterns includes first and second metal patterns spaced apart from each other by a predetermined distance, and an insulator disposed between the first and second metal patterns and formed in a zigzag shape.

In an exemplary embodiment, each of the first and second metal patterns includes a horizontal electrode extending in a length direction and a vertical electrode extending in a width direction every predetermined distance from the horizontal electrode.

In an embodiment, in the first and second metal patterns, vertical electrodes are disposed to be staggered and disposed in parallel in the length direction.

In an embodiment, the plurality of capacitor patterns are disposed on a passive shield layer and one passivation layer adjacent to the dummy shield layer from among the multi-stage passivation layers attached to the silicon substrate, and the one passivation layer is logic It is divided into a first area that is not used for and a second area that is used for logic.

In an embodiment, the plurality of capacitor patterns are disposed in a ratio of 100% to the total area of the first area and the area of the passive shield layer.

In an embodiment, the plurality of capacitor patterns are disposed in the second area at a ratio of 50% of the total area.

In an embodiment, the clock generator includes at least two detection sensors to generate the detection clock in units of a predetermined number of capacitor patterns.

In an embodiment, each of the at least two detection sensors includes a detection resistor, a detection transistor having one side connected to the detection resistor, a gate side connected to an output node, and an input node located between the detection resistor and the detection transistor. It contains one capacitor pattern.

In an embodiment, the clock generator receives a driving voltage through an input node of one of the at least two detection sensors, and outputs the detection clock to the counter through an output node of another detection sensor. .

In an embodiment, the clock generator further includes a plurality of detection sensors connected in series between the one detection sensor and the other detection sensor.

In an embodiment, it further comprises a reference clock generator for generating a reference clock corresponding to the sense clock based on the driving voltage.

In an embodiment, a predetermined security operation is performed based on a determination module for comparing the detection count information and the reference count information and outputting an alarm signal based on a difference between the first and reference count information, and the alarm signal. It includes a processing module to perform.

A silicon back surface protection device according to another exemplary embodiment of the present application includes a plurality of layers disposed on at least one of a silicon substrate on which a plurality of semiconductor chips are mounted, a plurality of protective layers attached to the surface of the silicon substrate, and the plurality of protective layers. And a protection circuit unit configured to determine whether a rear surface of the semiconductor chip is attacked based on the capacitor patterns of and the capacitance change of the plurality of capacitor patterns.

In an embodiment, the at least one includes a passive shield layer and one passivation layer adjacent to a lower side of the dummy shield layer among the multi-stage passivation layers, and the one passivation layer includes a first region not used for logic and It is divided into a second area used for logic.

In an embodiment, the plurality of capacitor patterns are disposed in a ratio of 100% of the total area to the first area and the area of the passive shield layer.

In an embodiment, the plurality of capacitor patterns are disposed in the second area at a ratio of 50% of the total area.

In an embodiment, the protection circuit unit generates the sense clock in units of a preset number of capacitor patterns.

In the operating method of the silicon back surface protection device according to the exemplary embodiment of the present application, the clock generation unit generates a sense clock by using at least two first capacitor patterns among a plurality of capacitor patterns disposed on a silicon substrate, and a reference clock Generating a reference clock by using a second at least two capacitor patterns corresponding to the first at least two capacitor patterns, by a counter unit counting the detection clock and the reference clock to detect detection count information and reference count information And outputting, to an attack counterpart, and performing a predetermined security operation on the semiconductor chip based on a difference between the detection count information and the reference count information by the attack counterpart.

In an embodiment, the plurality of capacitor patterns are disposed on a passive shield layer and one passivation layer adjacent to the dummy shield layer from among the multi-stage protective layers attached to the silicon substrate.

The silicon back surface protection device and its operation method of the present application determine whether a back side attack on a semiconductor chip is made based on a change in capacitance of a capacitor pattern disposed on the substrate protection layer, and the size of the silicon back surface protection device can be minimized. have.

1 is a block diagram of a silicon back surface protection device according to an embodiment of the present application.
2 is an example of a capacitor pattern of FIG. 1.
FIG. 3 is a diagram illustrating a protective layer on which the capacitor pattern of FIG. 2 is disposed.
4 is a circuit diagram illustrating a clock generator of FIG. 1.
5 is a diagram illustrating the detection sensor of FIG. 4.
6 is a diagram specifically illustrating an operation of the silicon back surface protection device of FIG. 1.
7 is a plan view illustrating a silicon substrate from which the protective layer of FIG. 3 has been removed.
8 is a diagram illustrating a plan view of a silicon substrate at the third passivation layer level of FIG. 3.
9 is a view in which a plurality of capacitor patterns are disposed on the silicon substrate of the plan view of FIG. 8.
10 is an operation process of the silicon back surface protection device of FIG. 1.

Hereinafter, embodiments of the present application will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present application may be modified into various other forms, and the scope of the present application is not limited to the embodiments described below. In addition, embodiments of the present application are provided to more completely explain the present invention to a person skilled in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

In the drawings, parts not related to the description are omitted in order to clearly describe the present application, and the thickness is enlarged to clearly express several layers and regions, and components having the same function within the scope of the same idea are the same reference. Describe using symbols. Furthermore, throughout the specification, when a part "includes" a certain component, it means that other components may be further included rather than excluding other components unless otherwise stated.

1 is a block diagram of a silicon back surface protection device 10 according to an embodiment, FIG. 2 is an example showing a capacitor pattern 110_1 of FIG. 1, and FIG. 3 is a capacitor pattern 110_1 of FIG. ) Is a diagram for explaining the protective layer 40 is disposed.

Referring to FIG. 1, the silicon back surface protection device 10 may include a clock generator 100, a counter 200, and an attack counter 300.

_{First, the clock generator 100 may generate a sense clock CK S} using a plurality of capacitor patterns 110_1 to 110_N disposed on a silicon substrate.

Here, each of the plurality of capacitor patterns 110_1 to 110_N may include first and second metal patterns 111_1 and 112_1 and an insulator 113_1.

As shown in FIG. 2, the first and second metal patterns 111_1 and 112_1 are formed to be spaced apart from each other by a predetermined distance D, and the insulator 113_1 is the first and second metal patterns 111_1 and 112_1. It may be formed to have a certain width (D) between.

In addition, the first and second metal patterns 111_1 and 112_1 may include horizontal electrodes extending in the length (L) direction and a plurality of vertical electrodes extending in the width (W) direction for each predetermined distance between the horizontal electrodes. Each of the vertical electrodes of the first and second metal patterns 111_1 and 112_1 may be disposed to be alternately disposed and may be disposed parallel to each other in the length L direction. Accordingly, the insulator 113_1 may be formed in a zigzag shape.

Depending on the embodiment, the plurality of capacitor patterns 110_1 to 110_N may be disposed on a protective layer attached to a silicon substrate on which a semiconductor chip is mounted.

As shown in FIG. 3, in a process in which semiconductor chips (eg, 30_1, 30_2) are mounted on the silicon substrate 20 and the protective layer 40 is attached to the surface of the silicon substrate 20, a plurality of capacitor patterns They 110_1 to 110_N may be disposed on the protective layer 40.

Specifically, the protective layer 40 protects the semiconductor chip (eg, 30_1, 30_2), and at the same time provides multiple protective layers (eg, 41 to 44) and a passive shield layer (eg, 45) used for operation or logic. Can include. Here, the multi-stage protective layers (eg, 41 to 44) and the passive shield layer (eg, 45) may be formed of metal.

For example, when the protective layer 40 includes first to fourth protective layers (eg, 41 to 44) and a passive shield layer (eg, 45), and the semiconductor chip (eg, 30_1) corresponds to an ASIC , The first to third protective layers 41 to 43 corresponding to the surface area of the silicon substrate 20 on which the semiconductor chip (eg, 30_1) is mounted are used for operation or logic, and the fourth protective layer 44 is a dummy As a shield layer, it can be used for protection purposes.

In addition, when the semiconductor chip (eg, 30_2) corresponds to the EEPROM, ROM, and RAM, the first and second protective layers 41 corresponding to the surface area of the silicon substrate 20 on which the semiconductor chip (eg, 30_2) is mounted. , 42) are used for operation or logic, and the passive shield layer 45 and the fourth protective layer 44 may be used for protection as dummy shield layers.

The plurality of capacitor patterns 110_1 to 110_N according to the embodiment are formed in the passive shield layer 45 and one protective layer (eg, 43) adjacent to the lower side of the dummy shield layer among the multi-stage protective layers 41 to 44. Can be placed. Here, the dummy shield layer may be a metal layer used only for protection purposes.

For example, when the dummy shield layer is the fourth passivation layer 44, one passivation layer (eg, 43) may be the third passivation layer 43. The third passivation layer 43 may be divided into a first area not used for logic and a second area used for logic.

Here, a plurality of capacitor patterns 110_1 to 110_N may be disposed in the first area of the third passivation layer 43 and the area of the passive shield layer 45 at a ratio of 100% to the total area of each area. In addition, in the second region of the third passivation layer 43, a plurality of capacitor patterns 110_1 to 110_N may be disposed at a ratio of 50% to the entire area.

Next, the counter unit 200 may output the detection count information D _{COUNT1 by counting the detection clock CK S} output from the clock generation unit 100. Here, the count information D _COUNT1 may be a signal corresponding to the detection clock CK _S.

_{In addition, when the counter unit 200 outputs the detection clock CK S} from the clock generation unit 100, the counter unit 200 _{receives the reference clock CK R} from the reference clock generation unit (not shown), and the reference clock CK _R ) May be counted to output the reference count information (D _{COUNT2) to the attack response unit 300.}

Here, the reference clock generation unit (not shown) is a replication circuit for the clock generation unit 100, and is included in the clock generation unit 100 or configured as a separate device, and is a reference clock corresponding to the _{detection clock CK S} (CK _R ) may be provided to the counter unit 200.

Next, the attack response unit 300 may perform a predetermined security operation on the semiconductor chip based on a difference between the _{detection count information D COUNT1} and the reference count information D _COUNT2. Here, the preset security operation is an operation for protecting against a back attack on the semiconductor chip, and may be an operation for stopping each operation on the semiconductor chip.

Specifically, the attack response unit 300 may compare the _{detection count information D COUNT1} output through the counter unit 200 and the reference count information D _COUNT2. Then, the attack response unit 300 may perform a preset security operation based on a difference between the _{detection count information D COUNT1} and the reference count information D _COUNT2.

The silicon back surface protection device 10 according to the embodiment of the present application may generate a sense clock CK _S using a plurality of capacitor patterns 110_1 to 110_N disposed on the passivation layer 40. In addition, the silicon back surface protection device 10 may output the detection count information D _COUNT1 and the reference count information D _{COUNT2 by counting the detection clock CK S} and the reference clock CK _R. At this time, since the silicon back surface protection device 10 can perform a predetermined security operation on the semiconductor chip based on the difference between the _{detection count information D COUNT1} and the reference count information D _COUNT2, While protecting against attack, it is possible to minimize the size and manufacturing cost of the silicon substrate.

FIG. 4 is a circuit diagram illustrating the clock generation unit 100 of FIG. 1, and FIG. 5 is a diagram illustrating a detection sensor (eg, 150_1) of FIG. 4.

Referring to FIG. 4, the clock generator 100 may include at least two detection sensors (eg, 150_1 to 150_5) to generate the _{detection clock CK S in units of the number of preset capacitor patterns.}

Specifically, each of the at least two sensing sensors (eg, 150_1 to 150_5) may include one sensing resistor R _S , one sensing transistor TR _S , and one capacitor pattern (eg, 110_1).

As illustrated in FIG. 5, one side of the _{sensing transistor TR S} may be connected to the sensing resistor R _S and a gate side may be connected to the _{output node N OUT.} In addition, one capacitor pattern (eg, 110_1) may be connected to an input node N _{IN located between the sensing transistor TR S} and the sensing resistor R _S. That is, the sensing resistor (R _S ) is the input node (N _IN ) and the sensing transistor (TR _S ) are connected in parallel, and the sensing transistor (TR _S ) is the sensing resistor (R _S ) and the input node (N _IN ) in parallel. Can be connected to.

Referring to FIG. 4 again, the clock generation unit 100 applies a driving voltage V _{CC through an input node N IN} of the first detection sensor 150_1 among at least two detection sensors (eg, 150_1 to 150_5). Can be provided. In addition, the clock generation unit 100 receives the detection clock CK _{S through the output node N OUT} of the fifth detection sensor 150_5 among at least two detection sensors (eg, 150_1 to 150_5). Can be printed as

At this time, in order to secure coverage against a rear attack, the clock generator 100 includes the second to fourth detection sensors 150_2 to 150_4 connected in series between the first and fifth detection sensors 150_1 and 150_5. Can be located in

For example, the second detection sensor 150_2 may be connected to _{the output node N OUT} of the first detection sensor 150_1 through the _{input node N IN.} In addition, the third detection sensor 150_3 may be connected to _{the output node N OUT} of the second detection sensor 150_1 through the _{input node N IN.} In addition, the fourth detection sensor 150_4 may be connected to _{the output node N OUT} of the third detection sensor 150_1 through the _{input node N IN.} In addition, the fifth detection sensor 150_5 may be connected to _{the output node N OUT} of the fourth detection sensor 150_1 through the _{input node N IN.}

That is, each of the first to fourth detection sensors 150_1 to 150_4 has an output node N _OUT connected to an input node N _IN of another detection sensor, and the second to fifth detection sensors 150_2 to 150_5 ) Each of the input nodes N _IN may be connected to an output node N _{OUT of another sensor.}

Hereinafter, with reference to FIG. 6, the counter unit 200 and the attack response unit 300 will be described in more detail.

6 is a diagram specifically illustrating an operation of the silicon back surface protection device 10_2 of FIG. 1.

1 to 6, the silicon back surface protection device 10_2 may include a clock generation unit 100, a reference clock generation unit 101, a counter unit 200, and an attack response unit 300. Hereinafter, redundant descriptions of the clock generation unit 100, the counter unit 200, and the attack response unit 300 having the same reference numbers described in FIGS. 1 to 5 will be omitted.

First, the counter unit 200 may include a detection clock counter 210 and a reference clock counter 220.

The detection clock counter 210 may count the detection clock CK _S generated by the clock generation unit 100 and output to the attack response unit 300.

Next, the reference clock counter 220 may count the reference clock CK _R generated from the reference clock generation unit 101 and output to the attack counter 300.

Here, the reference clock generation unit 101 includes second at least two capacitor patterns 110_1 corresponding to the first at least two or more capacitor patterns 110_1 to 110_5 preset through the clock generation unit 100 among the plurality of capacitor patterns. ~110_5) may be used to generate the _{reference clock CK R.} In this case, the number of the second at least two or more capacitor patterns 110_1 to 110_5 and the number of the first at least two or more capacitor patterns 110_1 to 110_5 may be the same. That is, the reference clock generation unit 101 may generate a reference clock CK _{R corresponding to the detection clock CK S.}

Next, the attack response unit 300 may include a determination module 310 and a processing module 320.

Specifically, the determination module 310 may compare _{detection count information D COUNT1 output through the detection clock counter 210 and reference count information D COUNT2} output through the reference clock counter 220.

Also, the determination module 310 may output an alarm signal based on a difference between the _{detection count information D COUNT1} and the reference count information D _COUNT2. Here, the warning signal may be a signal for identifying a rear attack on the semiconductor chip. For example, when _{the difference between the detection count information D COUNT1} and the reference count information D _COUNT2 is greater than or equal to a preset size, the determination module 310 may output an alarm signal to the processing module 320. In addition, when the detection count information D _COUNT1 and the reference count information D _COUNT2 are the same, the determination module 310 may not output an alarm signal.

That is, the determination module 310 may determine whether the semiconductor chip is attacked by the rear surface by outputting an alarm signal based on a difference between the _{detection count information D COUNT1} and the reference count information D _COUNT2.

According to an embodiment, the determination module 310 may adjust the level of the alarm signal based on a difference between the _{detection count information D COUNT1} and the reference count information D _COUNT2. Here, the alarm signal may include a plurality of voltage levels.

For example, when the difference between the detection count information (D _COUNT1 ) and the reference count information (D _COUNT2 ) is less than a preset size, the determination module 310 adjusts the level of the alarm signal to a low voltage level, and the low voltage level alarm signal May be output to the processing module 320. In addition, when the difference between the detection count information (D _COUNT1 ) and the reference count information (D _COUNT2 ) is greater than or equal to a preset size, the determination module 310 adjusts the level of the alarm signal to a high voltage level, and processes the alarm signal of the high voltage level. It can be output to the module 320.

Next, the processing module 320 may perform a preset security operation based on an alarm signal output through the determination module 310.

Depending on the embodiment, the processing module 320 may stop each operation of the semiconductor chip at once based on an alarm signal of a high voltage level. Also, the processing module 320 may selectively stop each operation of the semiconductor chip based on an alarm signal of a low voltage level.

In the present application, the clock generation unit 100 excluding the first at least two capacitor patterns (eg, 110_1 to 110_5), the reference clock generation unit 101 excluding the second at least two capacitor patterns (eg, 110_6 to 110_10) , The counter unit 200 and the attack response unit 300 may be referred to as a protection circuit unit. That is, the protection circuit unit is based on the change in capacitance of the capacitor pattern (eg, 110_1 to 110_5) through the clock generation unit 100, the reference clock generation unit 101, the counter unit 200, and the attack response unit 300. Thus, it is possible to determine whether the semiconductor chip is attacked on the back side.

7 is a plan view of the silicon substrate 20 from which the protective layer 40 of FIG. 3 has been removed, and FIG. 8 is a view of the silicon substrate 20 at the level of the third protective layer 43 of FIG. 3. FIG. 9 is a plan view, and FIG. 9 is a view in which a plurality of capacitor patterns 110_1 to 110_N are disposed on the silicon substrate 20 of FIG. 8.

3 and 7 to 9, a plurality of semiconductor chips may be mounted on the silicon substrate 20. Here, the plurality of semiconductor chips may include at least one of EEPROM, ASIC, RAM, and ROM.

The multi-stage protective layers 41 to 44 may be attached to the surface of the silicon substrate 20 to protect a plurality of semiconductor chips or to be used in a logic operation. For example, the multi-stage protective layers 41 to 44 may be attached to the entire surface of the silicon substrate 20 on which a plurality of semiconductor chips are mounted.

The capacitor pattern (eg, 110_1) according to the embodiment may be disposed on at least one of the multi-stage protective layers 41 to 44. Here, at least one may include a passive shield layer 45 and a third protective layer 43 located under the fourth protective layer 44 corresponding to the dummy shield layer among the multi-stage protective layers 41 to 44. have.

In this case, the third passivation layer 43 may be divided into a first area not used for logic and a second area used for logic.

As shown in FIG. 8, the first region is illustrated as being included as a region of the passive shield layer 45 for convenience of description.

According to an embodiment, a plurality of capacitor patterns 110_1 to 110_N may be disposed in a ratio of 100% to the total area of the first area of the third passivation layer 43 and the area of the passive shield layer 45. In this case, a plurality of capacitor patterns 110_1 to 110_N may be disposed in the second region of the third passivation layer 43 at a ratio of 50% of the total area.

10 is an operation process of the silicon back surface protection device 10 of FIG. 1.

Referring to FIGS. 1 to 10, first, in step S110, the clock generator 100 includes first at least two capacitor patterns (for example, among a plurality of capacitor patterns 110_1 to 110_N) disposed on the silicon substrate 20. , 110_1 to 110_5) may be used to generate the _{detection clock CK S.}

At this time, in step S120, the reference clock generation unit 101 uses the second at least two capacitor patterns (eg, 110_6 to 110_10) corresponding to the first at least two capacitor patterns (eg, 110_1 to 110_5), It is possible to generate a clock (CK _{R ).}

Then, in step S130, the counter unit 200 may output the detection count information D _COUNT1 and the reference count information D _{COUNT2 by counting the detection clock CK S} and the reference clock CK _R.

Thereafter, in step S140, the attack response unit 300 performs a predetermined security operation on the semiconductor chips 30_1 to 30_N based on the difference between the _{detection count information D COUNT1} and the reference count information D _COUNT2. I can.

Although the present application has been described with reference to the exemplary embodiment illustrated in the drawings, this is only exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other exemplary embodiments are possible therefrom. Therefore, the true technical protection scope of the present application should be determined by the technical idea of the attached registration claims.

10: silicone back protection device
100: clock generation unit
101: reference clock generation unit
200: counter unit
300: attack response unit

Claims (20)

A clock generator configured to generate a sense clock by using a change in capacitance of a plurality of capacitor patterns disposed on the silicon substrate;
A counter unit for counting the detection clock and outputting detection count information; And
A silicon backside protection device comprising an attack response unit configured to perform a predetermined security operation on a semiconductor chip mounted on the silicon substrate based on a difference between the detection count information and the reference count information. The method of claim 1,
The clock generator comprises at least two detection sensors to generate the detection clock in units of a predetermined number of capacitor patterns. The method of claim 2,
Each of the at least two detection sensors
Sensing resistance;
A sensing transistor having one side connected to the sensing resistor and a gate side connected to an output node; And
And a capacitor pattern connected to an input node positioned between the sense resistor and the sense transistor. The method of claim 2,
The clock generation unit receives a driving voltage through an input node of one of the at least two detection sensors and outputs the detection clock through an output node of another detection sensor. The method of claim 4,
The clock generator further comprises a plurality of detection sensors connected in series between the one detection sensor and the other detection sensor. The method of claim 4,
The silicon back surface protection device further comprising a reference clock generator configured to generate a reference clock corresponding to the sense clock based on the driving voltage. The method of claim 1,
Each of the plurality of capacitor patterns includes first and second metal patterns spaced apart from each other by a predetermined distance; And
Silicon back protection device comprising an insulator disposed between the first and second metal patterns. The method of claim 7,
Each of the first and second metal patterns may include horizontal electrodes extending in a length direction; And
Silicon back protection device comprising a vertical electrode extending in the width direction every predetermined distance from the horizontal electrode. The method of claim 8,
In the first and second metal patterns, the vertical electrodes are disposed to be staggered to each other and are disposed parallel to each other in a length direction. The method of claim 1,
The plurality of capacitor patterns are disposed on a passive shield layer and one passivation layer adjacent to the dummy shield layer downward among the multi-stage protective layers attached to the silicon substrate,
The one protective layer is divided into a first region not used for logic and a second region used for logic. The method of claim 10,
The first area and the area of the passive shield layer, the plurality of capacitor patterns are disposed in a ratio of a maximum of 100% of the total area, the silicon back surface protection device. The method of claim 10,
In the second area, the plurality of capacitor patterns are disposed at a maximum ratio of 50% over the entire area. The method of claim 1,
A determination module for comparing the detection count information and the reference count information, and outputting an alarm signal based on a result of the comparison; And
And a processing module that performs a preset security operation based on the alarm signal. A silicon substrate on which a plurality of semiconductor chips are mounted;
Multiple protective layers attached to the surface of the silicon substrate;
A plurality of capacitor patterns disposed on at least one of the multi-stage protective layers; And
A silicon rear surface protection device comprising a protection circuit unit configured to determine whether a rear surface is attacked on the semiconductor chip based on a change in capacitance of the plurality of capacitor patterns. The method of claim 14,
The at least one includes a passive shield layer and one protective layer adjacent to a lower side of the dummy shield layer among the multi-stage protective layers,
The one protective layer is divided into a first region not used for logic and a second region used for logic. The method of claim 15,
The silicon back surface protection device, wherein the plurality of capacitor patterns are disposed in a ratio of 100% to the total area of the first area and the area of the passive shield layer. The method of claim 15,
In the second area, the plurality of capacitor patterns are disposed at a ratio of 50% with respect to the total area. The method of claim 14,
The protection circuit unit generates a detection clock in units of a predetermined number of capacitor patterns. As a method of operation of the silicon back protection device,
Generating a sense clock by using the first at least two capacitor patterns among a plurality of capacitor patterns arranged on the silicon substrate by a clock generator;
Generating, by a reference clock generation unit, a reference clock using second at least two capacitor patterns corresponding to the first at least two capacitor patterns;
Counting the detection clock and the reference clock by a counter unit and outputting detection count information and reference count information to an attack counterpart; And
And performing a predetermined security operation on the semiconductor chip mounted on the silicon substrate based on the difference between the detection count information and the reference count information by the attack counterpart. The method of claim 19,
The plurality of capacitor patterns are disposed on one passivation layer and a passive shield layer adjacent to the dummy shield layer from among the multi-stage passivation layers attached to the silicon substrate.

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