KR20200061330A - Magnetic Random Access Memory(MRAM) having increased On/Off ratio and methods of manufacturing and operating the same - Google Patents

Abstract

Disclosed is a magnetic memory device having an increased on/off ratio and a method of manufacturing and operating the same. The magnetic memory device according to an embodiment includes a switching element and a storage node connected thereto, and the storage node includes a magnetic node in which two opposite bits are simultaneously written, and wherein one of the two bits is written The stacking order of the layers constituting a part of the magnetic node and the stacking order of the layers constituting the rest of the magnetic node in which the other of the two bits are recorded are the same. The source of the switching element can be shared with neighboring switching elements. The storage nodes are sequentially stacked vertically, and may include two MTJs that are independent of each other. Two bit lines are connected to the storage node, and the storage node may be provided between the two bit lines or below the two bit lines.

Description

Magnetic random access memory (MRAM) having increased on/off ratio and methods of manufacturing and operating the same}

The present disclosure relates to a memory device and its manufacturing and operation, and more particularly, to a magnetic memory device having an increased on/off ratio and a method of manufacturing and operating the same.

The magnetic random access memory (MRAM) reads data recorded in the MTJ by measuring the resistance difference according to the magnetization state of the free layer and the pinned layer of the MTJ. The magnetization direction of the pinned layer is fixed, and the magnetization direction of the free layer may be changed when a magnetic field of a certain intensity or more is applied or according to the spin state of the current flowing through the MTJ. When the magnetization directions of the free layer and the pinned layer are the same, the measured resistance is called an on resistance, and when the magnetization directions of the free layer and the pinned layer are opposite, the measured resistance is called an off resistance. The magnetic memory device can read data using a difference between an on-resistance and an off-resistance. Therefore, if the difference between the on-resistance and the off-resistance in the magnetic memory device is small, that is, if the on/off ratio is small, the sensing margin decreases and reliability of the read data may decrease. , Problems such as cell overlap and array size reduction may occur. In particular, if the resistance increases as the degree of integration increases, the sensing margin may be further reduced.

The present disclosure provides a magnetic memory device capable of increasing the sensing margin.

The present disclosure provides an operating method and a manufacturing method of such a magnetic memory device.

The magnetic memory device according to an embodiment includes a switching element and a storage node connected thereto, and the storage node includes a magnetic node in which two opposite bits are simultaneously written, and wherein one of the two bits is written The stacking order of the layers constituting a part of the magnetic node and the stacking order of the layers constituting the rest of the magnetic node in which the other of the two bits are recorded are the same.

In such a magnetic memory element, the switching element is a field effect transistor, and the source of the field effect transistor can be shared with neighboring field effect transistors.

The storage node may include two MTJs.

The two MTJs may be sequentially stacked and independent of each other.

Two bit lines are connected to the storage node, and the storage node may be provided between the two bit lines.

A method of operating a magnetic memory device according to an embodiment is a method of operating a magnetic memory device including a switching element and a storage node connected thereto, wherein the storage nodes are magnetic in which first and second bit data opposite to each other are recorded. A stacking order of layers comprising a node and forming part of the magnetic node in which one of the two bit data is recorded, and a stacking order of layers forming the other of the magnetic node in which the other one of the two bit data is recorded. It includes the process of applying an operating current to the magnetic node through two different and identical paths.

In this operating method, the operating current may be a write current for writing data to the magnetic node or a read current for reading data from the magnetic node.

A method of manufacturing a magnetic memory device according to an embodiment includes a process of forming a switching device on a substrate, a process of forming a storage node connected to the switching devices, and recording first and second bit data opposite to each other, and the storage And forming first and second bit lines connected to a node, and stacking order of layers constituting a part of the storage node in which one of the first and second bit data is recorded, and the first and second bit lines. The stacking order of the layers constituting the rest of the storage node in which the other one of the bit data is recorded is the same.

In this manufacturing method, the process of forming the storage node,

Forming a first MTJ in which one of the first and second bit data is recorded; forming a conductive pad layer connected to the switching element on the first MTJ; and on the conductive pad layer. And forming a second MTJ in which the other of the first and second bit data is recorded.

One of the first and second bit lines may be formed under the first MTJ, and the other may be formed on the second MTJ.

A process of forming a wire connected to the switching element between the first and second bit lines may be further included. In this case, the wiring may be formed below the first and second bit lines.

The magnetic memory device according to an embodiment is provided by stacking two MTJs in a unit cell. Read the data by measuring the resistance difference between the two stacked MTJs. Therefore, it is possible to secure a sensing margin twice that of a conventional MTJ on-state resistance and off-state resistance. In addition, since the two MTJs are vertically stacked, the sensing margin can be increased without increasing the area of the magnetic memory element.

1 is a three-dimensional view showing the structure of a magnetic memory device according to an embodiment.
2 is a three-dimensional view showing the structure of a magnetic memory device according to another embodiment.
3 is a layout of a memory including the magnetic memory device of FIG. 1 or 2.
4 is a cell array of a magnetic memory device according to an embodiment.
5 is an array for explaining a method of writing a magnetic memory device according to an embodiment.
6 is an array for explaining a method of writing a magnetic memory device according to another embodiment.
7 is a cross-sectional view showing a magnetization state of the first and second MTJ in the recording method of FIG. 5.
8 is a cross-sectional view showing a magnetization state of the first and second MTJ in the recording method of FIG. 6.
9 shows an array for explaining a method of reading a magnetic memory device according to an embodiment.
10 is a view for explaining a method of manufacturing a magnetic memory device according to an embodiment, and is a cross-sectional view of FIG. 3 taken along a 10-10' direction.
11 is a cross-sectional view showing another transistor that can replace the transistor of FIG. 10.

Hereinafter, a magnetic memory device having an increased on/off ratio and a method of manufacturing and operating the same according to an embodiment will be described in detail with reference to the accompanying drawings. In this process, the thickness of the layers or regions shown in the drawings is exaggerated for clarity of specification.

First, a magnetic memory device according to an embodiment will be described with reference to FIGS. 1 and 2.

1 shows a three-dimensional structure of a magnetic memory device according to an embodiment.

Referring to FIG. 1, a drain 20D and a source 20S exist under the gate stack 22+24G. The source 20S and the drain 20D are spaced apart. The gate stack 22+20G is positioned between the source 20S and the drain 20D. In the gate stack 22+20G, the gate insulating layer 22 and the gate electrode 20G may be sequentially stacked. The gate electrode 20G, the source 20S, and the drain 20D may be provided in a line form. The gate electrode 20G, the source 20S, and the drain 20D may constitute a transistor. Such a transistor is only an example of a switching element, and other switching elements may be provided instead of the transistor. First and second wirings 90 and 92 are provided on the gate electrode 20G. The first and second wirings 90 and 92 are provided in a direction crossing the gate electrode 20G. The first and second wirings 90 and 92 may be first and second bit lines. The first MTJ 30, the conductive pad layer 32 and the second MTJ 40 are sequentially stacked between the first and second wirings 90 and 92. The second MTJ 40 may be provided immediately above the first MTJ 30. Since the first and second MTJs 30 and 40 have a vertically stacked three-dimensional structure, even if two MTJs 30 and 40 are provided, the area of the memory cell is not further increased. The first and second MTJs 30 and 40 may constitute a storage node or a magnetic node. The pad layer 32 may be included in the storage node. The first MTJ 30 is provided on the first wiring 90, and the pinned layer 30p of the first MTJ 30 may be in direct contact with the first wiring 90. The second MTJ 40 is located under the second wiring 92. The second wiring 92 may directly contact the free layer 40f of the second MTJ 40. The first and second MTJs 30 and 40 are provided independently of each other. The pad layer 32 is in contact with the free layer 30f of the first MTJ 30 and is in contact with the pinned layer 40p of the second MTJ 40. The first and second MTJs 30 and 40 are formed by sequentially stacking the pinned layers 30p and 40p, the tunneling films 30t and 40t, and the free layers 30f and 40f, and may have the same layer configuration. . Opposing bits (data) may be written to the first and second MTJs 30 and 40. In other words, the layer configurations of the first and second MTJs 30 and 40 may be applied with operating currents, for example, write currents, in opposite directions to each other in the same state. Therefore, when 1 (or 0) is recorded in the first MTJ 30, for example, 0 (or 1) is recorded in the second MTJ 40. The pad layer 32 is connected to the drain 20D through the conductive plug 24. The third wiring 94 is provided at a position where the vertical position corresponds between the first and second wirings 90 and 92. The third wiring 94 may be provided at the same height as the pad layer 32. The third wiring 94 is connected to the source 20S through the conductive plug 26.

2 shows another three-dimensional structure of a magnetic memory device according to an embodiment. Only parts different from those in FIG. 1 will be described. The remaining part not described may be the same as FIG. 1.

Referring to FIG. 2, the position of the third wiring 94 is different from that of FIG. 1. That is, the third wiring 94 is provided at a lower position than the first wiring 90. In Figures 1 and 2, the source 20s is shared by two adjacent transistors.

3 shows a layout including the magnetic memory device of FIG. 1 or 2.

Referring to FIG. 3, the first and second wirings 90 and 92 (first and second bit lines) vertically cross the gate electrode 20G, that is, the word line. And the gate electrode 20G and the source 20S, that is, the source line are parallel. Reference numeral 20 denotes two adjacent transistors. Two adjacent transistors 20 share the source 20S.

4 shows a cell array of a magnetic memory device according to an embodiment.

Referring to FIG. 4, a plurality of transistors T1 are arranged in a matrix. Each transistor T1 has a source connected to a source line SL and a gate connected to a word line WL. Two MTJs 30 and 40 are arranged in each transistor T1. The two MTJs 30 and 40 are spaced apart, and the drain of the transistor T1 is connected to both MTJs 30 and 40 between the two MTJs 30 and 40. The first MTJ 30 of the two MTJs 30 and 40 is connected to the first bit line BL1, and the second MTJ 40 is connected to the second bit line BL2.

Next, an operation method of a magnetic memory device according to an embodiment will be described with reference to FIGS. 5 and 6.

5 shows an array used to describe the first recording method (first writing method). In FIG. 5, for convenience, only two unit memory cells are illustrated.

Referring to FIG. 5, a potential difference is formed between the source line SL and the bit lines BL1 and BL2 connected to the selected memory cell 95 to write data. That is, 0 V is applied to the source line SL, and the first write voltage Vw is applied to the first and second bit lines BL1 and BL2. In addition, a driving voltage VDD is applied to the word line WL connected to the transistor 23 of the selected memory cell 95, so that the transistor 23 is turned on. Accordingly, the first and second currents I1 and I2 are passed from the first and second bit lines BL1 and BL2 to the source line SL after the first and second MTJs 30 and 40 and the transistor 23. Flows. The amount of the first current I1 passing through the first MTJ 30 may be the same as the amount of the second current I2 passing through the second MTJ 40. However, the directions of the first and second currents I1 and I2 passing through the first and second MTJs 30 and 40 are opposite. Since the directions of the first and second currents I1 and I2 are opposite when the first and second MTJs 30 and 40 have the same layer configuration, the first and second MTJs 30 and 40 are opposite to each other. Bit data can be recorded. For example, the magnetization direction of the free layer of the first MTJ 30 by the first current I1 may be the same direction as the magnetization direction of the pinned layer, so the first MTJ 30 has a relatively low resistance. (Corresponding to bit data "1"). On the other hand, the magnetization direction of the free layer of the second MTJ 40 may be opposite to the magnetization direction of the pinned layer by the second current I2, so the second MTJ 40 has a relatively large resistance ( Bit data "0"). Bit data "1" (or "0") is regarded as a state in which the first MTJ 30 has a relatively low resistance, and bit data "0" in a state where the second MTJ 40 has a relatively high resistance. "(Or "1") can be regarded as recorded.

Fig. 6 shows an array used to describe the second recording method (second writing method). For convenience, only two unit memory cells are illustrated in FIG. 6. Only parts different from the first recording method in FIG. 5 will be described.

Referring to FIG. 6, 0V is applied to the source line SL and a second write voltage (-Vw) is applied to the first and second bit lines BL1 and BL2. Accordingly, the third and fourth currents flowing through the transistor 23 and the first and second MTJs 30 and 40 selected from the source line SL to the first and second bit lines BL1 and BL2, respectively. I3, I4) are generated. The amounts of the third and fourth currents I3 and I4 may be the same. However, the direction of the third current I3 passing through the first MTJ 30 and the direction of the fourth current I4 passing through the second MTJ 40 are opposite. The resistance states of the first and second MTJs 30 and 40 may be reversed from those of FIG. 5 by the third and fourth currents I3 and I4. That is, the first MTJ 30 is in a relatively high resistance state, and the second MTJ 40 is in a relatively small resistance state. Accordingly, the bit data recorded in the first and second MTJs 30 and 40 of FIG. 6 may be opposite to the bit data recorded in the first and second MTJs 30 and 40 of FIG. 5.

7 shows resistance states of the first and second MTJs 30 and 40 in the first recording method of FIG. 5.

Referring to FIG. 7, the magnetization direction of the free layer 30f of the first MTJ 30 is the same as the magnetization direction of the pinned layer 30p by the first current I1. Therefore, the resistance of the first MTJ 30 becomes relatively small (On resistance state). In addition, the magnetization direction of the free layer 40f of the second MTJ 40 while the second current I2 passes through the second MTJ 40 in the direction opposite to the first current I1 is the pinned layer 40p. It is opposite to the magnetization direction. Therefore, the resistance of the second MTJ 40 becomes relatively large (Off resistance state).

8 shows resistance states of the first and second MTJs 30 and 40 in the second recording method of FIG. 6.

Referring to FIG. 8, while the third current I3 opposite to the first current I1 passes through the first MTJ 30, the magnetization direction of the free layer 30f of the first MTJ 30 is a pinned layer. It is opposite to the magnetization direction of (30p). Therefore, the resistance of the first MTJ 30 becomes relatively large (Off resistance state). The magnetization direction of the free layer 40f of the second MTJ 40 is the magnetization direction of the pinned layer 40p while the fourth current I4 opposite to the second current I2 passes through the second MTJ 40. Will be the same as Therefore, the resistance of the second MTJ 40 becomes relatively small (On resistance state).

As such, in any case, the first and second MTJs 30 and 40 are bit data opposite to each other, so that one MTJ is turned on and the other is turned off, so the first and second MTJs The resistance difference between MTJs 30 and 40 becomes large.

9 illustrates an array for explaining a method (read method) of a magnetic memory device according to an embodiment. For convenience, only two unit memory cells are shown in FIG. 9.

Referring to FIG. 9, 0 V is applied to the source line SL and an operating voltage (read voltage) Vr is applied only to the first and second bit lines BL1 and BL2 connected to the selected memory cell 95. . Accordingly, a potential difference is formed between the first and second bit lines BL1 and BL2 and the source line SL, and the fifth and the second and third bit lines BL1 and BL2 are directed to the source line SL. The sixth currents I5 and I6 flow. The fifth and sixth currents I5 and I6 are operating currents for reading data recorded in the first and second MTJs 30 and 40. The fifth and sixth currents I5 and I6 are smaller than the first to fourth currents I1-I4. Therefore, even though the fifth and sixth currents I5 and I6 pass through the first and second MTJs 30 and 40, the resistance states of the first and second MTJs 30 and 40 do not change. The data recorded in the second MTJ 30, 40 is retained.

Since the current passing through the first MTJ 30 and the current passing through the second MTJ 40 will be different depending on the resistance state of each MTJ, data sensed and recorded in the first and second MTJs 30 and 40 Can be distinguished. By measuring the current passing through the first and second MTJs 30 and 40, the difference in resistance between the first and second MTJs 30 and 40 can be measured. Since the data is read by directly measuring the difference in resistance between one MTJ in the on-resistance state and another MTJ in the off-resistance state, after measuring the on-resistance and off-resistance of one MTJ, the measured values are turned on and off. The sensing margin can be doubled compared to the conventional case of reading data compared to a reference value between resistors. Also, by using a current sense amplifier, a high-speed read operation is possible.

Next, a method of manufacturing a magnetic memory device (MRAM) according to an embodiment will be described with reference to FIG. 10. FIG. 10 shows a cross-section of FIG. 3 taken in a 10-10' direction.

Referring to FIG. 10, a gate stack 70 is formed on a portion of the substrate 10. The substrate 10 may be a semiconductor substrate doped with a predetermined impurity. For example, it may be a silicon substrate. The gate stack 70 may include a stack of a gate insulating film and a gate electrode sequentially. First and second impurity regions 72 and 74 are formed on the substrate 10 on both sides of the gate stack 70. The first and second impurity regions 72 and 74 may be formed by ion implantation of conductive impurities. At this time, the conductive impurities may be of the opposite type to that doped to the substrate 10. For example, if the substrate 10 is doped with p-type impurities, the first and second impurity regions 72 and 74 may be formed by ion implantation of n-type impurities. One of the first and second impurity regions 72 and 74 may be a source region (source line) and the other may be a drain region. The first and second impurity regions 72 and 74, the gate stack 70 and the substrate 10 may constitute a field effect transistor. A first interlayer insulating layer 76 covering the field effect transistor is formed on the first substrate 10. The first interlayer insulating layer 76 may be formed of a known material such as BPSG or silicon oxide film. The first wiring 90 is formed on the first interlayer insulating layer 76. The first MTJ 30 is formed on the first wiring 90. Subsequently, a second interlayer insulating layer 80 covering the first wiring 90 and surrounding the first MTJ 30 is formed. The second interlayer insulating layer 80 may be the same as the first interlayer insulating layer 76. The conductive pad layer 32 is formed on the first MTJ 30. The pad layer 32 may be connected to the first impurity region 72. A third interlayer insulating layer 82 surrounding the pad layer 32 is formed on the second interlayer insulating layer 80. The third interlayer insulating layer 82 may be formed of the same material as the first interlayer insulating layer 76. The second MTJ 40 is formed on the pad layer 32. At this time, the second MTJ 40 may be formed to be located directly above the first MTJ 30. In this way, the first and second MTJs 30 and 40 are vertically stacked. The first and second MTJs 30, 40 are each independent. The second MTJ 40 may be formed to have the same layer structure as the first MTJ 30. For example, the second MTJ 40 may be formed by sequentially stacking a pinned layer, a tunneling film, and a free layer, and the first MTJ 30 may also be formed to have the same layer configuration. The first and second MTJs 30 and 40 may constitute one storage node. At this time, the pad layer 32 may also be included in the one storage node. Since the first and second MTJs 30 and 40 include magnetic layers, a storage node including the first and second MTJs 30 and 40 may be regarded as a magnetic node. A fourth interlayer insulating layer 84 surrounding the second MTJ 40 is formed on the third interlayer insulating layer 82. The fourth interlayer insulating layer 84 may be formed of the same material as the third interlayer insulating layer 82. The third wiring 92 is formed on the fourth interlayer insulating layer 84. The third wiring 92 is formed to contact the upper surface of the second MTJ 40.

On the other hand, the transistor formed of the substrate 10, the first and second impurity regions 72 and 74, and the gate stack 70 is replaced by a transistor provided with a source/drain on the channel layer as shown in FIG. It might be.

Referring to FIG. 11, a channel layer 102 is present on the substrate 100, and first and second electrodes 104 and 106 spaced apart from the channel layer 102 are formed. One of the first and second electrodes 104 and 106 may be a source electrode and the other may be a drain electrode. The gate insulating layer 108 is formed on the channel layer 102 between the first and second electrodes 104 and 106, and the gate electrode 110 is formed on the gate insulating layer 108.

Although many matters are specifically described in the above description, they should be interpreted as examples of preferred embodiments rather than limiting the scope of the invention. Therefore, the scope of the present invention should not be determined by the described embodiments, but should be determined by the technical spirit described in the claims.

10, 100: substrate 20: two adjacent transistors
20D: Drain 20G, 110: Gate electrode
20S: source 22, 108: gate insulating film
23: Transistor of the selected memory cell
24, 26: conductive plug 30, 40: first and second MTJ
30f, 40f: free layer 30p, 40p: pinned layer
30t, 40t: Tunneling film 32: Pad layer
70: gate stack 72, 74: first and second impurity regions
76, 80, 82, 84: first to fourth interlayer insulating layers
90, 92, 94: first to third wiring 95: selected memory cell
102: channel layer 104, 106: first and second electrodes
BL1, BL2: first and second bit lines I1-I6: first to sixth currents
Vw: 1st write voltage -Vw: 2nd write voltage
SL: Source line T1: Transistor
WL: Wordline

Claims (15)

Switching element; And
Includes; a storage node connected to the switching element,
The storage node includes a magnetic node in which two opposite bits are simultaneously written,
A stacking order of layers constituting a part of the magnetic node in which one of the two bits is written, and a stacking order of layers constituting the rest of the magnetic node in which the other one of the two bits is written are the same as each other. According to claim 1,
The switching element is a field effect transistor,
The field effect transistor is a magnetic memory device including a source shared with a neighboring field effect transistor. According to claim 1,
The storage node is a magnetic node, and a magnetic memory device including two MTJs. The method of claim 3,
The two MTJs are sequentially stacked and are independent of each other. The method of claim 1 or 3,
Two bit lines are connected to the storage node, and the storage node is a magnetic memory device provided between the two bit lines. In the operating method of a magnetic memory device comprising a switching element and a storage node connected to the switching element,
The storage node includes magnetic nodes to which first and second bit data opposite to each other are recorded,
The stacking order of the layers constituting a part of the magnetic node in which one of the two bit data is recorded and the stacking order of the layers constituting the rest of the magnetic node in which the other one of the two bit data is recorded are the same,
And applying an operating current to the magnetic node through two different paths. The method of claim 6,
The operating current is a write current for writing data to the magnetic node. The method of claim 6,
The operating current is a read current for reading data from the magnetic node. The method of claim 6,
The storage node is sequentially stacked and operating method of a magnetic memory device including two independent MTJ. The method of claim 9,
A method of operating a magnetic memory device in which two bit lines are connected to the storage node, and the storage node is provided between the two bit lines. Forming a switching element on the substrate;
Forming a storage node connected to the switching element and having opposite first and second bit data; And
And forming first and second bit lines connected to the storage node.
Stacking order of layers constituting part of the storage node in which one of the first and second bit data is written, and stacking order in layers constituting the rest of the storage node in which the other of the first and second bit data is written Is a manufacturing method of the same magnetic memory device. The method of claim 11,
The forming of the storage node may include:
Forming a first MTJ in which one of the first and second bit data is recorded
Forming a conductive pad layer connected to the switching element on the first MTJ; and
And forming a second MTJ on which the other of the first and second bit data is written on the conductive pad layer. The method of claim 12,
A method of manufacturing a magnetic memory device, wherein one of the first and second bit lines is formed below the first MTJ, and the other is formed on the second MTJ. The method of claim 13,
And forming a wire connected to the switching element between the first and second bit lines. The method of claim 13,
And forming wirings connected to the switching elements below the first and second bit lines.

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