KR20150068264A - Processor having a variable pipeline, and system-on-chip - Google Patents

Abstract

The processor includes a security level determination unit and a variable pipeline. The security level determination unit determines the security level of the encrypted data to be processed by the processor. The variable pipeline receives encrypted data, decrypts the encrypted data during a clock cycle corresponding to the security level determined by the security level determination unit, generates original data, and processes the original data. Thus, a strong encryption operation can be performed without substantially degrading the operation performance, so that the data can be safely protected.

Description

PROCESSOR HAVING A VARIABLE PIPELINE, AND SYSTEM-ON-CHIP < RTI ID = 0.0 >

The present invention relates to a processor, and more particularly, to a processor having a variable pipeline and a system-on-chip comprising the same.

Instructions and / or data are encrypted and stored in a security product such as a smart card, a Trusted Platform Module (TPM), and the like. In such a security product, the encryption unit disposed outside the processor decrypts and provides the encrypted instructions and / or data to the processor in order for the processor to execute such stored encrypted instructions and / or data. On the other hand, in order not to affect the operation performance (or operation speed) of the system, the encryption unit disposed outside the processor must perform a simple encryption / decryption operation having an operation time of less than one clock cycle. However, as hacking (or tampering) techniques become more sophisticated, data and / or instructions encrypted by such simple encryption operations may be more easily restored to raw data by hackers (or attackers) . To prevent such data leakage, the encryption unit disposed outside the processor can perform encryption / decryption operations of one clock cycle or more. However, in this case, the operation performance may be greatly deteriorated.

In order to solve the above problems, it is an object of the present invention to provide a processor having a variable pipeline.

Another object of the present invention is to provide a system-on-chip (SOC) including the processor.

It is to be understood, however, that the present invention is not limited to the above-described embodiments and various modifications may be made without departing from the spirit and scope of the invention.

In order to achieve the above object, a processor according to embodiments of the present invention includes: a security level determination unit that determines a security level of encrypted data to be processed in a processor; and a security level determination unit that receives the encrypted data, And a variable pipeline for performing a decryption operation on the encrypted data during a clock cycle corresponding to the security level determined by the security level to generate original data and processing the original data.

In one embodiment, the variable pipeline may include a variable decryption block that changes the computation time of the decryption operation according to the security level of the encrypted data.

In one embodiment, the variable decryption block does not perform the decryption operation when the security level of the encrypted data is a low security level, and when the security level of the encrypted data is a general security level, And perform the decryption operation during the computation time of two or more clock cycles when the security level of the encrypted data is a high security level.

In one embodiment, the variable pipeline includes: a variable decryption block for decrypting the encrypted data input to the processor during the clock cycle corresponding to the security level to generate the original data; A decode block for decrypting the original data, and an execution block for executing the decrypted original data.

In one embodiment, the variable pipeline includes a fetch block for storing the encrypted data input to the processor in a register, a decryption unit for decrypting the encrypted data stored in the register during the clock cycle corresponding to the security level, A variable decoding block for generating original data, a decode block for decoding the original data, and an execution block for executing the decoded original data.

In one embodiment, the variable pipeline includes a plurality of decryption blocks connected in series and a plurality of decryption blocks, respectively disposed in front of the decryption blocks, each having a data path corresponding to a corresponding decryption block of the decryption blocks, And may include a plurality of switches that selectively connect the plurality of switches.

In one embodiment, each of the plurality of switches corresponding to the clock cycle corresponding to the security level connects the data path to the corresponding decryption block, and the remaining of the plurality of switches Each of which may connect the data path to a block of the next stage.

In one embodiment, the variable pipeline includes a plurality of decryption blocks that perform the decryption operation for different computation times, and a decryption unit that decrypts the data path using the computation time of the clock cycle corresponding to the security level of the decryption blocks And a switch for connecting the decoding block to the decoding block.

In one embodiment, the variable pipeline includes a plurality of decryption blocks for performing the decryption operation of different decryption algorithms, and a decryption block for decrypting the data path to a decryption block of the decryption algorithm corresponding to the security level of the decryption blocks And may include a switch for connecting.

In one embodiment, the variable pipeline may encrypt the processing result of the original data during the clock cycle corresponding to the security level and output the encrypted data to the outside.

In one embodiment, the variable pipeline may include a variable encryption block that alters the computation time of the encryption operation according to the security level.

In one embodiment, the security level determination unit includes: a security policy storage unit that stores an address range for the encrypted data and a number of clock cycles corresponding to the address range; and an address of the encrypted data to be processed in the processor To read the number of clock cycles corresponding to the address range to which the received address belongs from the security policy storage unit, and to perform the decryption operation for an operation time corresponding to the number of read clock cycles And a pipeline control unit for controlling the pipeline.

In one embodiment, the security policy storage unit further stores an encryption key corresponding to the address range, and the pipeline control unit controls the encryption key corresponding to the encryption key corresponding to the address range to which the received address belongs, And to control the variable pipeline to perform an operation.

In one embodiment, the security policy storage further stores a type of a decryption algorithm corresponding to the address range, and the pipeline control unit controls the decryption algorithm of the decryption algorithm corresponding to the address range to which the received address belongs, And to control the variable pipeline to perform an operation.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a system-on-chip comprising a memory unit for storing encrypted data and a memory unit for receiving the encrypted data from the memory unit, And a processor for decrypting the encrypted data during a clock cycle corresponding to the determined security level to generate original data, and processing the original data.

The processor and system-on-chip according to embodiments of the present invention include a variable pipeline that adjusts the computation time of the encryption / decryption operation according to the security level of the data to be processed, Strong encryption / decryption operations can be performed.

In addition, the processor and the system-on-chip according to embodiments of the present invention are capable of safely protecting data by performing an encryption / decryption operation on data in a pipeline of the processor.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously expanded without departing from the spirit and scope of the present invention.

1 is a block diagram illustrating a processor in accordance with embodiments of the present invention.
2 is a block diagram illustrating a processor in accordance with one embodiment of the present invention.
3 is a timing diagram showing an execution cycle of the processor of Fig.
4 is a block diagram illustrating a processor in accordance with another embodiment of the present invention.
5 is a timing diagram showing an execution cycle of the processor of Fig.
6 is a block diagram illustrating a processor in accordance with another embodiment of the present invention.
7 is a block diagram illustrating a processor in accordance with another embodiment of the present invention.
8 is a block diagram illustrating a processor in accordance with another embodiment of the present invention.
9 is a block diagram illustrating a processor in accordance with another embodiment of the present invention.
10 is a timing diagram showing an execution cycle of the processor of Fig.
11 is a block diagram illustrating a system-on-chip in accordance with embodiments of the present invention.
12 and 13 are views showing examples in which a system-on-chip according to embodiments of the present invention is employed in a smart card.
14 is a diagram showing an example in which a system-on-chip according to embodiments of the present invention is employed in a Trusted Platform Module (TPM).
15 is a diagram showing an example in which a system-on-chip according to embodiments of the present invention is employed in an application processor (AP).

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

Here, the term " data " refers to an " instruction " (also referred to as program data, program code, etc.) executed by a processor, Quot; normal data ", or may be used to refer collectively to the instruction and the data.

Here, the term " pipeline " means a data processing method in which a plurality of data are processed in parallel by respective stages connected in series, or a hardware configuration for performing such a parallel data processing method Can be used to mean.

1 is a block diagram illustrating a processor in accordance with embodiments of the present invention.

Referring to FIG. 1, the processor 100 includes a variable pipeline 110 and a security level determination unit 150.

The security level determination unit 150 determines the security level of the encrypted data (ENC-DATA) to be processed by the processor 100. Here, the encrypted data (ENC-DATA) indicates that the program data (which may be referred to as an encrypted instruction, an encrypted program code, or the like) executed by the processor 100 is encrypted, May indicate that the normal data used, modified or generated by the user is encrypted. The security level determination unit 150 may determine the security level of the encrypted data (ENC-DATA) according to the location where the encrypted data (ENC-DATA) is stored in the external memory. For example, the security level determination unit 150 stores the security level set for the predetermined address range of the external memory, and when the encrypted data (ENC-DATA) input to the processor 100 is an address belonging to the address range The security level determining unit 150 may determine the security level of the encrypted data (ENC-DATA) to be the security level set as described above.

The variable pipeline 110 may receive the encrypted data (ENC-DATA) and perform a decryption operation on the encrypted data (ENC-DATA) to generate the original data. Thus, since the decryption operation for the encrypted data (ENC-DATA) is performed in the processor 100 (i.e., the variable pipeline 110), data is encrypted outside the processor 100, Is not exposed. Thus, the data can be safely protected.

In addition, the variable pipeline 110 may perform a decryption operation on the encrypted data (ENC-DATA) during a clock cycle corresponding to the security level determined by the security level determination unit 150 to generate original data have. Each encrypted data ENC-DATA may have one of a plurality of security levels, and the variable pipeline 110 may have different clock cycles for encrypted data ENC-DATA of different security levels The decoding operation can be performed. For example, each encrypted data (ENC-DATA) may have one of three security levels, and the variable pipeline 110 may determine that the security level of the encrypted data (ENC-DATA) low security level, the decryption operation is not performed and the decryption operation is performed during a computation time of one clock cycle when the security level of the encrypted data (ENC-DATA) is a normal security level, When the security level of the encrypted data (ENC-DATA) is high security level, the decryption operation can be performed during the operation time of two or more clock cycles. Thus, the computation time of the decryption operation is changed according to the security level of the encrypted data (ENC-DATA) to be processed, and the number of execution clock cycles of the variable pipeline 110 can be changed. Accordingly, the encryption / decryption operation of the encryption / decryption algorithm suitable for the security level of each data can be performed.

In one embodiment, the variable pipeline 100 is configured to perform encryption / decryption operations corresponding to the security level of each data so as to perform variable encryption (encryption / decryption) for changing the operation time of the decryption operation according to the security level of the encrypted data Block. In another embodiment, the variable pipeline 100 comprises a plurality of decryption blocks coupled in series, wherein the encrypted data (ENC-DATA) is the number of clock cycles corresponding to the security level of the plurality of decryption blocks It is possible to pass through the decryption block. In another embodiment, the variable pipeline 100 includes a plurality of decryption blocks having different computation times, and the encrypted data (ENC-DATA) is a decryption key of a clock cycle corresponding to the security level of the decryption blocks It is possible to pass the decoding block having the calculation time. According to an embodiment, the decryption blocks having different computation times may perform a decryption operation of the same decryption algorithm or a decryption operation of different decryption algorithms.

In addition, the variable pipeline 110 may process the original data. For example, the variable pipeline 110 may process the original data by performing a fetch operation, a decode operation, and an execute operation on the original data. In another example, to process the original data, the variable pipeline 110 may include a fetch operation, a decode operation, an execute operation, a buffer / data operation, - Can perform a write-back operation.

In one embodiment, when the processing result of the original data is to be stored in the external memory, the variable pipeline 110 encrypts the processing result of the original data for a clock cycle corresponding to the security level, ENC-RES-DATA) to the outside. For example, the variable pipeline 110 does not perform the encryption operation when the security level is the low security level, and performs the encryption operation during the operation time of one clock cycle when the security level is the general security level And may perform the encryption operation for a computation time of two or more clock cycles if the security level is a high security level. In one embodiment, the variable pipeline 110 may include a variable encryption block that changes the computation time of the encryption operation in accordance with the security level, so as to perform encryption / decryption operations appropriate to the security level of each data. Thus, the computation time of the encryption / decryption operation is changed according to the security level of the encrypted data (ENC-DATA) to be processed or the security level of the encrypted result data (ENC-RES-DATA) to be stored, 110 may be changed. Accordingly, the encryption / decryption operation of the encryption / decryption algorithm suitable for the security level of each data can be performed.

As such, the processor 100 may perform data processing, including encryption / decryption of data, using the variable pipeline 110. That is, the fetch operation, the decode operation, and the write operation together with the encryption / decryption operation can be performed in a pipelined manner. Accordingly, when encryption / decryption operations of a strong encryption / decryption algorithm of one clock cycle or more are performed for data to be processed consecutively, a time delay for data to be initially processed may occur, There is no time delay and / or operation performance That is, the processor 100 according to the embodiments of the present invention can perform a strong encryption / decryption operation without substantially degrading the operation performance.

As described above, the processor 100 according to the embodiments of the present invention performs encryption / decryption operations on data in the processor 100, i.e., the variable pipeline 110, The data can be safely protected. In addition, the processor 100 according to the embodiments of the present invention performs the encryption / decryption of data in a pipelined manner together with fetching, decoding, and / or the like so that the performance of the processor 100 and the system including the processor 100 is almost It may not deteriorate. In addition, the processor 100 according to embodiments of the present invention includes a variable pipeline that adjusts the computation time of the encryption / decryption operation according to the security level of the data to be processed, The encryption / decryption operation of the strong encryption / decryption algorithm can be performed, and the data that requires low level security can be processed faster.

Figure 2 is a block diagram illustrating a processor in accordance with one embodiment of the present invention, and Figure 3 is a timing diagram illustrating an execution cycle of the processor of Figure 2;

Referring to FIG. 2, the processor 200 includes a variable pipeline 210 and a security level determination unit 250.

The security level determination unit 250 determines the security level of the encrypted data (ENC-DATA) to be processed by the processor 200. [ The security level determination unit 250 stores the security policy for the encrypted data ENC-DATA, determines the security level of the encrypted data ENC-DATA to be processed based on the stored security policy, The variable pipeline 210 may be controlled based on the security level. In one embodiment, the security level determination unit 250 includes a security policy storage unit 260 that stores a security policy for encrypted data ENC-DATA, and a security policy storage unit 260 that stores security policies And a pipeline control unit 280 for controlling the variable pipeline 210 based on the received signal.

For example, the security policy storage unit 260 may store at least one security policy record 270 for encrypted data (ENC-DATA). As an example, the security policy record 270 includes a range 272 of addresses of the external memory, a clock cycle of the encryption / decryption operation to be performed on the encrypted data ENC-DATA stored in the range 272 of this address Number 274 and an encryption key 276 used in encryption / decryption operations to be performed on the encrypted data ENC-DATA stored in the range 272 of addresses. In one embodiment, the security policy record 270 may be written to the security policy store 260 when a predetermined application or program is loaded into the external memory to be executed.

The pipeline control unit 280 may receive the address ADDR of the encrypted data ENC-DATA to be processed by the processor 200. [ For example, the pipeline control unit 280 may include a predetermined register included in the processor 200, for example, a program counter (PC), an instruction pointer (IP), or an instruction register (ADDR) of the encrypted data (ENC-DATA) that is input to the variable pipeline 210 from the input buffer (IR).

The pipeline control unit 280 searches the security policy record 270 including the range 272 of the address to which the address ADDR received in the security policy storage unit 260 belongs, The number of clock cycles 274 included in the security policy record 270 can be read. The pipeline control unit 280 provides the variable number pipeline 210 with a cycle number signal NCYC indicative of the number of clock cycles 274 so that the variable pipeline 210 has an operation time corresponding to the clock cycle number 274 Lt; RTI ID = 0.0 > 210 < / RTI > The pipeline control unit 280 may further read the encryption key 276 included in the security policy record 270 from the security policy storage unit 260. [ The pipeline control unit 280 provides the variable pipeline 210 with the encryption key 276 to the variable pipeline 210 so that the variable pipeline 210 uses the encryption key 276 to perform the decryption operation. Can be controlled.

The variable pipeline 210 receives the encrypted data ENC-DATA and decrypts the encrypted data ENC-DATA for a clock cycle corresponding to the security level determined by the security level determination unit 250 To generate the original data, and to process the original data. In one embodiment, the variable pipeline 210 may include a variable decryption block 220, a fetch block 230, a decode block 232, and an exclude block 234.

The variable decryption block 220 may decrypt the encrypted data ENC_DATA input to the processor 200 during a clock cycle corresponding to the security level thereof to generate original data. That is, the variable decryption block 220 can change the operation time of the decryption operation according to the security level of the encrypted data (ENC_DATA). In one embodiment, the pipeline controller 280 may provide the variable number decoding unit 220 with a cycle number signal NCYC indicating the number of clock cycles corresponding to the security level of the encrypted data ENC_DATA, The block 220 may perform a decryption operation for a number of clock cycles indicated by the cycle number signal NCYC input from the pipeline control unit 280. [ For example, if the security level of the encrypted data (ENC_DATA) is a low security level, the cycle number signal NCYC may represent zero clock cycles, and the variable decryption block 220 may not perform a decryption operation . Further, when the security level of the encrypted data ENC_DATA is a general security level, the cycle number signal NCYC may represent one clock cycle, and the variable decryption block 220 may perform a decryption operation during a computation time of one clock cycle Can be performed. Further, when the security level of the encrypted data ENC_DATA is a high security level, the cycle number signal NCYC may represent 2 clock cycles, and the variable decryption block 220 may perform the decryption operation during the computation time of 2 clock cycles Can be performed. The variable decryption block 220 may further receive the encryption key KEY from the pipeline controller 280 and may perform the decryption operation using the received encryption key KEY. In this way, since the decoding operation is performed by the processor 200, that is, the variable decoding block 220, the original data is not exposed to the outside of the processor 200, so that the data can be protected more securely.

The fetch block 230 may store the original data generated by the variable decryption block 220 in a register included in the processor 200. [ For example, the fetch block 230 may store the original data in an instruction register (IR). The decode block 232 may decode the original data. For example, the decode block 232 may decode the original data stored in the instruction register to determine an operation to be performed in the execution block 234. The execution block 234 may execute the decrypted original data.

This variable pipeline 210 can process the encrypted data ENC_DATA in a pipeline manner in parallel. FIG. 3 shows an example of the pipeline processing of the variable pipeline 210. 3, reference numeral 310 denotes execution timing for the first encrypted data (ENC-DATA1) having the general security level, reference numeral 330 denotes execution timing for the second encrypted data (ENC-DATA2) having the general security level (ENC-DATA3) having a high security level, and 370 indicates an execution timing for the fourth encrypted data (ENC-DATA4) having a high security level have.

As shown in FIG. 3, the first encrypted data (ENC-DATA1) may be input to the processor 200 in a first clock cycle. On the other hand, the data may arrive at the processor 200 before a predetermined setup time (for example, a CPU setup time) from the time when the processing for the data is performed so that data is correctly input to the processor 200 . In the second clock cycle, the second encrypted data (ENC-DATA2) may be input to the processor 200 while the decryption operation for the first encrypted data (ENC-DATA1) is performed. Fetch operation on the first encrypted data (ENC-DATA1) (or original data of the first encrypted data (ENC-DATA1)) in the third clock cycle, a fetch operation on the second encrypted data (ENC- Operation, and input of the third encrypted data (ENC-DATA3) can be performed simultaneously. Also, in a fourth clock cycle, a decode operation for the first encrypted data (ENC-DATA1), a fetch operation for the second encrypted data (ENC-DATA2), a second fetch operation for the third encrypted data Decryption operation, and input of the fourth encrypted data (ENC-DATA4) can be performed simultaneously. In this way, each stage of the variable pipeline 210, that is, the variable decode block 220, the fetch block 230, the decode block 232, and the exclude block 234, , ENC-DATA2, ENC-DATA3, ENC-DATA4) in parallel, processing performance of the processor 200 and the system including the processor 200 can be improved.

(ENC-DATA1) among the data (ENC-DATA1, ENC-DATA2, ENC-DATA3 and ENC-DATA4) which are successively processed as compared with the case where the encryption / The processing time may be delayed by one clock cycle and the computation time of the decryption operation is increased (for example, when the third encrypted data (ENC-DATA3) is processed). However, since the encryption / decryption operation is performed in a pipelined manner together with the fetch operation, the decode operation, and the exhaust operation, no delay may occur in the subsequent processing. Therefore, the delay in the overall processing time of the data (ENC-DATA1, ENC-DATA2, ENC-DATA3, and ENC-DATA4) continuously processed by this pipelined processing may be insignificant.

Also, as in the example shown in Fig. 3, the decryption operation for the encrypted data (ENC-DATA1, ENC-DATA2) having the general security level is performed for one clock cycle, and the encrypted data (ENC-DATA3, ENC-DATA4) may be performed for two clock cycles. Thus, the computation time of the encryption / decryption operation can be adjusted according to the security level of the data. Accordingly, the encryption / decryption operation of the encryption / decryption algorithm suitable for the security level of each data can be performed.

As described above, the processor 200 according to an exemplary embodiment of the present invention performs a decoding operation on data in the processor 200, that is, the variable decoding block 220, so that original data is not exposed to the outside Data can be safely protected. In addition, the processor 200 according to an embodiment of the present invention performs pipelining of decoding of data with fetching, decoding, and / or the like, thereby substantially degrading the performance of the processor 200 and the system including the processor 200 . In addition, the processor 200 according to an embodiment of the present invention includes a variable pipeline that adjusts the computation time of the decryption operation according to the security level of the data to be processed, so that a strong It is possible to perform a decryption operation of a decryption algorithm and to perform a quick process on data requiring a low level of security.

FIG. 4 is a block diagram illustrating a processor according to another embodiment of the present invention, and FIG. 5 is a timing diagram illustrating an execution cycle of the processor of FIG.

Referring to FIG. 4, the processor 400 includes a variable pipeline 410 and a security level determination unit 450. The processor 400 of Figure 4 may have a similar configuration to the processor 200 of Figure 2 except that the variable decoding block 420 is disposed between the fetch block 430 and the decode block 432. [

The security level determination unit 450 determines the security level of the encrypted data (ENC-DATA) to be processed by the processor 400. [ The security level determination unit 450 may include a security policy storage unit 460 and a pipeline control unit 480. The security policy storage unit 460 may store at least one security policy record 470 for the encrypted data ENC-DATA. As an example, the security policy record 470 may include a range of addresses 472, a number of clock cycles 474, and an encryption key 476. The pipeline control unit 480 receives the address ADDR of the encrypted data ENC-DATA and stores the security address in the security policy storage unit 460, which includes the range 472 of the address to which the address ADDR received, The policy record 470 can be searched. The pipeline control unit 480 may provide the number of clock cycles 474 and the encryption key 476 included in the discovered security policy record 470 to the variable decryption block 420 included in the variable pipeline 410 have.

The variable pipeline 410 may include a fetch block 430, a variable decryption block 420, a decode block 432, and an exclude block 434. Fetch block 430 may fetch encrypted data (ENC-DATA) from an external memory and store it in a register included in processor 400. [ For example, the fetch block 430 may store the encrypted data (ENC-DATA) in an instruction register (IR). The variable decryption block 420 may decrypt the encrypted data ENC-DATA stored in the register for a clock cycle corresponding to the security level of the encrypted data ENC-DATA to generate original data. For example, the variable decryption block 420 may perform a decryption operation for the number of clock cycles indicated by the cycle number signal NCYC input from the pipeline control unit 480. [ In addition, the variable decryption block 420 may perform the decryption operation using the encryption key (KEY) input from the pipeline controller 480. [ For example, the original data generated by the variable decryption block 420 may be stored in the instruction register or other register. Decode block 432 may decode the original data and execute block 434 may execute the decoded original data.

This variable pipeline 410 may process the encrypted data ENC_DATA in parallel in a pipelined fashion. FIG. 5 shows an example of the pipeline processing of the variable pipeline 410. 5, reference numeral 510 denotes execution timing for the first encrypted data (ENC-DATA1) having the general security level, reference numeral 530 denotes execution timing for the second encrypted data (ENC-DATA2) having the general security level 550 indicates the execution timing for the third encrypted data (ENC-DATA3) having a high security level, and 570 indicates the execution timing for the fourth encrypted data (ENC-DATA4) having the high security level have.

As shown in FIG. 5, a fetch operation, a decryption operation, a decode operation, and an excitation operation may be sequentially performed on each of the encrypted data (ENC-DATA1, ENC-DATA2, ENC-DATA3 and ENC-DATA4) . Each of the stages of the variable pipeline 410, that is, the fetch block 430, the variable decoding block 420, the decode block 432, and the exclude block 434 are provided with different data (ENC-DATA1, ENC -DATA2, ENC-DATA3, ENC-DATA4) in parallel, processing performance of the processor 400 and the system including the same can be improved. In addition, since the encryption / decryption operation is performed in a pipelined manner together with the fetch operation, the decode operation, and the execution operation, the operation performance may not be substantially lowered. In addition, the computation time of the encryption / decryption operation can be adjusted according to the security level of the data. Accordingly, the encryption / decryption operation of the encryption / decryption algorithm suitable for the security level of each data can be performed.

As described above, the processor 400 according to another embodiment of the present invention performs a decoding operation on data in the processor 400, that is, the variable decoding block 420, so that the original data is not exposed to the outside Data can be safely protected. In addition, the processor 400 according to another embodiment of the present invention performs pipelining of decoding of data with fetching, decoding, and / or the like, thereby substantially reducing the performance of the processor 400 and the system including the processor 400 . In addition, the processor 400 according to another embodiment of the present invention includes a variable pipeline that adjusts the computation time of the decryption operation according to the security level of the data to be processed, It is possible to perform a decryption operation of a decryption algorithm and to perform a quick process on data requiring a low level of security.

On the other hand, although FIGS. 2 and 4 show an example in which the stages of the pipeline excluding the decryption block are three stages of a fetch stage, a decode stage, and an execute stage, according to an embodiment, Stages. 2 and 4 show an example in which the processor includes one pipeline, however, according to an embodiment, the processor may include more than one pipeline. 4 shows an example in which the variable decryption block 420 is located between the fetch block 430 and the decode block 432. The variable decryption block 420 is provided between the fetch block 430 and the decode block 432, The variable decoding block 220 or at least one decoding block to be described later may be disposed at any position on the variable pipeline. Hereinafter, embodiments in which at least one decoding block is disposed at the front end of the fetch block 230 will be described as an example.

6 is a block diagram illustrating a processor in accordance with another embodiment of the present invention.

Referring to FIG. 6, the processor 600 includes a variable pipeline 610 and a security level determination unit 650. The processor 600 of FIG. 6 includes a plurality of decryption blocks 621, 623 and 625 connected in series instead of the variable decryption block 220 shown in FIG. 2, and a plurality of switches 622, 624, 626, 628, as well as a processor 200 similar to that of FIG.

The security level determination unit 650 determines the security level of the encrypted data (ENC-DATA) to be processed by the processor 600. [ The security level determination unit 650 may include a security policy storage unit 660 and a pipeline control unit 680. The security policy storage unit 660 may store at least one security policy record 670 for the encrypted data ENC-DATA. As an example, the security policy record 670 may include a range of addresses 672, a number of clock cycles 674, and an encryption key 676. The pipeline control unit 680 receives the address ADDR of the encrypted data ENC-DATA and stores the security data in the security policy storage unit 660, which includes the range 672 of the address to which the address ADDR received, The policy record 670 can be searched. The pipeline control unit 680 includes a plurality of switching signals for controlling the plurality of switches 622, 624, 626, 628 based on the number of clock cycles 674 included in the detected security policy record 670 SWS1, SWS2, SWSN and SWSO and provides the encryption key 676 included in the searched security policy record 670 to the decryption blocks 621, 623 and 625 included in the variable pipeline 610 can do.

The variable pipeline 610 includes a plurality of decryption blocks 621, 623 and 625 connected in series, a plurality of switches 622, 624 and 626 respectively arranged at the front ends of decryption blocks 621, 623 and 625, A fetch block 630, a decode block 632, and an exclude block 634. [ Each of the decryption blocks 621, 623, and 625 can perform a decryption operation of one clock cycle. Each of the switches 622, 624 and 626 selectively connects the data path coupled to its input to a corresponding one of the decode blocks 621, 623 and 625 or to a block of the next stage (i.e., the fetch block 630) You can connect. For example, the first switch 622 may selectively couple the data path to the first decoding block 621 or the fetch block 630 in response to the first switching signal SWS1, The Nth switch 626 may selectively connect the data path to the second decoding block 623 or the fetch block 630 in response to the second switching signal SWS2, Thereby selectively coupling the data path to the Nth decryption block 625 or the fetch block 630. [ In one embodiment, the variable pipeline 610 may further include a switch 628 disposed at the front end of the fetch block 630. The switch 628 may couple one of the plurality of data paths to the fetch block 630 in response to the switching signal SWSO.

The pipeline controller 680 is located at the front of the plurality of switches 622, 624, and 626, and the number of switches corresponding to the number of clock cycles 674 connects the data paths to the corresponding decryption blocks, The switching signals SWS1, SWS2, and SWSN may be generated so that the switches connect the data path to the fetch block 630. [

For example, when the number of clock cycles 674 corresponding to the address range 672 to which the address ADDR of the encrypted data (ENC-DATA) belongs is 1, the pipeline control unit 680 outputs the first switching signal SWS1 to the first logic level and the remaining switching signals SWS2, SWSN to the second logic level. The first switch 622 couples the data path of the encrypted data ENC-DATA in response to the first switching signal SWS1 of the first logic level to the first decoding block 621 and the remaining switches 624 , 626 (or the second switch 624 as the immediately following switch) may couple the data path to the fetch block 630 in response to the second logic level switching signals SWS2, SWSN. Accordingly, the decryption operation of one clock cycle is performed by the first decryption block 621 on the encrypted data (ENC-DATA), so that the original data can be generated. Meanwhile, the first decryption block 621 may perform the decryption operation using the encryption key (KEY) provided from the pipeline controller 680. In another example, when the number of clock cycles 674 is two, the first and second switching signals SWS1 and SWS2 have a first logic level and the remaining switching signals SWSN have a second logic level . Accordingly, the decryption operation of two clock cycles is performed on the encrypted data (ENC-DATA) by the first and second decryption blocks 621 and 623 to generate original data. The first and second decryption blocks 621 and 623 may perform the decryption operation using the encryption key KEY provided from the pipeline controller 680. [

The fetch block 630 may store the original data in a predetermined register included in the processor 600. [ Decode block 632 may decode the original data, and the EXECUTE block 634 may execute the decoded original data.

As described above, the processor 600 according to another embodiment of the present invention performs a decoding operation on data in the processor 600, i.e., in a plurality of cascade-connected decryption blocks 621, 623, and 625 , The original data is not exposed to the outside, so that the data can be safely protected. In addition, the processor 600 according to another embodiment of the present invention performs pipelining of decoding of data with fetching, decoding, and / or the like, thereby substantially reducing the performance of the processor 600 and the system including the processor 600 . In addition, the processor 600 according to another embodiment of the present invention includes a variable pipeline that adjusts the computation time of the decryption operation according to the security level of the data to be processed, It is possible to perform a decryption operation of a strong decryption algorithm and to perform a quick process on data requiring a low level of security.

7 is a block diagram illustrating a processor in accordance with another embodiment of the present invention.

Referring to FIG. 7, the processor 700 includes a variable pipeline 710 and a security level determination unit 750. The processor 700 of FIG. 7 includes a plurality of decryption blocks 721, 723, and 725 that perform a decryption operation for different computation time on behalf of the variable decryption block 220 shown in FIG. 2, , But may have a similar configuration to the processor 200 of FIG.

The security level determination unit 750 determines the security level of the encrypted data (ENC-DATA) to be processed by the processor 700. [ The security level determination unit 750 may include a security policy storage unit 760 and a pipeline control unit 780. At least one security policy record 770 for the encrypted data (ENC-DATA) may be stored in the security policy storage unit 760. As an example, the security policy record 770 may include a range of addresses 772, a number of clock cycles 774, and an encryption key 776. The pipeline control unit 780 receives the address ADDR of the encrypted data ENC-DATA and sends a security policy including the range 772 of the address 772 to which the address ADDR received in the security policy storage unit 760 belongs The policy record 770 can be searched. The pipeline control unit 780 generates a switching signal SWS for controlling the switch 722 based on the number of clock cycles 774 included in the discovered security policy record 770 and outputs the detected security policy record 730 included in the variable pipeline 710 to the decryption blocks 721, 723, and 725 included in the variable pipeline 710.

The variable pipeline 710 includes a plurality of decryption blocks 721, 723 and 725 having different computation times, a switch 722 disposed in front of the decryption blocks 721, 723 and 725, a fetch block 730 ), A decode block 732, and an exclude block 734. The decryption blocks 721, 723, and 725 may perform decryption operations for different computation times. For example, the first decryption block 721 performs a decryption operation for one clock cycle, the second decryption block 723 performs a decryption operation for two clock cycles, and the Nth decryption block 725 performs an N clock The decoding operation of the cycle can be performed. The switch 722 outputs the data path of the encrypted data ENC-DATA in response to the switching signal SWS to one of the decryption blocks 721, 723 and 725 or a block of the next stage (for example, 730). In one embodiment, the variable pipeline 710 may further include a switch 728 disposed at the front end of the fetch block 730. The switch 728 may couple one of the plurality of data paths to the fetch block 730 in response to the switching signal SWSO.

The pipeline control unit 780 outputs the switching signal SWS so that the encrypted data ENC-DATA is applied to the decryption block having the computation time corresponding to the clock cycle number 774 among the decryption blocks 721, 723, Lt; / RTI >

For example, when the number of clock cycles 774 corresponding to the address range 772 to which the address ADDR of the encrypted data ENC-DATA belongs is 1, the pipeline control unit 780 outputs the encrypted data ENC -DATA) may be connected to the first decoding block 721 which performs a decoding operation of one clock cycle. Accordingly, the decryption operation of one clock cycle is performed by the first decryption block 721 on the encrypted data (ENC-DATA), and the original data can be generated. Meanwhile, the first decryption block 721 may perform the decryption operation using the encryption key (KEY) provided from the pipeline controller 780. In another example, when the number of clock cycles 774 is 2, the pipeline control unit 780 outputs a second decryption block 723 in which the data path of the encrypted data (ENC-DATA) performs a decryption operation of two clock cycles, The switching signal SWS can be generated. Accordingly, the decryption operation of two clock cycles is performed by the second decryption block 723 on the encrypted data (ENC-DATA), so that the original data can be generated. Meanwhile, the second decryption block 723 may perform the decryption operation using the encryption key (KEY) provided from the pipeline controller 780.

The fetch block 730 may store the original data in a predetermined register included in the processor 700. [ The decode block 732 decodes the original data and the execution block 734 can execute the decoded original data.

As described above, the processor 700 according to another embodiment of the present invention performs a decoding operation on data in the processor 700, that is, in the plurality of decryption blocks 721, 723, and 725, The original data is not exposed and the data can be safely protected. In addition, the processor 700 according to another embodiment of the present invention performs pipelined decoding of data with fetching, decoding, and / or the like, thereby substantially reducing the performance of the processor 700 and the system including the same . In addition, the processor 700 according to another embodiment of the present invention includes a variable pipeline that adjusts the computation time of the decryption operation according to the security level of the data to be processed, It is possible to perform a decryption operation of a strong decryption algorithm and to perform a quick process on data requiring a low level of security.

8 is a block diagram illustrating a processor in accordance with another embodiment of the present invention.

Referring to FIG. 8, the processor 800 includes a variable pipeline 810 and a security level determination unit 850. The processor 800 of FIG. 8 includes a plurality of decryption blocks 821, 823, and 825 that perform decryption operations of different decryption algorithms on behalf of the variable decryption block 820 shown in FIG. 2, , But may have a similar configuration to the processor 200 of FIG.

The security level determination unit 850 determines the security level of the encrypted data (ENC-DATA) to be processed by the processor 800. [ The security level determination unit 850 may include a security policy storage unit 860 and a pipeline control unit 880. The security policy storage unit 860 may store at least one security policy record 870 for the encrypted data ENC-DATA. As an example, the security policy record 870 may include a range of addresses 872, a number of clock cycles 874, and an encryption key 876, and may indicate the type of decryption / 878). The pipeline control unit 880 receives the address ADDR of the encrypted data ENC-DATA and sends a security policy including the range 872 of the address 872 to which the address ADDR received in the security policy storage unit 860 belongs. The policy record 870 can be searched. The pipeline control unit 880 generates a switching signal SWS for controlling the switch 822 based on the algorithm type 878 and / or the clock cycle number 874 included in the discovered security policy record 770 And provide the encryption key 876 included in the searched security policy record 870 to the decryption blocks 821, 823, and 825 included in the variable pipeline 810.

The variable pipeline 810 includes a plurality of decryption blocks 821, 823 and 825 having different decoding algorithms, a switch 822 disposed at the front end of the decryption blocks 821, 823 and 825, a fetch block 830 ), A decode block 832, and an exclude block 834. The decryption blocks 821, 823, and 825 may perform decryption operations of different decryption algorithms. For example, the first decoding block 821 performs the decoding operation of the first decoding algorithm, the second decoding block 823 performs the decoding operation of the second decoding algorithm, and the Nth decoding block 825 The decoding operation of the Nth decoding algorithm can be performed. The switch 822 responds to the switching signal SWS by sending the data path of the encrypted data ENC-DATA to one of the decryption blocks 821, 823 and 825 or to a block of the next stage (e.g., 830). In one embodiment, the variable pipeline 810 may further include a switch 828 disposed at the front end of the fetch block 830. The switch 828 may couple one of the plurality of data paths to the fetch block 830 in response to the switching signal SWSO.

The pipeline control unit 880 generates the switching signal SWS so that the encrypted data ENC-DATA is applied to the decoding block having the decoding algorithm represented by the algorithm type 878 among the decoding blocks 821, 823 and 825 can do.

For example, if the algorithm type 878 corresponding to the address range 872 to which the address (ADDR) of the encrypted data (ENC-DATA) belongs indicates the first decryption algorithm, And generate a switching signal SWS so that the data path of the data (ENC-DATA) is connected to the first decoding block 821 performing the decoding operation of the first decoding algorithm. Accordingly, the decryption operation of the first decryption algorithm is performed by the first decryption block 821 on the encrypted data (ENC-DATA), and the original data can be generated. Meanwhile, the first decryption block 821 may perform the decryption operation using the encryption key (KEY) provided from the pipeline controller 880. In another example, when the algorithm type 878 indicates a second decryption algorithm, the pipeline control unit 880 determines whether the data path of the encrypted data (ENC-DATA) is a second decryption algorithm And generate the switching signal SWS to be connected to the decryption block 823. [ Accordingly, the decryption operation of the second decryption algorithm is performed by the second decryption block 823 on the encrypted data (ENC-DATA), so that the original data can be generated. Meanwhile, the second decryption block 823 can perform the decryption operation using the encryption key (KEY) provided from the pipeline controller 880. [

8 illustrates an example in which types of decryption algorithms correspond to decryption blocks 1: 1. However, according to an embodiment, the variable pipeline 810 includes two or more decryption blocks for performing one kind of decryption algorithm , And the two or more decoding blocks may have different computation times. In this case, the pipeline control unit 880 can generate the switching signal SWS so that the decryption operation is performed by the appropriate decryption block based on the algorithm type 878 and the clock cycle number 874.

The fetch block 830 may store the original data in a predetermined register included in the processor 800. [ Decode block 832 may decode the original data, and the execution block 834 may execute the decoded original data.

As described above, the processor 800 according to another embodiment of the present invention performs a decoding operation on data in the processor 800, i.e., a plurality of decryption blocks 821, 823, and 825, The original data is not exposed and the data can be safely protected. In addition, the processor 800 according to another embodiment of the present invention performs pipelined decoding of data with fetching, decoding, and / or the like, thereby substantially reducing the performance of the processor 800 and the system including the same . In addition, the processor 800 according to another embodiment of the present invention includes a variable pipeline that adjusts the computation time of the decryption operation according to the security level of the data to be processed, It is possible to perform a decryption operation of a strong decryption algorithm and to perform a quick process on data requiring a low level of security.

FIG. 9 is a block diagram illustrating a processor according to another embodiment of the present invention, and FIG. 10 is a timing diagram illustrating an execution cycle of the processor of FIG.

Referring to FIG. 9, the processor 900 includes a variable pipeline 910 and a security level determination unit 950. The processor 900 of FIG. 9 may have a similar configuration to the processor 200 of FIG. 2, in addition to further including a variable encryption block 940.

The security level determination unit 950 determines the security level of the encrypted data (ENC-DATA) to be processed by the processor 900 and controls the variable level determination unit 950 to perform the decryption operation and the encryption operation while the clock level corresponding to the determined security level is high The variable decryption block 920 and the variable encryption block 940 included in the pipeline 910 can be controlled.

The variable pipeline 910 may include a variable decryption block 920, a fetch block 930, a decode block 932, an exclude block 934, and a variable encryption block 940. The variable decryption block 920 may decrypt the encrypted data ENC_DATA input to the processor 900 during a clock cycle corresponding to its security level to generate original data. The fetch block 930 may store the original data in a register and the decode block 932 may decode the raw data stored in the register and the execution block 934 may execute the decoded original data .

When the processing result of the original data is to be stored in the external memory, the variable encryption block 940 encrypts the processing result of the original data during a clock cycle corresponding to the security level determined by the security level determination unit 950 And output the encrypted result data (ENC-RES-DATA) to the outside. In one embodiment, the security level determination unit 950 can control the variable encryption block 940 based on the security level of the encrypted data (ENC_DATA). In another embodiment, the security level determination unit 950 can control the variable encryption block 940 based on the security level of the encrypted result data (ENC-RES-DATA) to be stored in the external memory. For example, the security level determination unit 950 searches the address range including the address of the external memory where the encrypted result data (ENC-RES-DATA) is to be stored, and sets the number of clock cycles corresponding to the search range And controls the variable cryptographic block 940 to perform the cryptographic operation during the computation time of the number of the read clock cycles.

This variable pipeline 910 can process the encrypted data ENC_DATA in a pipeline manner in parallel. Fig. 10 shows an example of the pipeline processing of the variable pipeline 910. Fig. 10, reference numeral 1010 denotes execution timing for the first encrypted data (ENC-DATA1) having the general security level, reference numeral 1030 denotes execution timing for the second encrypted data (ENC-DATA2) having the general security level 1050 indicates the execution timing for the third encrypted data (ENC-DATA3) having a high security level, and 1070 indicates the execution timing for the fourth encrypted data (ENC-DATA4) having the high security level have.

As shown in FIG. 10, a decryption operation, a fetch operation, a decode operation, an excitation operation and an encryption operation are sequentially performed on each of the encrypted data (ENC-DATA1, ENC-DATA2, ENC-DATA3 and ENC- . In other words, each stage of the variable pipeline 910, that is, the variable decryption block 920, the fetch block 930, the decode block 932, the secret block 934, and the variable encryption block 940, (ENC-DATA1, ENC-DATA2, ENC-DATA3 and ENC-DATA4) in parallel, the performance of the processor 900 and the system including the same can be improved. In addition, since the encryption / decryption operation is performed in a pipelined manner together with the fetch operation, the decode operation, and the execution operation, the operation performance may not be substantially lowered. In addition, the computation time of the encryption / decryption operation can be adjusted according to the security level of the data. Accordingly, the encryption / decryption operation of the encryption / decryption algorithm suitable for the security level of each data can be performed.

As described above, the processor 900 according to another embodiment of the present invention performs a decryption operation and an encryption operation on data in the processor 900, that is, the variable decryption block 920 and the variable encryption block 940 The original data is not exposed to the outside, so that the data can be safely protected. In addition, the processor 900 according to another embodiment of the present invention performs pipelining of data decryption and encryption together with fetch, decode, and execution to improve the performance of the processor 900 and the system including the same It can be hardly lowered. In addition, the processor 900 according to another embodiment of the present invention includes a variable pipeline that adjusts the computation time of the decryption operation and the encryption operation according to the security level of the data to be processed, so that a high level of security is required A strong decryption / encryption algorithm decryption / encryption operation can be performed on the data, and faster processing can be performed on data requiring low level security.

9 shows an example in which the variable ciphering block 940 is disposed at the rear end of the execution block 930. However, the variable ciphering block 940 may be disposed at an arbitrary position on the variable pipeline. Also, according to an embodiment, the processor 900 may include a plurality of cryptographic blocks in series, similar to FIG. 6, with or instead of the variable cryptographic block 940, Or may include a plurality of cryptographic blocks of different encryption algorithms, similar to Fig.

11 is a block diagram illustrating a system-on-chip in accordance with embodiments of the present invention.

Referring to FIG. 11, the system-on-chip 1100 may include a processor 1110 and a memory unit 1120. According to an embodiment, the system-on-chip 1100 may further include an input / output interface 1130, an encryption unit 1140, a power control unit 1150, and a bus 1160. According to an embodiment, the system-on-chip 1100 may be a smart card chip, a Trusted Platform Module (TPM) chip, or an application processor (AP).

Processor 1110 may control the overall operation of system-on-chip 1100. For example, the processor 1110 may control operations of the memory unit 1120, the input / output interface 1130, the encryption unit 1140, the power control unit 1150, and the like. The processor 1110 may also fetch the encrypted data (e.g., encrypted program data or encrypted generic data) and process the fetched data. The processor 1110 may be a central processing unit (CPU) or a microprocessor. The processor 1110 may be coupled to the memory unit 1120 via a bus 1160.

In the memory unit 1120, data may be encrypted and stored. The memory unit 1120 may be a nonvolatile memory such as a volatile memory and / or a read only memory (ROM) 1124 such as a random access memory (RAM) 1122, a flash memory 1126, . ≪ / RTI > The random access memory 1122 may operate as a working memory for the processor 1110. For example, the random access memory 1122 may be implemented as a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like. The boot-only memory 1124 and the flash memory 1126 may store a boot image or may store security data such as a cryptographic key, sensitive data, main code, and / or other general data have.

The input / output interface 1130 is connected to an external device, and the processor 1110 can communicate with the external device via the input / output interface 1130. For example, the input / output interface 1130 may be a Universal Serial Bus (USB), a Multi-Media Card (MMC), a Peripheral Component Interconnect-Express (PCI-E), a Serial Attached SCSI (SAS), a Serial Advanced Technology Attachment ), PATA (Parallel Advanced Technology Attachment), SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE .

The encryption unit 1140 can perform an encryption / decryption operation in response to an external encryption / decryption request through the input / output interface 1130. The encryption unit 1140 encrypts and decrypts various algorithms including an AES (Advanced Encryption Standard) unit 1142, a DES (Data Encryption Standard) unit 1144, an RSA (Rivest Shamir Adleman) Can be performed. The power control unit 1150 can control and manage the power of the system-on-chip 1100.

Meanwhile, data may be encrypted and stored in the memory unit 1120. The processor 1110 may receive the encrypted data from the memory unit 1120. [ In addition, the processor 1110 may determine the security level of the encrypted data and perform a decryption operation on the encrypted data during a clock cycle corresponding to the determined security level to generate original data, Lt; / RTI > The processor 1110 encrypts / decrypts the data in the processor 100, thereby protecting the data from being exposed to the outside. In addition, the processor 1110 may perform encryption / decryption of data in the pipeline of the processor 1110, thereby substantially reducing the performance of the processor 1110 and the system 1100 including the same. In addition, the processor 1110 includes a variable pipeline that adjusts the computation time of the encryption / decryption operation according to the security level of the data to be processed, thereby providing a strong encryption / decryption algorithm encryption / decryption algorithm for data requiring a high level of security, It is possible to perform a decryption operation and to perform a quick process on data requiring a low level of security.

12 and 13 are views showing examples in which a system-on-chip according to embodiments of the present invention is employed in a smart card.

12 is an exploded perspective view illustrating a smart card 1200 including a system-on-a-chip 1100 according to embodiments of the present invention. 12, the smart card 1200 includes a system-on-a-chip 1100, first and second base members 1210 and 1220, a contact portion 1230, and an antenna 1240.

The first and second base members 1210 and 1220 may be formed of plastic or similar material. The system-on-chip 1100 is formed between the first and second base members 1210 and 1220. The system-on-chip 1100 may be a smart card chip included in the smart card 1200. The first base member 1210 is formed with a contact portion 1230 including a plurality of pins. The contact portion 1230 may be an interface for directly contacting and exchanging data with an external device such as a card terminal. For example, the contacts 1230 may conform to standards such as the International Standardization Organization (ISO) 7816. The antenna 1240 may be formed as a coil between the first and second base members 1210 and 1220. The antenna 1240 can transmit and receive radio signals of a predetermined frequency to an external device. For example, the antenna 1240 may conform to standards such as ISO 14443.

The processor included in the system-on-chip 1100 performs an encryption / decryption operation on data in the processor, thereby protecting the data from being exposed to the outside of the processor. In addition, the processor included in the system-on-chip 1100 may perform encryption / decryption of data in the processor's pipeline, thereby substantially reducing the performance of the processor and the system 1100 including the same. In addition, the processor included in the system-on-chip 1100 includes a variable pipeline that adjusts the computation time of the encryption / decryption operation according to the security level of the data to be processed, The encryption / decryption operation of the strong encryption / decryption algorithm can be performed, and the processing can be performed faster for data requiring low level security.

12 shows an example of a combi card (i.e., a dual interface card) including a contact 1230 and an antenna 1240, however, according to an embodiment, the smart card 1200 may be any one of a contact interface or a non- . ≪ / RTI > In another embodiment, the smart card 1200 may be a hybrid card including a contact integrated circuit and a non-contact integrated circuit.

13, a card 1350 including a system-on-chip according to embodiments of the present invention includes a subscriber identity module (SIM) card (not shown) removably mounted to the portable device 1300 1350).

On the other hand, according to the embodiment, the card including the system-on-chip according to the embodiments of the present invention may be a Smart Card, a MultiMedia Card (MMC), an embedded MultiMedia Card (eMMC ), A hybrid embedded MultiMedia Card (SDM), a Secure Digital (SD) card, a Micro SD card, a Memory Stick, an ID card, a PCMCIA (Personal Computer Memory Card International Association) A USB card, a CF card (Compact Flash Card), and the like.

The portable device 1300 may be a cellular phone, a smart phone, a tablet PC, a laptop computer, a personal digital assistant (PDA), a portable multimedia player such as a portable multimedia player (PMP), a digital camera, a music player, a portable game console, navigation, and the like.

14 is a diagram showing an example in which a system-on-chip according to embodiments of the present invention is employed in a Trusted Platform Module (TPM).

14, a computing system 1400 may include a CPU 1410, a system memory 1430, a chipset 1450, and a Trusted Platform Module (TPM) 1470. According to an embodiment, the computing system 1400 may be a personal computer (PC), a server computer, a workstation, a laptop, a cellular phone, a smart phone, A personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, A music player, a portable game console, navigation, and the like.

The CPU 1410 is mounted on a board such as a motherboard or a mainboard and can execute certain calculations or tasks. The CPU 1410 may include a memory controller that controls the operation of the system memory 1430. The system memory 1430 may store data processed by the CPU 1410. [ Also, the CPU 1410 may be coupled to the chipset 1450. Chipset 1450 may provide an interface to peripheral devices. Chipset 1450 may include an input / output hub and an input / output controller hub as a controller chipset.

Trust platform module 1470 may be mounted on a board such as a motherboard or a mainboard and connected to a chipset (not shown) via a Serial Peripheral Interface (SPI) bus or a Peripheral Component Interconnect Express (PCIe) 1450). Trust platform module 1470 may provide security functions such as data encryption / decryption, hashing, random number generation, encryption key generation, and the like.

Meanwhile, in the trusted platform module 1470, the processor performs an encryption / decryption operation on the data in the processor, so that the original data is not exposed to the outside of the processor, thereby safely protecting the data. In addition, the processor of trusted platform module 1470 may include a variable pipeline 1490 that includes an encryption / decryption stage that performs encryption / decryption operations during adaptively controlled computation times. Accordingly, the processor of the trusted platform module 1470 can perform a strong encryption / decryption operation without substantially degrading operational performance.

15 is a diagram showing an example in which a system-on-chip according to embodiments of the present invention is employed in an application processor (AP).

15, the portable device 1500 includes an application processor 1510, a memory 1520, a user interface 1530, a power supply 1540, a trusted platform module 1550, and a storage device 1560 . According to an embodiment, the portable device 1500 may further include a modem such as a baseband chipset, an image processor, and the like. Meanwhile, according to the embodiment, the portable device 1500 may be a cellular phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera Such as a digital camera, a music player, a portable game console, a navigation system, a laptop computer, and the like.

The application processor 1510 can control the overall operation of the portable device 1500. [ In one embodiment, application processor 1510 may execute applications that provide Internet browsers, games, animations, and the like. According to an embodiment, the application processor 1510 may include a single processor core or a plurality of processor cores (Multi-Core). For example, the processor 910 may include a multi-core such as a dual-core, a quad-core, and a hexa-core.

On the other hand, the application processor 1510 may be implemented as a system-on-chip. The processor included in the system-on-chip performs encryption / decryption operations on data in the processor, thereby protecting the data from being exposed to the outside of the processor. In addition, the processor of the system-on-chip may include a variable pipeline 1515 that includes an encryption / decryption stage for performing encryption / decryption operations during an adaptively controlled computation time. Accordingly, the processor of the system-on-chip can perform a strong encryption / decryption operation with little deterioration in operational performance.

The memory 1520 stores data necessary for the operation of the portable device 1500. For example, the memory 1520 may store a boot image for booting the portable device 1500, and may store data transmitted to and received from the external device. For example, the memory 1520 may be implemented as a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a mobile DRAM, a DDR SDRAM, an LPDDR SDRAM, a GDDR SDRAM, an RDRAM, or an EEPROM Programmable Read-Only Memory, Flash Memory, PRAM, Resistance Random Access Memory (RRAM), Nano Floating Gate Memory (NFGM), Polymer Random Access Memory (PoRAM) Random Access Memory), FRAM (Ferroelectric Random Access Memory), and the like.

The user interface 1530 may include one or more input devices such as a keypad, a touch screen, and / or one or more output devices such as speakers, display devices, and the like. The power supply 1540 can supply the driving power of the portable device 1500.

Trust platform module 1550 may provide security functions such as data encryption / decryption, hashing, random number generation, encryption key generation, and the like. The processor included in trust platform module 1550 may also include a variable pipeline that includes an encryption / decryption stage that performs encryption / decryption operations during adaptively controlled computation times.

The storage device 1560 may include a memory card, a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like. Meanwhile, the storage device 1560 may include a smart card, and the processor of the smart card may also include a variable pipeline that includes an encryption / decryption stage that performs encryption / decryption operations during adaptively controlled computation times. have.

The components of the portable device 1500 can be implemented using various types of packages, for example, package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs) (Plastic In-Line Package), Die in Waffle Pack, Die in Wafer Form, COB (Chip On Board), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP) Thin Quad Flat-Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP) (Multi-Chip Package), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), and the like.

The present invention can be applied to a system-on-chip that includes any processor and processor. For example, the present invention can be applied to a smart card chip, a trusted platform module (TPM) chip, an application processor (AP), and the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. You will understand.

100, 200, 400, 600, 700, 800, 900: Processor
110, 210, 410, 610, 710, 810, 910: variable pipelines
150, 250, 450, 650, 750, 850, 950:
1100: System-on-Chip

Claims (10)

A security level determination unit for determining a security level of encrypted data to be processed by the processor; And
Generating encrypted data by performing a decryption operation on the encrypted data during a clock cycle corresponding to the security level determined by the security level deciding unit to generate original data, A processor including a pipeline. 2. The apparatus of claim 1,
And a variable decryption block for changing an operation time of the decryption operation according to the security level of the encrypted data. 2. The apparatus of claim 1,
A variable decryption block for decrypting the encrypted data input to the processor during the clock cycle corresponding to the security level to generate the original data;
A fetch block for storing the original data in a register;
A decoding block for decoding the original data; And
And an execution block for executing the decrypted original data. 2. The apparatus of claim 1,
A fetch block for storing the encrypted data input to the processor in a register;
A variable decryption block for decrypting the encrypted data stored in the register during the clock cycle corresponding to the security level to generate the original data;
A decoding block for decoding the original data; And
And an execution block for executing the decrypted original data. 2. The apparatus of claim 1,
A plurality of decryption blocks connected in series; And
And a plurality of switches, respectively disposed at the front ends of the decoding blocks, each of the switches selectively connecting the data path to a corresponding decoding block or a block of the next stage among the decoding blocks. 2. The apparatus of claim 1,
A plurality of decryption blocks for performing the decryption operation during different computation times; And
And a switch for connecting the data path to a decryption block having the computation time of the clock cycle corresponding to the security level among the decryption blocks. 2. The apparatus of claim 1,
A plurality of decryption blocks for performing the decryption operation of different decryption algorithms; And
And a switch for connecting the data path to a decryption block of the decryption algorithm corresponding to the security level among the decryption blocks. The processor according to claim 1, wherein the variable pipeline encrypts the processing result of the original data during the clock cycle corresponding to the security level and outputs the encrypted data to the outside. The apparatus of claim 1,
A security policy storage unit for storing an address range for the encrypted data and a number of clock cycles corresponding to the address range; And
Wherein the processor receives the address of the encrypted data to be processed by the processor, reads the number of clock cycles corresponding to the address range to which the received address belongs from the security policy storage, And a pipeline control unit for controlling the variable pipeline to perform the decoding operation during the computation time. A memory unit for storing encrypted data; And
Receives the encrypted data from the memory unit, determines a security level of the encrypted data, decrypts the encrypted data during a clock cycle corresponding to the determined security level, and generates original data And a processor for processing the original data.

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