KR20120005844A - Semiconductor memory device and program method thereof - Google Patents

Abstract

In an embodiment, a semiconductor memory device may include a memory cell array including three bit multi-level cells programmed into first to third logical pages; Page buffers including first to fourth latch circuits for storing data in the 3-bit multi-level cell or reading and storing data stored in the memory cell; And storing two bits of data of one bit of three bits of data to be stored in the three-bit multi-level cell in each of the first and second latches of the page buffer, and using the data stored in the first and second latches. By setting the data of the third and fourth latches, and then programming the 3-bit multi-level cell according to the data stored in the third and fourth latches, and using the read reference voltage during the program verify operation. And a control logic for reading a page, storing the read data in the third latch, and performing program verification according to the data stored in the first to fourth latches.

Description

Semiconductor memory device and method of programming the same

The present invention relates to a semiconductor memory device and a program method thereof.

There is an increasing demand for nonvolatile memory devices that can be electrically programmed and erased and that data can be stored without being erased even when power is not supplied. In order to develop a large-capacity memory device capable of storing a large number of data, high integration technology of memory cells has been developed. A nonvolatile memory device includes a plurality of memory cells connected in series to form a string, and the plurality of strings include a memory cell array.

A string of a semiconductor memory device has a structure in which a plurality of memory cells are connected in series between a bit line and a source line. Due to the string structure, the number of contacts of the bit line and the source line is reduced, and the memory cell can be made smaller to realize a high capacity memory. However, as the size of the memory cell decreases, the access speed is slow because the current of the memory cell is very small.

One memory cell may store data of two or more multi-level forms. That is, by adjusting the amount of charge charged in the floating gate of the memory cell to vary the magnitude of the threshold voltage, it is possible to make a number of threshold voltage levels, and the data represented by the memory cells having the respective threshold voltages can be represented by using several bits of data. have. Such a multi-level cell program method has been widely used because it dramatically increases the capacity of nonvolatile memory cells. In the multi-level cell program method, two or more logical page data are programmed in one physical page, and program verification using a plurality of verification voltages is performed to move a threshold voltage of a memory cell to one of a plurality of threshold voltage distributions.

The programming of the multi-level cell may be performed by repeatedly applying a high program voltage to the gate of the memory cell to increase the threshold voltage of the memory cell and verifying that the threshold voltage of the memory cell reaches a desired level. Is done.

The program operation is performed in units of pages, and the threshold voltage of the memory cell is increased in stages.

That is, the program operation is completed from memory cells having a low target threshold voltage by a program among the memory cells in the page, and the memory cell having a high target threshold voltage by the program is the last program.

To this end, a page buffer circuit is connected to the memory cell, and the program operation is performed by using the latches in the page buffer.

In this case, the number of latches included in the page buffer circuit is determined according to the number of bits that can be stored in the multi-level cell.

In general, four page buffers are required for 2-bit multi-level cells, and five page buffers are required for 3-bit multi-level cells.

In the case of a 3-bit multi-level cell, three latches store three bits of data to be stored in the memory cell. The latches storing the three bits of data distinguish the target voltage to which the corresponding memory cell is to be programmed. And the other two latches are actually needed to program the memory cells.

Therefore, as the number of bits of data that can be stored in the multi-level cell increases, the number of latches of the page buffer also increases, so that the total circuit area of the semiconductor memory device may increase.

An embodiment of the present invention provides a semiconductor memory device and a program method thereof that can reduce the number of latches required for a page buffer by using only four latches when programming a 3-bit multi-level cell.

In a semiconductor memory device according to an embodiment of the present invention,

A memory cell array comprising 3-bit multi-level cells programmed into first to third logical pages; Page buffers including first to fourth latch circuits for storing data in the 3-bit multi-level cell or reading and storing data stored in the memory cell; And storing two bits of data of one bit of three bits of data to be stored in the three-bit multi-level cell in each of the first and second latches of the page buffer, and using the data stored in the first and second latches. By setting the data of the third and fourth latches, and then programming the 3-bit multi-level cell according to the data stored in the third and fourth latches, and using the read reference voltage during the program verify operation. And a control logic for reading a page, storing the read data in the third latch, and performing program verification according to the data stored in the first to fourth latches.

 Program method of a semiconductor memory device according to another embodiment of the present invention,

Data in the first to fourth latches of the page buffer to program the first to third logical pages to program 3-bit multi-level cells whose threshold voltage may be changed to one of the first to eighth threshold voltage distributions. Setting and executing a program according to the data state of the second and third latches; And performing program verification on each of the second to eighth threshold voltage distributions, and performing program verification on each of the threshold voltage distributions, reading the multi-level data using a reference voltage. Storing in the third latch; Precharging bit lines using data stored in the third latch; A first verifying step of applying a first verifying voltage determined according to each threshold voltage distribution to a selected word line to read data and to store the data into the second latch; Precharging bit lines using data stored in the third latch; Transferring data from the second latch to the third latch; And a second verifying step of reading data using the second verifying voltage lower than the first verifying voltage and storing the data in the third latch.

The semiconductor memory device and the program method thereof according to an embodiment of the present invention can reduce the circuit area of the page buffer by reducing the number of latches of the page buffer when programming a 3-bit multi-level cell.

1 shows a semiconductor memory device for explaining the present invention.
FIG. 2 illustrates the page buffer of FIG. 1.
3 illustrates threshold voltage gates of the memory cells of FIG. 1.
4 is a flowchart illustrating a program method according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 shows a semiconductor memory device for explaining the present invention.

Referring to FIG. 1, the semiconductor memory device 100 may include a memory cell array 110, a page buffer group 120, an X decoder 130, a voltage supply circuit 140, an input / output logic 150, and a control logic 160. ).

The memory cell array 100 includes a plurality of memory blocks BK. Each memory block BK includes a plurality of cell strings CS.

Each cell string includes a 0 th to 31 th memory cell C0 to C31 connected in series between a drain select transistor (DST) and a source select transistor (SST).

A gate of the drain select transistor DST is connected to a drain select line DSL, and a gate of the source select transistor SST is connected to a source select line SSL.

The gates of the 0th to 31st memory cells C0 to C31 are connected to the 0th to 31st word lines WL0 to WL31, respectively. The 0th to 31st memory cells are 3-bit multi-level cells.

The drains of the drain select transistors DST are connected to bit lines, respectively. The bit line is divided into an even bit line (BLe) and an odd bit line (BLo).

The source of the source select transistor SST is commonly connected to a common source line SL.

The page buffer group 120 includes a plurality of page buffers 121 that operate for a program or a read operation.

Each page buffer PB is connected to one even bit line BLe and an odd bit line BLO pair.

The input / output logic 150 performs data input / output with the page buffer group 120 and the outside. In the semiconductor memory device 100 according to the embodiment, the input / output logic 150 is connected to an external device (not shown) by eight IOs.

The X decoder 130 includes a plurality of block selection circuits 131. Each block selection circuit 131 is connected to each memory block BK.

In response to the control signal from the control logic 160, the block selection circuit 131 may include the drain select line DSL and the source select line SSL of the connected memory block BK, and the 0 th to 31 rd word lines. WL0 to WL31 may be replaced by a global source select line (GSSL), a global drain select line (GDSL), and zeroth to thirty-first global word lines of the voltage supply circuit 160. Line GWL0 to GWL31).

The voltage supply circuit 140 generates an operating voltage in response to the control signal from the control logic 160 and provides the generated operating voltage to the global lines GSSL, GDSL, GWL0 to GWL31.

The control logic 160 outputs a control signal for controlling the operation of the page buffer group 120, the X decoder 130, the input / output logic 150, and the voltage supply circuit 140 of the semiconductor memory device 100.

The page buffer 121 of the page buffer group 120 is as follows.

FIG. 2 illustrates the page buffer of FIG. 1.

Referring to FIG. 2, the page buffer 121 includes first to twentieth NMOS transistors N1 to N20, a first PMOS transistor P1, and first to fourth latches L1 to L4.

The first NMOS transistor N1 is connected between the bit line BL and the sensing node SO, and the sensing signal PBSENSE is input to the gate of the first NMOS transistor N1.

The first PMOS transistor P1 is connected between the power supply voltage and the sensing node SO and a precharge signal PRECH is input.

The second NMOS transistor N2 is connected between the sensing node SO and the node QC, and the third NMOS transistor N3 is connected between the sensing node SO and the node QC_N.

The first transfer signal TRAN_N is input to the gate of the second NMOS transistor N2, and the second transfer signal TRAN is input to the gate of the third NMOS transistor N3. The first and second transmission signals TRANC_N and TRANC are inverted relative to each other.

The first latch L1 is a cache latch connected between the node QC and the node QC_N. The first latch L1 is a latch that receives data from the data lines IOb and IO.

For this purpose, an eighteenth NMOS transistor N18 is connected between the node QC and the data line IOb, and a nineteenth NMOS transistor N19 is connected between the node QC_N and the data line IO. The Y pass signal PBYPASS is input to the gates of the eighteenth and nineteenth NMOS transistors N18 and N19.

The fourth NMOS transistor N4 is connected between the node QC and the node K, and the fifth NMOS transistor N5 is connected between the node QC_N and the node K. The first reset signal CRST is input to the gate of the fourth NMOS transistor N4, and the first set signal CSET is input to the gate of the fifth NMOS transistor N5. The fourth and fifth NMOS transistors N4 and N5 operate to change data of the first latch L1.

The sixth NMOS transistor N6 is connected between the sensing node SO and the node QM_N. The third transmission signal TRANM is input to the gate of the sixth NMOS transistor N6.

The second latch L2 is a main latch connected between the node QM and the node QM_N. The second latch L2 is used for the program operation.

The seventh NMOS transistor N7 is connected between the node QM and the node K, and the eighth NMOS transistor N8 is connected between the node QM_N and the node K.

The second reset signal MRST is input to the gate of the seventh NMOS transistor N7, and the second set signal MSET is input to the gate of the eighth NMOS transistor N8. The seventh and eighth NMOS transistors N7 and N8 operate to change data of the second latch L2.

The ninth NMOS transistor N9 is connected between the sensing node SO and the node QT_N. The fourth transmission signal TRANT is input to the gate of the ninth NMOS transistor N9.

The third latch L3 is a temp latch connected between the node QT and the node QT_N. The third latch L3 is also used for the program operation.

The tenth NMOS transistor N10 is connected between the node QT and the node K, and the eleventh NMOS transistor N11 is connected between the node QT_N and the node K.

The third reset signal TRST is input to the gate of the tenth NMOS transistor N10, and the third set signal TSET is input to the gate of the eleventh NMOS transistor N11. The tenth and eleventh NMOS transistors N10 and N11 are used for data change of the third latch L3.

The twelfth NMOS transistor N12 and the thirteenth NMOS transistor N13 are connected in series between the sensing node SO and the ground node. The fifth transfer signal FSORST is input to the gate of the twelfth NMOS transistor N12, and the gate of the thirteenth NMOS transistor N13 is connected to the node QF.

The 14th and 15th NMOS transistors N14 and N15 are connected in series between the sensing node SO and the ground node. A sixth transmission signal FSOSET is input to a gate of the fourteenth NMOS transistor N14, and a gate of the fifteenth NMOS transistor N15 is connected to a node QF_N.

The fourth latch L4 is a flag latch connected between the node QF and the node QF_N. The sixteenth NMOS transistor N16 is connected between the node QF and the node K, and the seventeenth NMOS transistor N17 is connected between the node QF_N and the node K. FIG.

The fourth reset signal FRST is input to the gate of the sixteenth NMOS transistor N16, and the fourth set signal FSET is input to the gate of the seventeenth NMOS transistor N17.

The twentieth NMOS transistor N20 is connected between the node K and the ground node, and the gate of the twentieth NMOS transistor N20 is connected to the sensing node SO.

A program operation according to an embodiment of the present invention using the page buffer 121 will be described in detail below.

Meanwhile, the memory cells of the memory cell array 110 of FIG. 1 are 3-bit multi-level cells. Therefore, when the program is executed, the threshold voltage distribution is as follows.

3 illustrates threshold voltage gates of the memory cells of FIG. 1.

Referring to FIG. 3, since the memory cells of the memory cell array 110 of FIG. 1 are 3-bit multi-level cells according to an embodiment of the present disclosure, three logical pages, for example, a Least Significant (LSB) per word line, are used. Bit page, Center Significant Bit (CSB) page, and Most Siginificant Bit (MSB) page.

Referring to FIG. 3, when the LSB page is programmed, the threshold voltage distribution is divided into two 301 and 302. When the CSB pages are programmed, there are four threshold voltage distributions (303 to 306).

Finally, when the program is completed up to the MSB page, the threshold voltage distribution is divided into eight (307 to 308). In the state programmed up to the MSB page, the voltage for verifying data uses the first to seventh verify voltages RD1 to RD7.

If double verifying, first to sixth double verify voltages RD1 'to RD6' are further used as shown in FIG.

In the embodiment of the present invention, in order to program using only four latches, the threshold voltage distributions 305 and 306 are programmed to be higher than the voltage RD8, and the threshold voltage distributions 311 to 314 are also higher than the voltage RD8. To be programmed. The voltage RD8 is higher than the highest voltage of the threshold voltage distribution 310 and lower than the fourth verification voltage RD4.

The first and fourth latches L1 and L4 are programmed to program using the second and third latches L2 and L3 of the page buffer 121 and to distinguish the eight threshold voltage distributions 307 to 314. ).

In general, three latches are required to distinguish the eight threshold voltage distributions 307 to 314. However, in the exemplary embodiment of the present invention, only two latches L1 and L4 are used to store two data states among three-bit data states, and one data state is used by directly reading a memory cell.

To program a 3-bit multi-level cell with only four latches:

4 is a flowchart illustrating a program method according to an exemplary embodiment of the present invention.

Reference is made to FIGS. 2 and 3 when describing FIG. 4. 4 partially illustrates only verifying memory cells included in the threshold voltage distribution 308 of FIG. 3.

For the program, a program command, an address, data to be programmed and a confirmation command are input from the outside (S401).

The data to be programmed is input to the first latch L1 of the page buffer. The 3-bit MLC has 3 bits of data to program. Therefore, the first latch L1 receives the data to be programmed, transfers it to one of the second to fourth latches L2 to L4, and makes the data state before starting the program through the data setting process (S403).

The data setting process of the first to fourth latches L1 to L4 is differently set according to a program algorithm. After determining which data to set, the control signals applied to the page buffer 121 are changed to desired data. Can be set in the state. Therefore, when describing an embodiment of the present invention, a data setting process will be omitted.

When the result of the data setting is shown for eight threshold voltages at once, the first latch L1 becomes '11001100', the second latch L2 becomes '10000000', and the fourth latch L4 becomes '01100110'. Becomes The third latch L3 is not set separately.

When the data setting is completed, the program is applied by applying a program voltage to the word line selected by the input address (S405).

First, the node QT_N of the third latch L3 is set to '1', and then data is read using the voltage RD8 for program verification (S409). At this time, the read data is stored in the third latch L3.

The state of the third latch L3 of the memory cells to be programmed with the eight threshold voltage distributions 307 to 314 is '11110000'.

The bit line is precharged (S411). At this time, the data read in step S409 is precharged according to the data stored in the third latch L3.

In operation S413, the bit line voltage is changed by applying the first verification voltage RD1 to the selected word line.

After changing the bit line voltage, the sensing node SO and the bit line are connected to change the voltage of the sensing node SO according to the bit line voltage (S415).

The voltage of the sensing node SO is changed according to the data states of the second and third latches L2 and L3 (S417). This is to exclude memory cells to be programmed with a threshold voltage distribution other than the threshold voltage distribution 308.

After the voltage of the sensing node is changed, data according to the sensing node voltage is stored in the second latch L2 (S419). Accordingly, the second latch L2 of the page buffer 121 connected to the memory cells having the threshold voltage higher than the first verify voltage RD1 becomes '0' and has a threshold voltage lower than the first verify voltage RD1. The second latch L2 of the page buffer 121 connected to the memory cell becomes '1'.

Next, verification using the first double verify voltage RD1 ′ should be performed. Generally, verification using the first double verifying voltage RD1 'is performed first, but the present invention verifies using the first double verifying voltage RD1' after program verifying using the first verifying voltage RD1. .

In order to program verify using the first double verify voltage RD1 ′, all the bit lines after the verify using the first verify voltage are discharged, and then the bit lines are precharged (S421). At this time, the bit line is precharged according to the data of the third latch L3.

The data of the second latch L2 is copied to the third latch L3 (S423).

After copying data to the third latch L3, the first double verify voltage RD1 ′ is applied to the selected word line to change the voltage of the bit line (S425).

After transferring the bit line voltage to the sensing node SO (S427), the voltage of the sensing node SO is changed using the second and third latches L2 and L3 (S429).

In operation S431, data according to the voltage state of the sensing node SO is stored in the third latch L3.

The operations of steps S409 to S431 change only the verify voltage and the double verify voltage, respectively, and program verify the memory cells to be programmed with the remaining threshold voltage distributions 309 to 314. However, memory cells that are to be programmed with the threshold voltage distribution 314 do not require program verification using the double verify voltage.

After the program verification is completed, the program according to the data state of the second and third latches L2 and L3 is executed.

By the above operation, since the page buffer 121 requiring five latches is programmed and verified with only four latches, the area of the page buffer 121 can be reduced.

In addition, even in 4-bit multi-level cells and 5-bit multi-level cells, the number of latches can be reduced by using a method of reading a memory cell in one data state.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

100 semiconductor device 110 memory cell array
120: page buffer group 130: X decoder
140: voltage supply circuit 150: input / output circuit
160: control logic

Claims (7)

A memory cell array comprising 3-bit multi-level cells programmed into first to third logical pages;
Page buffers including first to fourth latch circuits for storing data in the 3-bit multi-level cell or reading and storing data stored in the memory cell; And
In each of the first and second latches of the page buffer, two bits of data of three bits of data to be stored in the three-bit multi-level cell are stored one bit, and the data stored in the first and second latches is used. After setting the data of the third and fourth latches, the 3-bit multi-level cell is programmed according to the data stored in the third and fourth latches, and a page selected using a read reference voltage during a program verify operation. Reads the data, stores the read data in the third latch, and then executes the control logic to perform program verification according to the data stored in the first to fourth latches.
Semiconductor memory device comprising a. The method of claim 1,
When programming the 3-bit multi-level cells, the threshold voltage distribution when the second logic page is programmed and the threshold voltage distribution when the third logic page is programmed do not overlap the reference voltage. A semiconductor memory device. The method of claim 2,
When the program verification is double verification,
And performing a program verify using a first verify voltage for each of the threshold voltage distributions, and a program verify using a second verify voltage lower than the first verify voltage. Memory device. Data in the first to fourth latches of the page buffer to program the first to third logical pages to program 3-bit multi-level cells whose threshold voltage may be changed to one of the first to eighth threshold voltage distributions. Setting and executing a program according to the data state of the second and third latches; And
Performing program verification for each of the second to eighth threshold voltage distributions,
The program verification for each threshold voltage distribution is
Reading the multi-levels of data using a reference voltage and storing the multi-level data in the third latch;
Precharging bit lines using data stored in the third latch;
A first verifying step of applying a first verifying voltage determined according to each threshold voltage distribution to a selected word line to read data and to store the data into the second latch;
Precharging bit lines using data stored in the third latch;
Transferring data from the second latch to the third latch;
And a second verifying step of reading data using the second verifying voltage lower than the first verifying voltage and storing the data in the third latch. The method of claim 4, wherein
The first verification step,
Applying the first verify voltage to a selected word line to change the voltage of the bit line, and then transferring the voltage of the bit line to a sensing node of the page buffer; And
And changing a voltage of the sensing node according to the data states of the first and fourth latches, and storing data in the third latch according to the changed data state of the sensing node. . The method of claim 4, wherein
The second verification step,
Changing the voltage of the bit line using a second verification voltage lower than the first verification voltage, and transferring the changed voltage of the bit line to the sensing node;
Changing the voltage of the sensing node according to the data states of the second and fourth latches; And
And storing data according to the voltage state of the sensing node in the third latch. The method of claim 4, wherein
The reference voltage is,
The threshold voltage distribution according to the program result of the second logic page and the first to eight threshold voltage distributions according to the program result of the third logic page do not overlap with any threshold voltage distribution. Program method for a semiconductor memory device, characterized in that.

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