KR20100111462A - Flash memory device and method for fabricating the same - Google Patents

Abstract

A charge trapping flash memory device having a structure which can be manufactured by a simplified process and an increased program / erase window, and a method of manufacturing the same are provided. The charge trapping flash memory device of the present invention includes a substrate, an insulating film formed on the substrate, a semiconductor layer formed on the insulating film in the cell region, and select transistors and memory cells disposed on the semiconductor layer.

Description

Flash memory device and method for fabricating the same {Flash memory device and method for fabricating the same}

The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly to a charge trap type flash memory device and a method of manufacturing the same.

In general, semiconductor memory devices used to store data can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, while nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Thus, such as in mobile phone systems, memory cards and other applications for storing music and / or video data, nonvolatile memory devices in situations where power is not always available, often interrupted, or where low power usage is required. Is widely used. A typical example of such a nonvolatile memory device is a flash memory device capable of batch erasing.

Most NAND flash memory devices have a floating gate structure in which a polysilicon film is capped with an inter-poly oxide (IPO). Floating gate type nonvolatile memory devices are excellent in extensibility and have recently been developed to multi-level chips. However, in recent years, as the integration of memory devices using floating gates is rapidly integrated, there is a serious problem of interference or coupling, in which threshold voltages are rapidly changed according to charge states of adjacent cells. . Thus, attempts have been made for a new cell structure to overcome such interference between adjacent cells. Recently, interest in flash memory devices having a charge trapping layer having less interference between cells even though the degree of integration has increased has increased.

1 is a cross-sectional view illustrating an example of a flash memory device having a charge trap layer.

A tunneling layer 110 made of an oxide film is formed on a substrate 100 such as a silicon substrate. The impurity regions 102 such as the source / drain are disposed in the substrate 100 so as to be spaced apart from each other by a predetermined interval, and the channel region 104 is disposed therebetween. A silicon nitride film is formed as the charge trap layer 120 on the tunneling layer 110, and an insulating film as the blocking layer 130 and a control gate electrode 140 are sequentially disposed thereon.

When the control gate electrode 140 is positively charged and an appropriate bias is applied to the impurity region 102, hot electrons from the substrate 100 are directed to a trap site in the charge trap layer 120. Trapped. This is the operation of writing to or programming a memory cell. On the other hand, when the control gate electrode 140 is negatively charged and an appropriate bias is applied to the impurity region 102, holes from the substrate are also trapped in the trap site in the charge trap layer 120. Holes trapped in the charge trap layer recombine with the extra electrons already in the trap site, which is the erase operation of the programmed memory cell.

On the other hand, the technology development of NAND flash memory devices is proceeding to the development of devices that are smaller in size and larger in capacity than other semiconductor memory devices. In order to construct a small size and high capacity device, a charge trap type device is advantageous and is considered as one of the next generation NAND flash memory devices. In particular, in order to form a device isolation layer and a gate structure, it is advantageous to have a small stack structure, but since the charge trap device traps electrons in the nitride film, the stack height is smaller than the polysilicon floating gate used in the floating gate device. have. In the development of such a charge trapping flash memory, there is a need for the development of a charge trapping device and a method of manufacturing the same, which can enlarge a program / erase window without being more complicated than a conventional process. to be.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a charge trapping flash memory device having a structure which can be manufactured by a simplified process and has an increased program / erase window.

Another object of the present invention is to provide a method for manufacturing a charge trap type flash memory device that can simplify the process.

In order to achieve the above technical problem, the charge trap type flash memory device includes a substrate; An insulating film formed on the substrate; A semiconductor layer formed on the insulating film in the cell region; And select transistors and memory cells disposed on the semiconductor layer.

The semiconductor layer may be formed of a polysilicon film doped with N-type impurities at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3.

The semiconductor layer may have a structure in which a first polysilicon film doped with P-type impurities and a second polysilicon film doped with N-type impurities are sequentially stacked. In this case, the first or second polysilicon film may be doped at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3.

The memory cell may include a tunneling layer, a charge trap layer, a blocking layer, and a control gate electrode sequentially stacked on the semiconductor layer.

The selection transistor may be a MOS transistor having a gate insulating layer stacked on the semiconductor layer and a gate electrode disposed on the gate insulating layer.

According to an aspect of the present invention, there is provided a method of manufacturing a charge trap type flash memory device, including sequentially forming a first insulating film and a semiconductor layer on a substrate, and a tunneling layer and a charge trap layer of a memory cell on the semiconductor layer. Forming a second insulating film to be used as a gate insulating film of the selection transistor and a blocking layer of the memory cell, and forming a gate conductive film on the second insulating film, on the resultant product of the tunneling layer and the charge trap layer. And patterning the gate conductive layer, the second insulating layer, the charge trap layer, and the tunneling layer to form a gate stack of the selection transistor and the memory cell.

The semiconductor layer may be formed of a polysilicon film doped with N-type impurities at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3.

The semiconductor layer can be formed to a thickness of 100 to 600 kPa.

The semiconductor layer may be formed by stacking a first polysilicon film doped with P-type impurities and a second polysilicon film doped with N-type impurities.

The first or second polysilicon film is doped at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3 and may be formed to a thickness of 50 to 400 GPa.

After forming the first insulating film and the semiconductor layer on the substrate, the method may further include forming a device isolation film defining a device isolation region in the semiconductor layer.

Defining an isolation region of the semiconductor layer may include etching the semiconductor layer in an inactive region, filling a region in which the semiconductor layer is etched with an insulating film, and planarizing the insulating film. have.

Forming a tunneling layer and a charge trap layer of a memory cell on the semiconductor layer may include forming a tunneling layer and a charge trap layer on the semiconductor layer, and the tunneling layer and the charge trap in a region where a select transistor is to be formed. Removing the layer.

The gate conductive layer may be formed of a polysilicon layer or a metal doped with a P-type dopant having a large work function.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

2 to 6 are cross-sectional views illustrating a method of manufacturing a charge trap type flash memory device according to an embodiment of the present invention.

Referring to FIG. 2, an insulating film 210, such as a high density plasma (HDP) oxide film, is formed on the semiconductor substrate 200, and then a semiconductor layer 220 is formed on the insulating film 210. The insulating layer 210 is for electrically separating the semiconductor substrate 200 and the semiconductor layer 220, and is formed to a thickness such that the semiconductor substrate 200 and the semiconductor layer 220 do not conduct with each other. The semiconductor layer 220 serves as a well in which a channel is formed in a charge trap type flash memory device. When the doping concentration is too high, an electric current is large and an off characteristic does not appear. It may be formed of a polysilicon film doped at a concentration of about 10 ¹⁴ ions / cm 3 to 1 10 ¹⁸ ions / cm 3. In addition, the semiconductor layer 220 may be thin because the on / off characteristics of the cell are not easily seen when it is thick. do. In other words, the thickness must be determined so that it can be conducted through each word line. This may vary depending on a bias condition. In a general bias condition, the thickness of the semiconductor layer 220 may be determined within a range of 100 to 600 GHz.

Referring to FIG. 3, the semiconductor layer 220 of the inactive region is etched, and then the etched region is filled with an insulating film (not shown) and planarized to limit the active region. In order to limit the active area, the semiconductor layer 220 may be etched to have a thickness, which is advantageous in terms of etching thickness, compared to a method of etching a semiconductor substrate and filling it with an insulating layer to form a trench isolation layer. The buried margin for filling the region with the insulating film can also be increased. Next, the tunneling layer 230 and the charge trap layer 240 are formed on the semiconductor layer 220 where the active region is limited. The tunneling layer 230 may be formed of, for example, an oxide film. The charge trap layer 240 may be a stoichiometric silicon nitride (Si ₃ N ₄ ) film, a silicon-rich silicon nitride (Si _x N _y ) film, or a stokiometric silicon nitride (Si ₃ N ₄₎ ) And a silicon-rich silicon nitride (Si _x N _y ) film may be formed in a stacked structure. The tunneling layer 230 is formed to a thickness of about 1 to 4 nm, and the charge trap layer 240 is formed to a thickness of about 3 to 12 nm.

Referring to FIG. 4, a photoresist pattern 250 defining a region where a selection transistor is to be formed is formed on the charge trap layer 240. The charge trap layer 240 and the tunneling layer 230 are sequentially etched using the photoresist pattern 250 as a mask to remove the charge trap layer and the tunneling layer in the region where the selection transistor is to be formed. When the charge trap layer and the tunneling layer remain in the selection transistor region, a hot hole that contributes to erasure in the erase operation after completion of the device has an electric field between the gate of the selection transistor and the polysilicon layer 220. This is because the phenomenon of tunneling and programming to the charge trap layer in the selection transistor region occurs. In order to prevent this phenomenon, the tunneling layer and the charge trap layer of the selection transistor region are removed to form a MOS transistor.

Referring to FIG. 5, for example, an oxide film 260 is formed on the resultant. The oxide layer 260 is used as a blocking layer of a memory cell and a gate insulating layer of a selection transistor. The blocking layer prevents charge trapped in the charge trap layer 240 from moving to the control gate. The oxide film 260 may be formed of a high-k material having a high dielectric constant in addition to the silicon oxide film. High-k materials include aluminum oxide (Al ₂ O ₃ ) film, hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), radium oxide (La ₂ O ₅ ), barium zirconium oxide (BaZrO ₃ ), tantalum Oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), gadolinium oxide (Gd ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), and the like.

Next, a gate conductive film 270 is formed on the resultant product on which the oxide film 260 is formed. The gate conductive layer 270 may be formed of a polysilicon layer doped with an N-type or a P-type having a large work function, and in some cases, titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W) It may be formed of a metal film such as.

The gate conductive layer 270 becomes a gate of a selection transistor and a control gate electrode of a memory cell. When the gate of the selection transistor is P-type, the conductive channel of the semiconductor layer 220 serving as the well is N-type, so that a surface channel is formed. When the gate of the selection transistor is N-type, a buried channel is formed. Is formed. Therefore, after the gate conductive layer 270 is formed of an undoped polysilicon layer, the gate conductive layer 270 may be doped to a desired conductivity type through a mask process and ion implantation according to the conductivity type of the selection transistor and the memory cell. Can be.

Referring to FIG. 6, the gate conductive layer and the oxide layer are patterned to form a gate electrode 270a and a gate insulating layer 260a of a selection transistor, and a control gate electrode 270b and a blocking layer 260b of a memory cell, respectively. do. Subsequently, a predetermined impurity ion is implanted and activated into the polysilicon layer 220 to form a source / drain 280.

The charge trapping device of the present invention manufactured as described above is erased by hot holes instead of tunneling by general back bias. That is, hot holes are generated by applying an appropriate bias between the gate and the source / drain of the select transistor, and the generated hot holes are coupled with the electrons trapped in the charge trap layer while moving through the bit line between the source and the drain. Erase is achieved. To this end, first, a negative bias of 0 to -10V is applied to the gate 270a of the select transistor, and a bias of 0 to 10V is applied to the source / drain. An inversion layer is formed by a negative bias applied to the gate 270a of the selection transistor, and the semiconductor layer 220 is formed by a positive bias applied to the source / drain 280. The electron-hole pairs (EHPs) formed in the depletion region of) are broken and hot holes are generated. At this time, the generated hot hole moves in the source direction and is coupled with electrons programmed in the charge trap layer 240 of the memory cell, thereby erasing data programmed in the memory cell.

7 is a cross-sectional view illustrating a method of manufacturing a charge trap type flash memory device according to another embodiment of the present invention. The same reference numerals as in the first embodiment denote the same parts.

Referring to FIG. 7, the semiconductor layer 220 serving as a well in which the channel of the flash memory device is formed is formed in two layers. Specifically, after the insulating film 210 is formed on the substrate 200 to electrically insulate the semiconductor layer and the substrate, the first polysilicon film 221 and the second conductive layer having different conductivity types are formed on the insulating film 210. The polysilicon layer 222 is sequentially stacked to form a semiconductor layer 220. The first polysilicon film 221 is formed of a polysilicon film doped with P-type impurities, and the second polysilicon film 222 is formed of a polysilicon film doped with N-type impurities. The first polysilicon film 221 and the second polysilicon film 222 are each formed to a thickness of about 50 to 400 kPa, and the doping concentration is about 1x10 ¹⁴ ions / cm 3 to 1x10 ¹⁸ ions / cm 3, respectively. . The other manufacturing process is performed in a similar manner to the first embodiment shown in Figs.

When the semiconductor layer 220 in which the channel of the flash memory device is formed is formed by stacking polysilicon films having different conductivity types, the diffusion length of the hot holes may be increased during the erase operation. That is, when the semiconductor layer is formed by stacking the P-polysilicon film 221 and the N-polysilicon film 222 into two layers, the portion of the N-polysilicon film 222 is formed by the P-polysilicon film 221. Since depletion due to the junction has already occurred, the entire N-polysilicon film 222 can be fully depleted even with a relatively small gate bias during the erase operation. In addition, since the hole generated by the GIDL in the select transistor is less likely to recombine with the electrons in the N-polysilicon layer 222, the holes are recombined with the electrons trapped in the charge trap layer 240 of the memory cell. Therefore, the erase operation becomes easy. In addition, when the gate bias is increased, when the electron-hole pair is broken in the depleted portion between the N-polysilicon film 222 and the P-polysilicon film 221, holes generated at this time are trapped in the charge trap layer. Recombination with the electrons is advantageous in terms of erasure.

According to the above-described charge trap type flash memory device and a method of manufacturing the same, a semiconductor layer isolated with an insulating film is formed on a substrate, and a memory cell including a charge trap layer is formed on the semiconductor layer. Accordingly, the memory device may be manufactured by a simpler and easier process, and the program / erase window may be increased by applying an erase method by hot holes.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 is a cross-sectional view illustrating an example of a flash memory device having a charge trap layer.

2 to 6 are cross-sectional views illustrating a method of manufacturing a charge trap type flash memory device according to an embodiment of the present invention.

7 is a cross-sectional view illustrating a method of manufacturing a charge trap type flash memory device according to another embodiment of the present invention.

Claims (16)

Board; An insulating film formed on the substrate; A semiconductor layer formed on the insulating film in the cell region; And And a select transistor and memory cells disposed on the semiconductor layer. The method of claim 1, And the semiconductor layer is made of a polysilicon film doped with N-type impurities at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3. The method of claim 1, And the semiconductor layer comprises a first polysilicon film doped with P-type impurities and a second polysilicon film doped with N-type impurities in that order. The method of claim 3, And the first or second polysilicon film is doped at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3. The method of claim 1, And the memory cell includes a tunneling layer, a charge trap layer, a blocking layer, and a control gate electrode sequentially stacked on the semiconductor layer. The method of claim 1, The selection transistor includes a gate insulating layer stacked on the semiconductor layer, and And a MOS transistor having a gate electrode disposed on the gate insulating film. Sequentially forming a first insulating film and a semiconductor layer on the substrate; Forming a tunneling layer and a charge trap layer of a memory cell on the semiconductor layer; Forming a second insulating film to be used as a gate insulating film of a selection transistor and a blocking layer of a memory cell on a resultant product of the tunneling layer and the charge trap layer; Forming a gate conductive film on the second insulating film; And Patterning the gate conductive layer, the second insulating layer, the charge trap layer, and the tunneling layer to form a gate stack of a selection transistor and a memory cell. The method of claim 7, wherein And the semiconductor layer is formed of a polysilicon film doped with an N-type impurity at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3. The method of claim 8, And the semiconductor layer is formed to a thickness of 100 to 600 GHz. The method of claim 7, wherein And the semiconductor layer is formed by laminating a first polysilicon film doped with P-type impurities and a second polysilicon film doped with N-type impurities. The method of claim 10, Wherein the first or second polysilicon film is doped at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3. The method of claim 10, And the first or second polysilicon film is formed to a thickness of 50 to 400 GPa. The method of claim 7, wherein After forming a first insulating film and a semiconductor layer on the substrate, And forming a device isolation film defining a device isolation region in the semiconductor layer. The method of claim 13, Forming the device isolation film, Etching the semiconductor layer in the inactive region; Filling a region in which the semiconductor layer is etched with an insulating film, and Planarizing the insulating film to form an isolation layer. The method of claim 7, wherein Forming the tunneling layer and the charge trap layer of the memory cell on the semiconductor layer, Forming a tunneling layer and a charge trap layer on the semiconductor layer; Removing the tunneling layer and the charge trap layer in the region where the select transistor is to be formed. The method of claim 7, wherein And the gate conductive film is formed of a polysilicon film or a metal doped with a P-type dopant having a large work function.

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