KR20090037277A - Cross point memory array - Google Patents

Abstract

A cross point memory array is provided to minimize a voltage drop by including an electrode structure having a multilayer structure. A first electrode(21) has a double layer structure of a first conductive layer(21a) and a second conductive layer(21b). A plurality of first laminate structures(S1) is formed on a top of the second conductive layer. A second electrode(25) intersects with the first electrode, and is formed on a top of the first laminate structure. A current(C1) supplied to a first memory resistor(22) of the first laminate structure is mainly delivered through the first conductive layer. The first electrode minimizes a voltage drop by a double layer structure laminated of the first conductive layer and the second conductive layer.

Description

Cross point memory array

The present invention relates to a memory device, and more particularly to a cross point resistive memory array.

The semiconductor memory array includes a number of unit memory cells that are circuitry connected. DRAM (Dynamic Random Access Memory), a typical semiconductor memory device, is composed of one switch and one capacitor, and has the advantages of high integration and fast operation speed. However, DRAM is a nonvolatile memory device, which loses all stored data after the power is turned off. In contrast, nonvolatile memories can retain their stored data even after the power is turned off. A flash memory is a typical nonvolatile memory device. However, the flash memory has a disadvantage of low integration and slow operation speed compared to DRAM.

Nonvolatile memory devices include magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), and resistance random access memory (RRAM). Here, the RRAM (resistance random access memory) is mainly using a variable resistance characteristic of the transition metal oxide, that is, a characteristic in which the resistance value changes depending on the state.

A metal layer formed of a single metal is used as an electrode of a resistive memory element, and a noble metal layer such as Pt is usually used.

The present invention provides a cross point resistive memory array capable of suppressing or minimizing a voltage drop problem by including an electrode structure having a multilayer structure.

An embodiment of the present invention includes a plurality of first electrode lines formed in parallel to each other; A plurality of second electrode lines formed to cross the first electrode lines and parallel to each other; And a first memory resistor formed at an intersection point of the first electrode line and the second electrode line, wherein at least one of the first electrode line and the second electrode line includes a first conductive layer and a noble metal. Provided is a cross point memory array having a multilayer structure with two conductive layers.

The resistivity of the first conductive layer may be lower than the resistivity of the second conductive layer.

The first conductive layer may be formed of any one of Al, Mo, Cu, and Ag.

The second conductive layer may be a layer formed of the noble metal or an alloy layer including the noble metal.

The precious metal may be any one of Pt, Au, Pd, Ir, and Ag.

The second conductive layer may be formed on the first conductive layer, or the first conductive layer may be formed on the second conductive layer.

The second conductive layer may be a line pattern.

The second conductive layer may be a dot pattern provided at the intersection.

A first switch structure may be further provided at the intersection of the first electrode line and the second electrode line to control the flow of current to the first memory resistor.

A first intermediate electrode may be further provided between the first memory resistor and the first switch structure.

The first memory resistor, the first intermediate electrode, the first switching structure, and the second electrode line may be sequentially provided on the first electrode line.

The first switching structure, the first intermediate electrode, the first memory resistor, and the second electrode line may be sequentially provided on the first electrode line.

The first switch structure may be any one of a diode, a threshold switching element, and a varistor.

The diode may be an oxide diode.

The first memory resistor is Ni oxide, Cu oxide, Ti oxide, Co oxide, Hf oxide, Zr oxide, Zn oxide, W oxide, Nb oxide, TiNi oxide, LiNi oxide, Al oxide, InZn oxide, V oxide, SrZr oxide It may include at least one of, SrTi oxide, Cr oxide, Fe oxide or Ta oxide.

A memory array according to an embodiment of the present invention is formed to cross the second electrode line, a plurality of third electrode lines parallel to each other; And a second memory resistor provided at an intersection point of the second electrode line and the third electrode line, wherein the third electrode line includes the first conductive layer and the second conductive layer. It may have a structure.

A second switch structure may be further provided at the intersection of the second electrode line and the third electrode line to control the flow of current to the second memory resistor.

A second intermediate electrode may be further provided between the second memory resistor and the second switch structure.

The second memory resistor, the second intermediate electrode, the second switching structure, and the third electrode line may be sequentially provided on the second electrode line.

The second switching structure, the second intermediate electrode, the second memory resistor, and the third electrode line may be sequentially provided on the second electrode line.

The second switch structure may be any one of a diode, a threshold switching element, and a varistor.

The diode may be an oxide diode.

The cross point memory array may be a multilayer cross point memory device having a 1D (diode) -1R (resistor) cell structure.

The first and / or second memory resistors may include elements reversibly converted from a high resistance state to a low resistance state or from a low resistance state to a high resistance state.

The first and / or second memory resistors may include elements that are irreversibly converted from a high resistance state to a low resistance state.

Hereinafter, a memory array according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the thicknesses and widths of the layers or regions shown in each drawing are exaggerated for clarity. In an embodiment of the present invention, the electrode in contact with the memory resistor or the switch structure is formed in a multilayer structure of a noble metal layer and a metal layer having a lower specific resistance than the noble metal layer. That is, in a resistive memory device including a memory resistor, at least one of the upper and lower electrodes may include a resistive memory device including a precious metal layer and a metal layer having a lower specific resistance than the precious metal layer, and a cross point memory array including the same.

1A and 1B illustrate a unit device of a memory array according to an embodiment of the present invention. The unit device of the memory array according to the embodiment of the present invention may basically have a 1S (switch) -1R (resistor) structure, preferably a 1D (diode) -1R (resistor) structure.

Referring to FIG. 1A, the memory resistor 22, the switch structure 24, and the second electrode 25 may be sequentially provided on one surface of the first electrode 21. An intermediate electrode 23 may be further provided between the memory resistor 22 and the switch structure 24. The first electrode 21 is formed between the first conductive layer 21a and the first conductive layer 21a and the memory resistor 22 formed of a metal having a low resistivity, and includes a second noble metal. It can be formed in a multilayer structure including the conductive layer 21b. The specific resistance of the first conductive layer 21a may be lower than that of the second conductive layer 21b, and the material of the first conductive layer 21a may be cheaper than the material of the second conductive layer 21b. In some cases, the first conductive layer 21a may also be a kind of noble metal, but in this case, the specific resistance of the first conductive layer 21a is lower than that of the second conductive layer 21b, and the first conductive layer is The material of 21a may be less expensive than the material of the second conductive layer 21b. The second electrode 25 may also have a multilayer structure including a noble metal conductive layer and a metal layer having a lower specific resistance than the noble metal conductive layer.

Referring to FIG. 1B, the memory resistor 22, the switch structure 24, and the second electrode 25 are sequentially provided on one surface of the first electrode 21. An intermediate electrode 23 may be further provided between the memory resistor 22 and the switch structure 24. The second electrode 25 is formed on the switch structure 24 and includes a third conductive layer 25a including a noble metal and a fourth metal including a lower resistivity than the precious metal of the third conductive layer 25a. It may be a multi-layer structure having a conductive layer 25b. That is, the second electrode 25 may have an inverse structure of the first electrode 21 of FIG. 1A. However, in some cases, the second electrode 25 may have the same stacked structure as the first electrode 21 of FIG. 1A. In addition, the first electrode 21 of FIG. 1B may have the same stacked structure as the first electrode 21 of FIG. 1A.

As described above, in the memory device according to the embodiment of the present invention, at least one of the first electrode 21 and the second electrode 25 in contact with the memory resistor 22 or the switch structure 24 has a multilayer structure. It can be formed as.

Hereinafter, materials for forming each layer of the memory device according to the embodiment of the present invention shown in FIGS. 1A and 1B will be described.

The second conductive layer 21b and the third conductive layer 25a are preferably formed of a material having a high work function. For example, the second conductive layer 21b and the third conductive layer 25a may be formed of a noble metal such as Pt, Au, Pd, Ir, or Ag. The first conductive layer 21a and the fourth conductive layer 25b are preferably formed of a material having a lower specific resistance than the material of forming the second conductive layer 21b and the third conductive layer 25a. For example, the first conductive layer 21a and the fourth conductive layer 25b may be formed of a material having a specific resistance value of 9 × 10 ⁻⁸ Ω · m or less, more specifically, Al, Mo, Cu, or Ag. Can be. Such a material is not only low in resistivity but also relatively inexpensive, and thus can serve to prevent voltage drop, and is very economically advantageous. Ag is a kind of precious metal, but has a low specific resistance and is inexpensive among precious metals. Therefore, when a precious metal having a higher resistivity and higher cost than Ag is used as the material of the second conductive layer 21b or the third conductive layer 25a, Ag is used as the first conductive layer 21a or the fourth conductive layer 25b. Can be used.

The intermediate electrode 23 electrically connects the memory resistor 22 and the switch structure 24. Without the intermediate electrode 23, the switch structure 24 acts like a resistor, which may cause a problem in device operation. . In more detail, in the case where the switch structure 24 is a diode, when the memory resistor 22 is set without the intermediate electrode 23, the switch structure 24 may be damaged to lose rectification characteristics. The intermediate electrode 23 may be formed of an electrode material used for a semiconductor device. For example, Al, Hf, Zr, Zn, W, Co, Au, Ag, Pd, Pt, Ru, Ir, Ti, or a conductive metal oxide may be used. However, the present invention is not limited thereto, and in some cases, the intermediate electrode 23 may be formed to have the same configuration as the first electrode 21 or the second electrode 25.

The memory resistor 22 may be formed of a variable resistance material used in the resistive memory device. Here, the variable resistance material has two or more resistance characteristics depending on the application of current. Specifically, a transition metal oxide (TMO) may be used, and examples thereof include Ni oxide, Cu oxide, Ti oxide, Co oxide, Hf oxide, Zr oxide, and Zn oxide. In addition, W oxide, Nb oxide, TiNi oxide, LiNi oxide, Al oxide, InZn oxide, V oxide, SrZr oxide, SrTi oxide, Cr oxide, Fe oxide, Ta oxide may also be used.

The switch structure 24 may be formed of a diode, a threshold switching device, a varistor, or the like used in a semiconductor device. When the switch structure 24 is formed in a diode structure, a bilayer structure of an n-type semiconductor layer and a p-type semiconductor layer, preferably, a bilayer structure of an n-type oxide layer and a p-type oxide layer Can be. For example, the switch structure 24 is a structure in which a p-type oxide layer such as a CuO layer and an n-type oxide layer such as an InZnO layer are sequentially stacked, or a p-type oxide layer such as NiO and an n-type oxide layer such as TiO ₂ are sequentially It may be a stacked structure. In the case of the CuO layer, due to the naturally occurring Cu deficiency, O ^{2 −} that is not bonded with Cu may act as a donor to form a p-type semiconductor layer. For the InZnO layer, and naturally acts as a Zn gap (interstitial) and O public (vacancy), have not combined with the presence in addition to the grid, or O Zn ^{2 +} is an acceptor (acceptor) by the generated may be n-type semiconductor . Although the switch structure 24 may be manufactured using amorphous oxide layers that are easily formed at room temperature, the switch structure 24 may also be manufactured using an oxide layer of a crystalline phase. In the case of the silicon diode, since it must be formed in a high temperature process of about 800 ℃, there is a possibility that a variety of problems due to the high temperature process occurs. Therefore, in this embodiment, it is preferable to form the switch structure 24 with an oxide layer that can be easily formed at room temperature. A contact electrode (not shown) may be further provided between the switch structure 24 and the second electrode 25.

The resistive memory device according to the exemplary embodiment of the present invention may be manufactured using semiconductor processing techniques such as CVD and PVD.

2 shows a cross point resistive memory array in accordance with an embodiment of the invention.

Referring to FIG. 2, a plurality of first electrodes 21 and a plurality of second electrodes 25 formed in a direction intersecting with the electrodes of the first electrodes 21 formed in parallel with each other in a first direction are provided. The first stacked structure S1 may be provided at the intersection of the 21 and the second electrode 25. The first stacked structure S1 may include a first memory resistor 22, a first intermediate electrode 23, and a first switch structure 24 that are sequentially stacked on the first electrode 21. Positions of the first memory resistor 22 and the first switch structure 24 may be interchanged. The first memory resistor 22, the first intermediate electrode 23, and the first switch structure 24 correspond to the memory resistor 22, the intermediate electrode 23, and the switch structure 24 of FIG. 1A, respectively. At least one of the first electrode 21 and the second electrode 25 may have a multilayer structure including a conductive layer formed of a noble metal and a conductive layer formed of a metal having a lower specific resistance than the noble metal. That is, the first electrode 21 of FIG. 2 may have the same structure as the first electrode 21 of FIG. 1A, and the second electrode 25 of FIG. 2 is the same as the second electrode 25 of FIG. 1B. It may have a structure.

A second switch structure, a second intermediate electrode, a second memory resistor, a third electrode, etc. may be further provided on the second electrode 25 of FIG. 2. An example is shown in FIG. 3.

Referring to FIG. 3, the first electrode 21, the first stacked structure S1, and the second electrode 25 as shown in FIG. 2 are provided, and are spaced apart from the upper surface of the second electrode 25 by a predetermined interval. Three electrodes 29 are further provided. The third electrode 29 may have a wiring form and may be formed at equal intervals, and may cross, preferably, orthogonal to, the second electrode 25. The configuration of the third electrode 29 may be the same as the first electrode 21 or the second electrode 25. A second stacked structure S2 is provided at the intersection of the second electrode 25 and the third electrode 29. The second stacked structure S2 and the first stacked structure S1 may have the same stacked structure or a vertically symmetrical structure in a circuit. That is, if the first stacked structure S1 includes a structure in which the first intermediate electrode 23 and the first switch structure 24 are sequentially stacked on the first memory resistor 22, the second stacked structure S2. ) May have a structure in which the second intermediate electrode 27 and the second memory resistor 28 are sequentially stacked on the second switch structure 26. The second intermediate electrode 27 may be formed of the same material as the first intermediate electrode 23, and the second switch structure 26 may be a diode, in which case, the second intermediate electrode 27 may be formed in circuit with the first switch structure 24. It may have a vertically symmetric structure or the same laminated structure. That is, the first stacked structure S1, the second electrode 25, and the second stacked structure S2 may have a structure as illustrated in FIG. 4A or 4B. In FIGS. 4A and 4B, the rectifying directions of the first and second switch structures 24 and 26 may vary. In addition, the positions of the first memory resistor 22 and the first switch structure 24 in the first stacked structure S1 of FIGS. 4A and 4B may be interchanged, and the second memory resistor in the second stacked structure S2. The positions of 28 and the second switch structure 26 can also be interchanged.

In addition, in the structure of FIG. 4A, since the first and second switch structures 24 and 26 are symmetrically up and down with respect to the second electrode 25, the second electrode 25 is used as a common bit line. Information can be simultaneously recorded in the first and second memory resistors 22 and 28. On the other hand, in the structure of FIG. 4B, since the rectification directions of the first and second switch structures 24 and 26 are the same, information is written to either one of the first and second memory resistors 22 and 28 in one programming operation. can do.

Referring to FIGS. 2 and 3 again, the first and second stacked structures S1 and S2 are shown in a circular columnar shape, but they may have various deformation shapes, such as a rectangular column or a width wider downward. have. For example, the first and second stacked structures S1 and S2 are asymmetrically extended outside the intersection of the first and second electrodes 21 and 25 and the intersection of the second and third electrodes 25 and 29. It may have a shape. An example of the first laminated structure S1 having the asymmetrical shape is shown in FIG. 5.

Referring to FIG. 5, the first stacked structure S1 is in contact with the first portion P1 and the first portion P1 provided at the intersection of the first and second electrodes 21 and 25 and moves out of the intersection. It may include an extended second portion (P2). That is, the first stacked structure S1 has an asymmetrical shape that extends outside the intersection point of the first and second electrodes 21 and 25. In this case, the shape of the first switch structure 24 and the shape of the first memory resistor 22 may be different from each other. For example, the first switch structure 24 is formed to have an area corresponding to the first portion P1 and the second portion P2, and the first memory resistor 22 has an area corresponding to the first portion P1. It may be formed to have. When the first switch structure 24 is a diode, as the area of the first switch structure 24 increases, the forward current of the first switch structure 24 may increase and the switching characteristics may be improved. Although not shown here, the planar structure of the second stacked structure S2 may be similar to the first stacked structure S1 of FIG. 5.

Although not shown, the resistive memory array of FIG. 3 may further include a stacked structure having the same structure as that of the first stacked structure S1 and the second electrode 25 on the third electrode 29. .

Alternatively, the resistive memory array according to the embodiment of the present invention may be formed on the third electrode 29 of the first structure S1, the second electrode 25, the second structure S2, and the third electrode 29. At least one set may further include a laminate having the same structure as the laminate.

Alternatively, the resistive memory array according to the embodiment of the present invention may include the first structure S1, the second electrode 25, the second structure S2, the third electrode 29, and the like on the third electrode 29. The first structure S1 and the second electrode 25 may further include at least one or more sets of stacked structures having the same structure as the stacked structure in which the first structures S1 and the second electrodes 25 are sequentially stacked.

The resistive memory array according to the embodiment of the present invention may be a multi-layer cross point memory device having a 1D (diode) -1R (resistor) cell structure.

FIG. 6 is a view showing some structures of FIGS. 2 and 3, with reference to this, to explain in more detail the principle that the voltage drop problem is solved in the embodiment of the present invention.

Referring to FIG. 6, the first electrode 21 may have a double layer structure of the first conductive layer 21a and the second conductive layer 21b, and a plurality of first stacked layers on the second conductive layer 21b. The structure S1 is provided. On each first stacked structure S1, a second electrode 25 intersecting with the first electrode 21 is provided. When the current C1 is applied to the first memory resistor 22 of each first stacked structure S1 through the first electrode 21, the current C1 is mainly through the first conductive layer 21a. Will flow. This is because the specific resistance of the first conductive layer 21a is lower than that of the second conductive layer 21b. If the first electrode 21 has a single layer structure made of only the material of the second conductive layer 21b, since the material of the second conductive layer 21b has a relatively high specific resistance, The voltage drop is easily generated from one end E1 to the other end E2. Therefore, when the first electrode 21 has a single layer structure made of only the second conductive layer 21b material, a voltage having a desired size is hardly applied to all the first stacked structures S1. As a result, power consumption increases, and device operation may not be easy. However, as in the embodiment of the present invention, when the first electrode 21 is configured to include a double layer structure in which the first conductive layer 21a and the second conductive layer 21b are sequentially stacked, the current C1 is applied. Since mainly flows through the first conductive layer 21a having a low resistivity, the voltage drop problem can be suppressed or minimized.

In addition, when using the first electrode 21 including both the first conductive layer 21a and the second conductive layer 21b as in the embodiment of the present invention, a material constituting the second conductive layer 21b. That is, the manufacturing cost of the device can be lowered than when using a single layer electrode made of expensive precious metal. The reason why the second conductive layer 21b is required is that when the first memory resistor 22 and the first conductive layer 21a are in direct contact, their interfacial properties may deteriorate. That is, the second conductive layer 21b may be a layer required for the contact characteristic with the first memory resistor 22. It is economical to form the second conductive layer 21b to a minimum thickness as much as possible.

Meanwhile, the second electrode 25 may have an inverse structure of the first electrode 21 or may have the same stacked structure as the first electrode 21. The stack structure of the second electrode 25 may be influenced by what material layer is formed on the second electrode 25. If the n-type semiconductor layer is formed on the second electrode 25, the second electrode 25 preferably has an inverse structure of the first electrode 21. This is because, when the n-type semiconductor layer is directly formed on the noble metal conductive layer having a relatively high resistivity in the second electrode 25, their interface characteristics may deteriorate. On the other hand, when the p-type semiconductor layer is formed on the second electrode 25, the second electrode 25 may have the same stacked structure as the first electrode 21. This is because the noble metal conductive layer having a relatively high resistivity of the second electrode 25 can be directly contacted with the p-type semiconductor layer without any problem. The voltage drop problem can be suppressed also by the second electrode 25, and a manufacturing cost reduction effect can be obtained.

7 shows a modification of FIG. 6.

Referring to FIG. 7, the second conductive layer 21b is patterned to have a planar structure similar to that of the first stacked structure S1. That is, while the second conductive layer 21b of FIG. 6 is a line pattern, the second conductive layer 21b of FIG. 7 is a dot provided at the intersection of the first conductive layer 21a and the second electrode 25. ) Pattern. Even in the structure as shown in FIG. 7, the contact characteristic with the first memory resistor 22 may be secured by the second conductive layer 21b, and the voltage drop problem may be minimized by the first conductive layer 21a. In the array structure shown in FIGS. 2 and 3, the modified structure shown in FIG. 7 may be applied, and the precious metal conductive layer having a relatively high resistivity at the second electrode 25 and the third electrode 29 is also the second conductive layer 21b. Can be patterned.

On the other hand, while the noble metal layer is presented as the second conductive layer 21b and the third conductive layer 25a, according to another embodiment of the present invention as the second conductive layer 21b and the third conductive layer 25a. You may use the alloy layer containing a noble metal. In other words, the second conductive layer 21b and the third conductive layer 25a may be formed of an alloy including one of Pt, Au, Pd, Ir, and Ag, for example, Pt-Ni, Pt-Ti, Ir-Ti, or the like. Can be formed. Also in this case, the operating characteristics (switching characteristics) of the device can be secured by the second conductive layer 21b and the third conductive layer 25a, and the material of the first conductive layer 21a is the second conductive layer 21b. The fourth conductive layer 25b material may have a lower resistivity and a lower cost than the third conductive layer 25a material.

In addition, the memory array according to the embodiment of the present invention may be used as a rewritable memory or a one-time programmable memory. More specifically, the first and / or second memory resistors 22 and 28 include a first element that is reversibly converted from a high resistance state to a low resistance state or from a low resistance state to a high resistance state. In this case, the cross point memory array according to the embodiment of the present invention is a rewritable memory. Examples of the first element include the above-described variable resistance material layer, a filament fuse, and the like. On the other hand, when the first and / or second memory resistors 22 and 28 include a second element that is irreversibly converted from a high resistance state to a low resistance state, the memory cell once programmed is returned to its original state. Since it cannot be reverted, the cross point memory array according to an embodiment of the present invention is a one-time programmable (OTP) memory. An example of the second element is an antifuse, and the antifuse may be formed of silicon oxide, silicon nitride, or the like.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, one of ordinary skill in the art will be able to further diversify the components of the memory array in the embodiments of the present invention, and may modify the structure of the memory array. In addition, it will be appreciated that the first and second electrodes 21 and 25 having the multilayer structure in FIGS. 1A and 1B may be applied to various semiconductor devices. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

1A and 1B are cross-sectional views of a memory device according to example embodiments.

2 and 3 are perspective views of a memory array in accordance with embodiments of the present invention.

4A and 4B are circuit diagrams of a memory array.

5 is a plan view of a memory array in accordance with another embodiment of the present invention.

6 is a perspective view illustrating a principle of suppressing a voltage drop in a memory array according to an embodiment of the present invention.

7 is a perspective view of a memory array in accordance with another embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

21 ... First electrode 21a ... First conductive layer

21b ... second conductive layer 22 ... first memory resistor

23 ... first intermediate electrode 24 ... first switch structure

25 ... second electrode 25a ... third conductive layer

25b ... fourth conductive layer 26 ... second switch structure

27 ... second intermediate electrode 28 ... second memory resistor

P1 ... first part P2 ... second part

S1 ... first laminated structure S2 ... second laminated structure

Claims (25)

A plurality of first electrode lines formed in parallel to each other; A plurality of second electrode lines formed to cross the first electrode lines and parallel to each other; And a first memory resistor formed at an intersection point of the first electrode line and the second electrode line. And at least one of the first electrode line and the second electrode line has a multi-layered structure having a first conductive layer and a second conductive layer comprising a noble metal. The method of claim 1, And the specific resistance of the first conductive layer is lower than that of the second conductive layer. The method according to claim 1 or 2, And the first conductive layer is formed of any one of Al, Mo, Cu, and Ag. The method of claim 1, And the second conductive layer is a layer formed of the noble metal or an alloy layer containing the noble metal. The method according to claim 1 or 4, And the precious metal is any one of Pt, Au, Pd, Ir, and Ag. The method of claim 1, And the second conductive layer is formed on the first conductive layer, or the first conductive layer is formed on the second conductive layer. The method of claim 1, And the second conductive layer is a line pattern. The method of claim 1, And the second conductive layer is a dot pattern provided at the intersection point. The method of claim 1, At the intersection of the first electrode line and the second electrode line, And a first switch structure for regulating the flow of current to the first memory resistor. The method of claim 9, And a first intermediate electrode between the first memory resistor and the first switch structure. The method of claim 10, And the first memory resistor, the first intermediate electrode, the first switching structure, and the second electrode line are sequentially provided on the first electrode line. The method of claim 10, And a first switching structure, the first intermediate electrode, the first memory resistor, and the second electrode line in order on the first electrode line. The method of claim 9, And the first switch structure is any one of a diode, a threshold switching element or a varistor. The method of claim 13, And the diode is an oxide diode. The method of claim 1, The first memory resistor is Ni oxide, Cu oxide, Ti oxide, Co oxide, Hf oxide, Zr oxide, Zn oxide, W oxide, Nb oxide, TiNi oxide, LiNi oxide, Al oxide, InZn oxide, V oxide, SrZr oxide And at least one of SrTi oxide, Cr oxide, Fe oxide, and Ta oxide. The method of claim 1, A plurality of third electrode lines formed to cross the second electrode lines and parallel to each other; And And a second memory resistor provided at an intersection point of the second electrode line and the third electrode line. The third electrode line has a multi-layered structure including the first conductive layer and the second conductive layer. The method of claim 16, At the intersection of the second electrode line and the third electrode line, And a second switch structure for regulating the flow of current to the second memory resistor. The method of claim 17, And a second intermediate electrode between the second memory resistor and the second switch structure. The method of claim 18, And the second memory resistor, the second intermediate electrode, the second switching structure, and the third electrode line are sequentially provided on the second electrode line. The method of claim 18, And the second switching structure, the second intermediate electrode, the second memory resistor, and the third electrode line are sequentially provided on the second electrode line. The method of claim 17, And the second switch structure is any one of a diode, a threshold switching element or a varistor. The method of claim 21, And the diode is an oxide diode. The method of claim 16, And wherein the cross point memory array is a multi-layer cross point memory device having a 1D (diode) -1R (resistor) cell structure. The method of claim 1, And the first memory resistor includes a component that is reversibly converted from a high resistance state to a low resistance state or from a low resistance state to a high resistance state. The method of claim 1, And the first memory resistor includes an element that is irreversibly converted from a high resistance state to a low resistance state.

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