KR20090006628A - Phase change memory device and its manufacturing method - Google Patents

Abstract

A phase change memory device and its manufacturing method are provided. The phase change memory device includes a lower pattern on a substrate. An interlayer insulating film covering the substrate having the lower pattern is disposed. A cylindrical lower electrode penetrating the interlayer insulating layer and in contact with the lower pattern is disposed. An insulating pattern for cutting one side of the cylindrical lower electrode in the vertical direction is disposed in the interlayer insulating film. A phase change pattern contacting the upper portion of the cylindrical lower electrode cut at one side is disposed. An upper electrode is disposed on the phase change pattern. In addition, a method of manufacturing the phase change memory device is also provided.

Description

Phase change memory device and methods of fabrication the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a phase change memory device and a method of manufacturing the same.

Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. The nonvolatile memory devices have the advantage that data stored therein is not destroyed even if their power supply is cut off. Accordingly, the nonvolatile memory device is widely adopted in a mobile communication system, a mobile memory device, an auxiliary memory device of various digital devices, and the like.

There have been many efforts to develop a new memory device having a non-volatile memory characteristic and an efficient structure for improving the integration. A representative example of this is a phase change memory device. The unit cell of the phase change memory device includes an access device and a data storage element serially connected to the access device. The data storage element has a bottom electrode electrically connected to the access element and a phase change material film in contact with the bottom electrode. The phase change material film is a material film that is electrically switched between an amorphous state and a crystalline state or between various resistive states under the crystalline state, depending on the amount of current provided. .

When a program current flows through the lower electrode, joule heat is generated at an interface between the phase change material film and the lower electrode. This joule heat converts a portion of the phase change material film (hereinafter referred to as a 'transition region') into an amorphous state or crystalline state. The resistivity of the transition region having the amorphous state is higher than the resistivity of the transition region having the crystalline state. Therefore, by sensing the current flowing through the transition region in the read mode, it is possible to determine whether the information stored in the phase change material film of the phase change memory device is logic '1' or logic '0'.

Specifically, the operation of the phase change memory device is as follows. The current flowing through the switching element electrically heats the phase change material pattern, thereby reversibly converting the structure of the phase change material pattern into an amorphous state or a crystalline state, thereby storing information. Thereafter, the stored information is read by applying a read voltage between the upper electrode and the lower electrode in contact with the phase change material pattern to sense a current flowing through the phase change material pattern. Here, the reset state of the phase change material pattern is called a reset state, and the reset state of the phase change material pattern is called a set state.

In the operation implementation of such a phase change memory cell, a reset operation during a write operation requires heating above the melting point of the phase change material. As a result, the power consumption required for the reset operation becomes too large. Recently, as the phase change memory device is highly integrated, it is required to decrease the current applied during the reset operation.

Therefore, studies are being conducted to reduce the current applied during the reset operation by reducing the interface area between the phase change material film and the lower electrode where joule heat is generated.

The technical problem to be achieved by the present invention is to improve the above-described problems of the prior art, which is applied during a reset operation by reducing the interface area between the phase change material film and the lower electrode where joule heat is generated. A phase change memory device suitable for reducing current and a method of manufacturing the same are provided.

According to one aspect of the present invention, a phase change memory element is provided. The phase change memory device includes a lower pattern on a substrate. An interlayer insulating film covering the substrate having the lower pattern is disposed. A cylindrical lower electrode penetrating the interlayer insulating layer and in contact with the lower pattern is disposed. An insulating pattern for cutting one side of the cylindrical lower electrode in the vertical direction is disposed in the interlayer insulating film. A phase change pattern contacting the upper portion of the cylindrical lower electrode cut at one side is disposed. An upper electrode is disposed on the phase change pattern.

In some embodiments of the present invention, the cylindrical lower electrode may have a structure surrounding the side wall and the lower surface of the cylinder.

In other embodiments, an upper surface of the cylindrical lower electrode cut at one side may be a crescent shape, a C shape, or a (shape) when viewed in plan view.

In other embodiments, the lower pattern may include a diode and a diode electrode that are sequentially stacked.

In other embodiments, the lower pattern may include a contact plug in contact with the substrate and a conductive pattern on the contact plug. The transistor may further include a transistor electrically connected to the lower pattern on the substrate.

In another embodiment, the insulating pattern is a portion of the upper surface of the lower pattern and the cylindrical lower electrode cut one side through the interlayer insulating film while cutting one side of the cylindrical lower electrode in the vertical direction. It may be arranged to fill a trench structure that exposes the cut sidewall.

In another embodiment, the insulating pattern cuts one side of the cylindrical lower electrode in a vertical direction and exposes an upper surface and a sidewall of the cut region of the cylindrical lower electrode of which the one side is cut in the interlayer insulating film. It may be arranged to fill the trench structure.

According to another aspect of the present invention, a phase change memory device is provided. The phase change memory device includes lower patterns on a substrate. An interlayer insulating film is disposed on the substrate having the lower patterns. Cylindrical lower electrodes are disposed on the lower patterns through the interlayer insulating layer. Line type insulating patterns are disposed in the interlayer insulating layer to cut one side of the cylindrical lower electrodes in a vertical direction along a row direction or a column direction. Phase change patterns in contact with the upper portions of the cylindrical lower electrodes whose one side is cut are disposed. Upper electrodes are disposed on the phase change patterns.

In some embodiments of the present invention, the cylindrical lower electrodes may have a structure surrounding the side wall and the bottom surface of the cylinder.

In other embodiments, the top surface of the cylindrical lower electrodes cut from one side may be a crescent shape, a C shape or a (shape) when viewed in plan view.

In still other embodiments, the top surface of the cylindrical lower electrodes, the one side of which is cut, may have a C C C arrangement in which the same portions are cut and uniformly arranged in plan view.

In still other embodiments, the phase change patterns may be disposed extending in a direction parallel to the cutting plane of the cylindrical lower electrodes whose one side is cut or in a vertical direction of the cutting plane.

In still other embodiments, the line-shaped insulating patterns penetrate the interlayer insulating layer while cutting one side of the cylindrical lower electrodes in a vertical direction, and a portion of the upper surface of the lower patterns and the cylindrical lower part at which one side is cut. And may be arranged to respectively fill the linear trench structures exposing the cut sidewalls of the electrodes.

In example embodiments, the line-shaped insulating patterns may cut one side of the cylindrical lower electrodes in a vertical direction, and may cut the upper surface and sidewalls of the cut regions of the cylindrical lower electrodes of which one side is cut in the interlayer insulating layer. It may be arranged to fill the exposed line trench structures.

According to still another aspect of the present invention, a method of manufacturing a phase change memory device is provided. The method includes preparing a substrate having a lower pattern. An interlayer insulating film is formed on the substrate having the lower pattern. A cylindrical lower electrode is formed through the interlayer insulating layer to contact the lower pattern. An insulating pattern is formed in the interlayer insulating film to cut one side of the cylindrical lower electrode and the interlayer insulating film in a vertical direction. A phase change pattern is formed in contact with an upper portion of the cylindrical lower electrode cut at one side. An upper electrode is formed on the phase change pattern.

In some embodiments of the present invention, the cylindrical lower electrode may be formed to surround the side wall and the bottom surface of the cylinder.

In other embodiments, the upper surface of the cylindrical lower electrode cut one side may be formed in a crescent shape, C shape or (shape when viewed in plan view.

In other embodiments, the lower pattern may be formed to include a diode and a diode electrode stacked in sequence.

In some embodiments, the lower pattern may be formed to include a contact plug in contact with the substrate and a conductive pattern on the contact plug. A transistor electrically connected to the lower pattern may be formed on the substrate.

In another embodiment, the insulating pattern may be formed by cutting one side of the cylindrical lower electrode and the interlayer insulating layer in a vertical direction, and a portion of the upper surface of the lower pattern and the cylindrical lower electrode of which one side is cut. The method may include forming a trench structure exposing the cut sidewall, and forming an insulating layer in the trench structure.

In another embodiment, the insulating pattern may be formed by cutting one side of the cylindrical lower electrode and the interlayer insulating layer in a vertical direction, and the upper surface and the sidewall of the cut region of the cylindrical lower electrode cut at one side thereof. Forming a trench structure to expose the, and forming an insulating film inside the trench structure.

In other embodiments, forming the cylindrical lower electrode may include forming a lower electrode contact hole through the interlayer insulating layer to expose the upper portion of the lower pattern. A lower electrode layer covering sidewalls and a bottom surface of the lower electrode contact hole may be formed on the interlayer insulating layer having the lower electrode contact hole, and an internal insulating layer may be formed on the substrate having the lower electrode layer to fill the lower electrode contact hole. . Subsequently, the internal insulating film and the lower electrode film may be planarized until the upper surface of the interlayer insulating film is exposed.

In another embodiment, the internal insulating film and the lower electrode film may be planarized until the upper surface of the interlayer insulating film is exposed, and then an etch back process and a planarization process may be performed at least one time.

According to still another aspect of the present invention, a method of manufacturing a phase change memory device is provided. The method includes preparing a substrate having lower patterns. An interlayer insulating film is formed on the substrate having the lower patterns. Cylindrical lower electrodes are formed on the lower patterns by penetrating the interlayer insulating layer. Line insulating patterns are formed in the interlayer insulating film to cut one side of the cylindrical lower electrodes and the interlayer insulating film in a vertical direction along a row direction or a column direction. The one side forms phase change patterns in contact with the upper portions of the cylindrical lower electrodes. Upper electrodes are formed on the phase change patterns.

In some embodiments of the present invention, the cylindrical lower electrodes may be formed to surround the side wall and the bottom surface of the cylinder.

In other embodiments, the upper surface of the cylindrical lower electrodes cut one side may be formed in a crescent shape, C shape or (shape when viewed in plan view.

In still other embodiments, the top surface of the cylindrical lower electrodes, the one side of which is cut, may be formed to have a C C C arrangement in which the same portions are cut and uniformly arranged in plan view.

In still other embodiments, the phase change patterns may be formed to extend in a direction parallel to the cutting plane of the cylindrical lower electrodes whose one side is cut or in a vertical direction of the cutting plane.

In example embodiments, the forming of the linear insulating patterns may be performed by cutting one side of the cylindrical lower electrodes and the interlayer insulating layer in a vertical direction to cut a portion of the upper surface of the lower patterns and the cylindrical lower part of which one side is cut. Forming linear trench structures exposing the cut sidewalls of electrodes, and forming an insulating film inside the linear trench structures.

In still other embodiments, the forming of the linear insulating patterns may be performed by cutting one side of the cylindrical lower electrodes and the interlayer insulating layer in a vertical direction, and the upper surface of the cut regions of the cylindrical lower electrodes having one side cut. And forming linear trench structures exposing sidewalls, and forming an insulating layer in the linear trench structures.

According to the present invention, the upper surface of the cylindrical lower electrodes cut on one side has a C shape, a crescent shape or a ring shape of the cylindrical lower electrode as in the prior art as it has a shape. As a result, the area of the interface between the phase change pattern and the lower electrode in which joule heat is generated can be reduced, thereby reducing the current applied during the reset operation. In conclusion, it is possible to implement a phase change memory device which is advantageous for high integration.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

In addition, the crescent shape, C shape or (shape included in the present invention includes all of their rotated shapes.

1 is an equivalent circuit diagram illustrating a portion of a cell array region of a phase change memory device according to example embodiments, and FIG. 2 is a plan view corresponding to the equivalent circuit diagram of FIG. 1.

1 and 2, a phase change memory device according to example embodiments may include bit lines BL disposed in parallel with each other in a column direction, and word lines WL disposed in parallel with each other in a row direction. ), A plurality of phase change patterns Rp, and a plurality of diodes D.

The bit lines BL may be disposed to intersect the word lines WL. Each of the phase change patterns Rp may be disposed at intersections of the bit lines BL and the word lines WL. Each of the diodes D may be connected in series to a corresponding one of the phase change patterns Rp. In addition, each of the phase change patterns Rp may be connected to a corresponding one of the bit lines BL. Each of the diodes D may be connected to a corresponding one of the word lines WL. The diodes D may serve as an access device. However, the diodes D may be omitted. Alternatively, the access element may be a MOS transistor.

3A to 3E, the manufacturing method of the phase change memory device according to the embodiments of the present invention will be described. Here, reference numerals A and B of FIGS. 3A to 3E represent cross-sectional views cut along the cutting lines I ′ and II-II ′ of FIG. 2, respectively.

2 and 3A, an isolation layer 102 may be formed in a predetermined region of the substrate 100 to define the active regions 102a. The substrate 100 may be a semiconductor substrate such as a silicon wafer or a silicon on insulator (SOI) wafer. The substrate 100 may have impurity ions of a first conductivity type. The device isolation layer 102a may be formed using a shallow trench isolation (STI) technique. The device isolation layer 102 may be formed of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. The active regions 102a may be formed in a line shape.

Word lines WL 105 may be formed by implanting impurity ions of a second conductivity type different from the first conductivity type into the active regions 102a. Hereinafter, for the sake of brevity, the first and second conductivity types will be described assuming that they are P-type and N-type, respectively. However, the first and second conductivity types may be N type and P type, respectively.

A first interlayer insulating layer 107 may be formed on the substrate 100 having the word lines WL 105 and the device isolation layer 102. The first interlayer insulating film 107 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The first interlayer insulating layer 107 may be patterned to form contact holes 108h exposing predetermined regions of the word lines WL 105.

First and second semiconductor patterns 110 and 112 may be sequentially stacked in the contact holes 108h. The first and second semiconductor patterns 110 and 112 may be formed using an epitaxial growth technique or a chemical vapor deposition (CVD) technique. The first and second semiconductor patterns 110 and 112 may form diodes D.

The first semiconductor pattern 110 may be in contact with the word lines WL 105. The first semiconductor pattern 110 may be formed to have impurity ions of the second conductivity type. The second semiconductor pattern 112 may be formed to have impurity ions of the first conductivity type. Alternatively, the first semiconductor pattern 110 may be formed to have impurity ions of the first conductivity type, and the second semiconductor pattern 112 may be formed to have impurity ions of the second conductivity type. . A metal silicide layer may be further formed on the second semiconductor pattern 112, but it will be omitted for simplicity.

Diode electrodes 115 may be formed on the diodes D, respectively. The diode electrodes 115 include a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, Ru film And a CoSi film, a NiSi film, a conductive carbon group film, a Cu film, and a combination film thereof. For example, the diode electrodes 115 may be formed by sequentially stacking a TiN film and a W film.

The diode electrodes 115 may be formed in the contact holes 108h. In this case, the diode electrodes 115 may be self-aligned on the diodes D, respectively. Alternatively, the diode electrodes 115 may be omitted.

2 and 3B, a second interlayer insulating film 117 may be formed on the substrate 100 having the diode electrodes 115. The second interlayer insulating layer 117 may be patterned to form lower electrode contact holes 120h exposing the diode electrodes 115, respectively. The lower electrode layer 122 may be formed along the surface of the substrate having the lower electrode contact holes 120h. The lower electrode layer 122 may cover the diode electrodes 115 in the lower electrode contact holes 120h, and the lower electrode layer 122 may have sidewalls of the lower electrode contact holes 120h and It may be formed to cover the upper portion of the second interlayer insulating film 117.

The lower electrode film 122 includes a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, Ru film And a CoSi film, a NiSi film, a conductive carbon group film, a Cu film, and a combination film thereof.

An internal insulating layer 125 may be formed on the lower electrode layer 122 to fill the lower electrode contact holes 120h and cover the substrate 100. The internal insulating film 125 may be formed of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. In addition, the internal insulating layer 125 may be formed of the same material layer as the second interlayer insulating layer 117.

In another embodiment, the internal insulating layer 125 may be omitted. In this case, the lower electrode layer 122 may be formed to completely fill the lower electrode contact holes 120h.

2 and 3C, the internal insulating layer 125 and the lower electrode layer 122 are partially removed to form cylindrical lower electrodes in the lower electrode contact holes 120h on the diode electrodes 115. And 122 'and internal insulating patterns 125' may be formed.

In detail, the cylindrical lower electrodes 122 ′ and the internal insulating patterns 125 ′ may be formed using an etch-back process. In addition, forming the cylindrical lower electrodes 122 ′ and the internal insulating patterns 125 ′ may include a combination of a chemical mechanical polishing (CMP) process and an etch-back process. It can also be carried out using.

For example, the internal insulating film 125 and the lower electrode film 122 may be planarized using a chemical mechanical polishing (CMP) process using the second interlayer insulating film 117 as a stop film. have. As a result, the internal insulating layer 125 and the lower electrode layer 122 may remain in the lower electrode contact holes 120h.

In another example embodiment, the internal insulation layer 125 and the lower electrode layer 122 are planarized until the upper surface of the second interlayer dielectric layer 117 is exposed, and then the etch back process and the planarization process are performed. Further, the height uniformity of the cylindrical lower electrodes 122 ′ and the internal insulating patterns 125 ′ in the second interlayer insulating layer 117 may be increased.

The cylindrical lower electrodes 122 ′ may be formed to surround sidewalls and bottoms of the internal insulating patterns 125 ′, respectively. The cylindrical lower electrodes 122 ′ may be in contact with the diode electrodes 115, respectively. When the diode electrodes 115 are omitted, the cylindrical lower electrodes 122 ′ may directly contact the diodes D. Referring to FIG. The exposed surfaces of the cylindrical lower electrodes 122 ′ may be formed in a ring shape. The contact surfaces of the cylindrical lower electrodes 122 ′ and the diode electrodes 115 may be smaller than the upper surfaces of the diode electrodes 115.

In another embodiment, when the internal insulating layer 125 is omitted, the cylindrical lower electrodes 122 ′ may be formed in a pillar shape. In this case, the exposed surfaces of the cylindrical lower electrodes 122 ′ may be formed in a circular shape.

2 and 3D, one side of the cylindrical lower electrodes 122 ′ on the substrate 100 having the cylindrical lower electrodes 122 ′ and the internal insulating patterns 125 ′. A mask pattern 127 may be formed having lined openings 127t exposing the gaps. The linear openings 127t may be formed along the row direction or the column direction. Therefore, one side of the plurality of cylindrical lower electrodes 122 ′ disposed in the row or column direction in the one line-shaped opening 127t may be simultaneously exposed. The mask pattern 127 may be formed as a hard mask pattern or a photoresist pattern.

In addition, a portion of the internal insulating pattern 125 ′ may be exposed by the line-shaped openings 127t. For example, when the line-shaped openings 127t expose 50% of the upper surfaces of the cylindrical lower electrodes 122 ', the upper surfaces of the internal insulating patterns 125' may also be exposed by 50%. .

Using the mask pattern 127 as an etching mask, the cylindrical lower electrodes 122 ′ and the second interlayer insulating layer 117 exposed at one side are etched to form the diode electrodes 115 and the first. Line trench structures 130t exposing the interlayer insulating layer 107 may be formed. In this case, when a portion of the internal insulation patterns 125 ′ is exposed by the line-type openings 127t, the internal insulation patterns 125 ′ may also be etched at the same time. As a result, cylindrical lower electrodes 122 ″ cut at one side and internal insulating patterns 125 ″ cut at one side may be formed.

The top surfaces of the cylindrical lower electrodes 122 ″ cut at one side may be a C shape, a crescent shape having a uniform thickness, or a shape (.) Therefore, the cylindrical shape is cut at one side. Upper surfaces of the lower electrodes 122 ″ may have a smaller area than upper surfaces of the cylindrical lower electrodes 122 ′.

Alternatively, as shown in FIG. 4A, by using the mask pattern 127 as an etching mask, the lower electrodes 122 ′ and the second interlayer insulating layer 117 exposed at one side thereof may be etched. Line trenches 130t ′ may be formed to expose sidewalls and the top surface of the etched lower electrodes 122 ′. In this case, when a portion of the internal insulation patterns 125 ′ is exposed by the line-type openings 127t, the internal insulation patterns 125 ′ may also be etched at the same time.

The linear trench structures 130t and 130t 'may be formed along a row direction or a column direction. Specifically, as shown in FIG. 2, the line direction of the line trench structures 130t and 130t ′ may be formed in a direction perpendicular to the word lines 105 (WL).

Alternatively, as shown in FIGS. 5 and 6, the line direction of the line trench structures 130t ″ may be formed in a direction parallel to the word lines 105 (WL).

2 and 3E, an insulating layer may be formed on the substrate having the line trench structures 130t to fill the line trench structures 130t. The insulating layer may be planarized until the top surfaces of the cylindrical lower electrodes 122 ″ cut at one side thereof are exposed to form line insulating patterns 132 in the line trench structures 130t. .

Alternatively, as illustrated in FIG. 4B, an insulating layer may be formed to fill the linear trench structures 130t 'on the substrate having the linear trench structures 130t'. The insulating layer may be planarized until the upper surfaces of the cylindrical lower electrodes 122 ″ cut at one side thereof are exposed to form the linear insulating patterns 132 ′ in the linear trench structures 130t ′. Can be.

Stacking of the phase change pattern 135 and the upper electrode 137 sequentially stacked while contacting the cylindrical lower electrodes 122 ″ cut at one side thereof on the substrate having the line insulating patterns 132 and 132 ′. Patterns can be formed. The upper electrodes 137 may serve as bit lines BL. The phase change patterns 135 and the upper electrodes 137 may be formed in a direction perpendicular to the word lines WL 105. In addition, the phase change patterns 135 and the upper electrodes 137 (BL) may be formed in a direction parallel to the line direction of the line type insulating patterns 132 as shown in FIG. 2. .

Alternatively, as shown in FIGS. 5 and 6, when the line direction of the line type insulating patterns 132 ″ is formed in a direction parallel to the word lines 105 (WL), the phase change is performed. As illustrated in FIG. 5, the patterns 135 and the upper electrodes 137 and BL may be formed in a direction perpendicular to the line direction of the line type insulating patterns 132 ″. As a result, the distance L2 between the cylinder-shaped lower electrodes 122 '' 'cut at one side sharing the one phase change pattern 135 is cut at the one side of the structure shown in FIG. It can be kept wider than the distance (L1) between the type lower electrodes (122 ''). Thus, it is possible to reduce thermal disturbances between cells.

The phase change patterns 135 may be formed of a chalcogenide material layer. For example, the phase change patterns 135 may include at least two compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. Can be formed. An interface film (not shown) may be interposed between the phase change patterns 135 and the cylindrical lower electrodes 122 ″ cut at one side thereof.

The upper electrodes 137 (BL) include a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, and a WBN. Film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, It can be formed into one selected from the group consisting of a Ru film, a CoSi film, a NiSi film, a conductive carbon group film, a Cu film, and a combination film thereof.

As described above, the upper surface of the cylindrical lower electrodes 122 '' cut off at one side according to the embodiments of the present invention is a ring of the cylindrical lower electrode 122 'as in the prior art. It is possible to have a narrower area than the upper surface of the shape. As a result, the interface area between the phase change pattern 135 and the lower electrode 122 ″ in which joule heat is generated is reduced, thereby reducing the current applied during the reset operation as compared with the related art. Will be.

7 is an enlarged plan view of a ring-shaped upper surface of the cylindrical lower electrode 122 ′ shown in FIG. 3C, and FIGS. 8A to 8D are views of the cylindrical lower electrode 122 ′ of FIG. 7. One side is a plan view illustrating a structure cut by cutting lines of C1, C2, C3, and C4, respectively, by a line type insulating pattern. In forming the cylindrical lower electrodes cut at one side thereof, cut line positions due to the line insulating patterns may be varied. For example, it can change freely within the range from the said cutting line C1 to the said cutting line C4.

Referring to FIGS. 7 and 8A, FIG. 8A is a plan view illustrating cylindrical lower electrodes 122a cut at one side by line insulating patterns 132a having the cutting line C1 of FIG. 7. The cutting line C1 represents a line for cutting the cylindrical lower electrodes 122 ′ by the thickness T of the side wall of the cylinder. As a result, the upper surfaces of the cylindrical lower electrodes 122a, the one side of which is cut, have a C shape when viewed in plan view, and the upper surfaces of the cylindrical lower electrodes 122a, the one of which is cut, of the one side. It may have a smaller area than the upper surfaces of the cylindrical lower electrodes 122 '.

Referring to FIGS. 7 and 8B, FIG. 8B is a plan view illustrating cylindrical lower electrodes 122b cut at one side by line insulating patterns 132b having the cutting line C2 of FIG. 7. The cutting line C2 represents a line for cutting the cylindrical lower electrodes 122 'by 1/2 of the cylinder diameter 120D. As a result, the top surfaces of the cylindrical lower electrodes 122b cut at one side thereof have a crescent shape with a uniform thickness when viewed in plan view, and the cylindrical lower electrodes 122b cut at one side thereof. ) May have a half area of the upper surface of the cylindrical lower electrode 122 ′.

Referring to FIGS. 7 and 8C, FIG. 8C is a plan view illustrating cylindrical lower electrodes 122c cut at one side by line insulating patterns 132c having a cutting line C3 of FIG. 7. The cutting line C3 represents a line for cutting the cylindrical lower electrodes 122 'by 3/4 of the cylinder diameter 120D. As a result, the top surfaces of the cylindrical lower electrodes 122c, the one side of which has been cut, have a shape as shown in plan view, and the top surfaces of the cylindrical lower electrodes 122c, the one of which is cut, of the one side. It is possible to have an area narrower than half the area of the upper surface of the cylindrical lower electrode 122 '.

Referring to FIGS. 7 and 8D, FIG. 8D is a plan view illustrating cylindrical lower electrodes 122d having one side cut by line insulating patterns 132d having the cutting line C4 of FIG. 7. The cutting line C4 represents a line for cutting the cylindrical lower electrode 122 'by the cylinder diameter 120D minus the cylinder thickness T. In other words, the cylindrical lower electrodes 122d having one side cut off may remain only as much as the cylinder thickness T, and the remaining regions may be removed by the line type insulating patterns 132d. As a result, the top surfaces of the cylindrical lower electrodes 122d, the one side of which has been cut, have a shape when viewed in plan view, and the top surfaces of the cylindrical lower electrodes 122d, which the one of the side have been cut. The one side of FIG. 8C may have a smaller area than the upper surfaces of the cut cylindrical lower electrodes 122c.

As described above, the upper surface of the cylindrical lower electrodes 122a, 122b, 122c, and 122d cut at one side according to embodiments of the present invention is the cylindrical lower electrode 122 'as in the prior art. It is possible to have a smaller area than the ring-shaped upper surface of the (ring). As a result, the interface area between the phase change pattern 135 and the lower electrodes 122a, 122b, 122c, and 122d in which joule heat is generated is reduced and applied during a reset operation as compared with the related art. It is possible to reduce the current.

9 is an equivalent circuit diagram illustrating a portion of a cell array region of a phase change memory device according to other embodiments of the present invention, and FIG. 10 illustrates a method of manufacturing a phase change memory device according to another embodiment of the present invention. It is sectional drawing for doing.

Referring to FIG. 9, a phase change memory device according to another embodiment of the present invention may include a plurality of bit lines BL arranged in parallel with each other in a column direction, word lines WL disposed in parallel with each other in a row direction. Phase change patterns Rp and a plurality of transistors Ta.

The bit lines BL may be disposed to intersect the word lines WL. Each of the phase change patterns Rp may be disposed at intersections of the bit lines BL and the word lines WL. Each of the phase change patterns Rp may be connected in series to a source / drain region of a corresponding one of the transistors Ta. In addition, each of the phase change patterns Rp may be connected to a corresponding one of the bit lines BL. Each of the transistors Ta may be connected to a corresponding one of the word lines WL. The transistors Ta may serve as an access device. However, the transistors Ta may be omitted. Alternatively, the access element may be a diode.

Referring to FIG. 10, an isolation layer 202 may be formed on the substrate 200 to define the active regions 202a. Word lines 205 and WL may be formed on the active regions 202a. Source / drain regions 206 may be formed in the active regions 202a adjacent to both sides of the word lines 205 and WL. A lower insulating layer 207 may be formed on the substrate 200 having the word lines 205 (WL). The word line 205 (WL), the active region 202a and the source / drain regions 206 may constitute a transistor (Ta in FIG. 9).

First plugs 210a and second plugs 210b may be formed in the lower insulating layer 207. Source lines 215b may be formed on the drain pads 215a and the second plugs 210b on the first plugs 210a. The drain pads 215a may be electrically connected to a selected one of the source / drain regions 206 by the first plugs 210a passing through the lower insulating layer 207. The source lines 215b may be electrically connected to another selected one of the source / drain regions 206 by the second plugs 210b passing through the lower insulating layer 207.

Subsequently, the upper electrode 137 may be formed using the same method as that of FIGS. 3B to 3E.

Referring to FIGS. 2 and 3E again, a phase change memory device according to embodiments of the present invention will be described.

2 and 3E, the phase change memory device may include a device isolation layer 102 defining active regions 102a in a predetermined region of the substrate 100. The substrate 100 may be a semiconductor substrate such as a silicon wafer or a silicon on insulator (SOI) wafer. The substrate 100 may have impurity ions of a first conductivity type. The device isolation layer 102 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. The active regions 102a may have a line structure.

The active regions 102a may function as word lines WL 105 including impurity ions of a second conductivity type different from the first conductivity type. Hereinafter, for the sake of brevity, a description will be given assuming that the first and second conductivity types are P-type and N-type, respectively. However, the first and second conductivity types may be N type and P type, respectively.

A first interlayer insulating layer 107 may be disposed on the substrate 100 having the word lines WL 105 and the device isolation layer 102. The first interlayer insulating film 107 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. Contact holes 108h may be disposed through the first interlayer insulating layer 107 to expose predetermined regions of the word lines WL 105. First and second semiconductor patterns 110 and 112 may be sequentially stacked in the contact holes 108h. The first and second semiconductor patterns 110 and 112 may form diodes D.

The first semiconductor pattern 110 may be in contact with the word lines WL 105. The first semiconductor pattern 110 may include impurity ions of the second conductivity type. The second semiconductor pattern 112 may include impurity ions of the first conductivity type. Alternatively, the first semiconductor pattern 110 may include impurity ions of the first conductivity type, and the second semiconductor pattern 112 may include impurity ions of the second conductivity type.

Diode electrodes 115 may be disposed on the diodes D, respectively. The diode electrodes 115 include a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, Ru film , A CoSi film, a NiSi film, a conductive carbon group film, a Cu film, and a combination film thereof. For example, the diode electrodes 115 may include a TiN film and a W film that are sequentially stacked.

The diode electrodes 115 may be disposed in the contact holes 108h. In this case, the diode electrodes 115 may be self-aligned on the diodes D, respectively. Alternatively, the diode electrodes 115 may be omitted.

A second interlayer insulating film 117 may be disposed on the substrate 100 having the diode electrodes 115. Cylindrical lower electrodes may be disposed on the diode electrodes 115 through the second interlayer insulating layer 117. Internal insulating patterns may be disposed in the cylindrical lower electrodes. Line insulating patterns 132 may be disposed in the second interlayer insulating layer 117 to cut one side of the cylindrical lower electrodes in a vertical direction in a row direction or a column direction. Cylindrical lower electrodes 122 ″ cut at one side and phase change patterns 135 contacting an upper portion of the internal insulating patterns 125 ″ at which one side is cut are disposed. Upper electrodes 137 are disposed on the phase change patterns 135, respectively. The upper electrodes 137 may serve as bit lines BL.

The top surfaces of the cylindrical lower electrodes 122 ″ cut at one side may be a C shape, a crescent shape having a uniform thickness, or a shape in plan view. Thus, the cylindrical shape is cut at one side. The upper surfaces of the lower electrodes 122 ″ may have a narrower area than the upper surface of the cylindrical lower electrodes of the related art. In addition, the one side of the lower electrodes 122 ″ may be cut. The top surface may have a CCC array in which identical parts are cut and uniformly arranged in plan view.

The line type insulating patterns 132 penetrate the second interlayer insulating layer 117 while cutting one side of the cylindrical lower electrodes in a vertical direction, so that a part of the upper surfaces of the diode electrodes 115 and the one side thereof are formed. Each of the lined trench structures 130t may be disposed to expose the cut sidewalls of the cut cylindrical lower electrodes 122 ″.

Alternatively, as shown in FIG. 4B, the line type insulating patterns 132 ′ are formed by cutting one side of the cylindrical lower electrodes in a vertical direction while cutting the one side in the second interlayer insulating layer 117. It may be arranged to fill the line trench structures 130t 'exposing the top surface and sidewalls of the cut regions of the type bottom electrodes 122' '.

The cylindrical lower electrodes 122 ″ cut at one side thereof include a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, and a WON film. Film, WSiN film, WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, It may include one selected from the group consisting of a ZrSiN film, ZrAlN film, Ru film, CoSi film, NiSi film, conductive carbon group film, Cu film, and a combination film thereof.

The internal insulating patterns 125 ″ cut at one side may include an insulating layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. Alternatively, the internal insulating patterns 125 ″ cut at one side may be the same material layer as the second interlayer insulating layer 117.

In another embodiment, the inner insulation patterns 125 ″ cut at one side may be omitted. In this case, the cylindrical lower electrodes 122 ″ cut at one side may have a pillar structure in which one side is cut.

The linear trench structures 130t and 130t 'may be disposed along the row direction or the column direction. Specifically, as shown in FIG. 2, the line direction of the line trench structures 130t and 130t ′ may be disposed in a direction perpendicular to the word lines 105 (WL). Alternatively, as shown in FIGS. 5 and 6, the line direction of the linear trench structures 130t ″ may be disposed in a direction parallel to the word lines 105 (WL).

The phase change patterns 135 and the upper electrodes 137 may be disposed in a direction perpendicular to the word lines WL 105. In addition, the phase change patterns 135 and the upper electrodes 137 and BL may be arranged in a direction parallel to the line direction of the line type insulating patterns 132 as shown in FIG. 2. .

Alternatively, as shown in FIGS. 5 and 6, when the line direction of the line type insulating patterns 132 ″ is disposed in a direction parallel to the word lines 105 (WL), the phase change may occur. As illustrated in FIG. 5, the patterns 135 and the upper electrodes 137 and BL may be disposed in a direction perpendicular to the line direction of the line type insulating patterns 132 ″. As a result, the distance L2 between the cylinder-shaped lower electrodes 122 '' 'cut at one side sharing the one phase change pattern 135 is cut at the one side of the structure shown in FIG. It can be kept wider than the distance (L1) between the type lower electrodes (122 ''). Thus, it is possible to reduce the thermal disturbance between the cells.

The phase change patterns 135 may include a chalcogenide material layer. For example, the phase change patterns 135 may include two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. It may include.

The upper electrodes 137 (BL) include a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, and a WBN. Film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, It may include one selected from the group consisting of a Ru film, a CoSi film, a NiSi film, a conductive carbon group film, a Cu film, and a combination film thereof.

As described above, the upper surfaces of the cylindrical lower electrodes 122 ″ cut off at one side according to embodiments of the present invention are a ring shaped upper surface of the cylindrical lower electrode as in the prior art. It is possible to have a smaller area. As a result, the interface area between the phase change pattern 135 and the lower electrode 122 ″ in which joule heat is generated is reduced, thereby reducing the current applied during the reset operation as compared with the related art. Will be.

Referring to FIG. 10 again, a phase change memory device according to other embodiments of the present invention will be described.

Referring to FIG. 10, an isolation layer 202 defining active regions 202a may be disposed on a substrate 200. Word lines 205 and WL may be disposed on the active regions 202a. Source / drain regions 206 may be disposed in the active regions 202a adjacent to both sides of the word lines 205 (WL). A lower insulating layer 207 may be disposed on the substrate 200 having the word lines 205 (WL). The word line 205 (WL), the active region 202a and the source / drain regions 206 may constitute a transistor (Ta in FIG. 9).

First plugs 210a and second plugs 210b may be disposed in the lower insulating layer 207. Drain pads 215a may be disposed on the first plugs 210a and source lines 215b may be disposed on the second plugs 210b. The drain pads 215a may be electrically connected to a selected one of the source / drain regions 206 by the first plugs 210a passing through the lower insulating layer 207. The source lines 215b may be electrically connected to another selected one of the source / drain regions 206 by the second plugs 210b passing through the lower insulating layer 207.

A second interlayer insulating layer 117 may be disposed on the substrate 200 having the drain pads 215a and the source lines 215b. Cylindrical lower electrodes may be disposed on the diode electrodes 115 through the second interlayer insulating layer 117. Internal insulating patterns may be disposed in the cylindrical lower electrodes. Line insulating patterns 132 may be disposed in the second interlayer insulating layer 117 to cut one side of the cylindrical lower electrodes in a vertical direction in a row direction or a column direction. Cylindrical lower electrodes 122 ″ cut at one side and phase change patterns 135 contacting an upper portion of the internal insulating patterns 125 ″ at which one side is cut are disposed. Upper electrodes 137 and BL are disposed on the phase change patterns 135, respectively. The upper electrodes 137 may serve as bit lines BL.

The top surfaces of the cylindrical lower electrodes 122 ″ cut at one side may be a C shape, a crescent shape having a uniform thickness, or a shape in plan view. Thus, the cylindrical shape is cut at one side. The upper surfaces of the lower electrodes 122 ″ may have a narrower area than the upper surface of the cylindrical lower electrodes of the related art. In addition, the one side of the lower electrodes 122 ″ may be cut. The top surface may have a CCC array in which identical parts are cut and uniformly arranged in plan view.

The cylindrical lower electrodes 122 ″ cut at one side thereof include a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, and a WON film. Film, WSiN film, WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, It may include one selected from the group consisting of a ZrSiN film, ZrAlN film, Ru film, CoSi film, NiSi film, conductive carbon group film, Cu film, and a combination film thereof.

The internal insulating patterns 125 ″ cut at one side may include an insulating layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. Alternatively, the internal insulating patterns 125 ″ cut at one side may be the same material layer as the second interlayer insulating layer 117. In another embodiment, the inner insulation patterns 125 ″ cut at one side may be omitted. In this case, the cylindrical lower electrodes 122 ″ cut at one side may have a pillar structure in which one side is cut.

The phase change patterns 135 and the upper electrodes 137 may be disposed in a direction perpendicular to the word lines WL 105. In addition, the phase change patterns 135 and the upper electrodes 137 and BL may be disposed in a direction parallel to or perpendicular to the line direction of the line type insulating patterns 132.

The phase change patterns 135 may include a chalcogenide material layer. For example, the phase change patterns 135 may include two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. It may include. The upper electrodes 137 (BL) include a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, and a WBN. Film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, It may include one selected from the group consisting of a Ru film, a CoSi film, a NiSi film, a conductive carbon group film, a Cu film, and a combination film thereof.

1 is an equivalent circuit diagram showing a portion of a cell array region of a phase change memory device according to embodiments of the present invention.

FIG. 2 is a plan view of a cell array region of a phase change memory device corresponding to the equivalent circuit diagram of FIG. 1.

3A to 3E are cross-sectional views taken along cut lines I-I 'and II-II' of FIG. 2 to explain a method of manufacturing a phase change memory device according to example embodiments.

4A and 4B are cross-sectional views taken along cut lines I-I 'and II-II' of FIG. 2 to explain a method of manufacturing a phase change memory device according to other exemplary embodiments.

5 is a plan view of a cell array region of a phase change memory device according to still other embodiments of the present invention.

6 is a cross-sectional view taken along cut lines I-I 'and II-II' of FIG. 5 to explain a method of manufacturing a phase change memory device according to still another embodiment of the present invention.

FIG. 7 is an enlarged plan view of a ring-shaped upper surface of the cylindrical lower electrode 122 ′ shown in FIG. 3C.

8A to 8D are plan views illustrating a structure in which one side of the cylindrical lower electrode 122 ′ of FIG. 7 is cut by cutting lines of C1, C2, C3, and C4, respectively, by a line type insulating pattern.

9 is an equivalent circuit diagram illustrating a portion of a cell array region of a phase change memory device according to still another embodiment of the present invention.

10 is a cross-sectional view for describing a method of manufacturing a phase change memory device according to still other embodiments of the present invention.

Claims (32)

A substrate having a lower pattern; An interlayer insulating film covering the substrate having the lower pattern; A cylindrical lower electrode penetrating the interlayer insulating layer to contact the lower pattern; An insulating pattern disposed in the interlayer insulating film while cutting one side of the cylindrical lower electrode in a vertical direction; A phase change pattern formed to contact the upper portion of the cylindrical lower electrode cut at one side; And And a top electrode formed on the phase change pattern. The method of claim 1, The cylindrical lower electrode is a phase change memory device, characterized in that the structure surrounding the side wall and the lower surface of the cylinder. The method of claim 1, The cylindrical lower electrode cut at one side is a phase change memory device, characterized in that the crescent shape, C shape or (shape when viewed in plan view. The method of claim 1, And the lower pattern is a diode and a diode electrode sequentially stacked. The method of claim 1, And the lower pattern is a contact plug in contact with the substrate and a conductive pattern on the contact plug. The method of claim 5, wherein And a transistor electrically connected to the lower pattern on the substrate. The method of claim 1, The insulating pattern is a trench that cuts one side of the cylindrical lower electrode in a vertical direction and penetrates the interlayer insulating film to expose a portion of the upper surface of the lower pattern and the cut sidewall of the cylindrical lower electrode cut at one side. A phase change memory device, characterized in that arranged to fill the structure. The method of claim 1, The insulating pattern is disposed to fill a trench structure in which one side of the cylindrical lower electrode is cut in the vertical direction and exposes an upper surface and a sidewall of the cut region of the cylindrical lower electrode, in which the one side is cut, in the interlayer insulating film. A phase change memory device, characterized in that. A substrate having lower patterns; An interlayer insulating film covering the substrate having the lower patterns; Cylindrical lower electrodes penetrating the interlayer insulating layer and disposed on the lower patterns, respectively; Line-type insulating patterns disposed in the interlayer insulating film while cutting one side of the cylindrical lower electrodes in a vertical direction along a row direction or a column direction; Phase change patterns formed to contact the upper portions of the cylindrical lower electrodes cut at one side thereof; And And a top electrode formed on each of the phase change patterns. The method of claim 9, The cylindrical lower electrodes have a structure surrounding the side wall and the bottom surface of the cylinder. The method of claim 9, Each of the cylindrical lower electrodes cut at one side has a crescent shape, a C shape, or a shape when viewed in plan. The method of claim 9, And the cylindrical lower electrodes cut at one side thereof have a C C C array in which the same portions are cut and uniformly arranged in plan view. The method of claim 9, And the phase change patterns extend in a direction parallel to the cutting plane of the cylindrical lower electrodes whose one side is cut or in a vertical direction of the cutting plane. The method of claim 9, The line-shaped insulating patterns cut through one side of the cylindrical lower electrodes in a vertical direction to expose a portion of the upper surface of the lower patterns and the cut sidewalls of the cylindrical lower electrodes with one side cut through the interlayer insulating layer. And a phase change memory device arranged to fill each of the linear trench structures. The method of claim 9, The line insulating patterns may include line trench structures exposing top surfaces and sidewalls of the cut regions of the cylindrical lower electrodes whose one side is cut in the interlayer insulating layer while cutting one side of the cylindrical lower electrodes in a vertical direction. A phase change memory element, characterized in that arranged to fill. Prepare a substrate with a lower pattern, An interlayer insulating film is formed on the substrate having the lower pattern, Forming a cylindrical lower electrode penetrating the interlayer insulating film to contact the lower pattern; An insulating pattern is formed in the interlayer insulating film to cut one side of the cylindrical lower electrode and the interlayer insulating film in a vertical direction; Form a phase change pattern in contact with the upper portion of the cylindrical lower electrode cut one side, A method of manufacturing a phase change memory device comprising forming an upper electrode on the phase change pattern. The method of claim 16, And the cylindrical lower electrode is formed to surround the side wall and the lower surface of the cylinder. The method of claim 16, The cylindrical lower electrode cut at one side is a crescent shape, a C shape or a manufacturing method of a phase change memory device, characterized in that (shaped) when viewed in plan view. The method of claim 16, And the lower pattern is formed of a diode and a diode electrode stacked in sequence. The method of claim 16, And the lower pattern is formed of a contact plug in contact with the substrate and a conductive pattern on the contact plug. The method of claim 20, And forming a transistor electrically connected to the lower pattern on the substrate. The method of claim 16, Forming the insulating pattern is Forming a trench structure by cutting one side of the cylindrical lower electrode and the interlayer insulating layer in a vertical direction to expose a portion of the upper surface of the lower pattern and the cut sidewall of the cylindrical lower electrode cut at one side; And forming an insulating film in the trench structure. The method of claim 16, Forming the insulating pattern is Forming a trench structure in which one side of the cylindrical lower electrode and the interlayer insulating film are cut in a vertical direction to expose an upper surface and sidewalls of the cut region of the cylindrical lower electrode, on which one side is cut, And forming an insulating film in the trench structure. The method of claim 16, Forming the cylindrical lower electrode A lower electrode contact hole is formed through the interlayer insulating layer to expose the upper portion of the lower pattern; Forming a lower electrode layer covering sidewalls and bottom surfaces of the lower electrode contact hole on the interlayer insulating layer having the lower electrode contact hole; Forming an internal insulating film filling the lower electrode contact hole on the substrate having the lower electrode film; And planarizing the internal insulating film and the lower electrode film until the upper surface of the interlayer insulating film is exposed. The method of claim 24, And planarizing the internal insulating film and the lower electrode film until the upper surface of the interlayer insulating film is exposed, and then performing an etch back process and a planarization process at least one or more times. . Prepare a substrate with lower patterns, An interlayer insulating film is formed on the substrate having the lower patterns, Cylindrical lower electrodes are formed on the lower patterns by penetrating the interlayer insulating film, Forming line type insulating patterns in the interlayer insulating film to cut one side of the cylindrical lower electrodes and the interlayer insulating film in a vertical direction along a row direction or a column direction; Forming phase change patterns in contact with the top of the cylindrical lower electrode is cut on one side, And forming upper electrodes on the phase change patterns, respectively. The method of claim 26, And the cylindrical lower electrodes are formed to surround sidewalls and a bottom surface of the cylinder. The method of claim 26, The cylindrical lower electrodes cut from one side are a crescent shape, a C shape or a shape of a phase change memory device when viewed in plan view. The method of claim 26, The cylindrical lower electrodes of which one side is cut are formed to have a C C C array in which the same portion is cut and uniformly arranged in plan view. The method of claim 26, And the phase change patterns are formed to extend in a direction parallel to the cut surfaces of the cylindrical lower electrodes whose one side is cut or in a vertical direction of the cut surfaces. The method of claim 26, Forming the line type insulating patterns Cutting one side of the cylindrical lower electrodes and the interlayer insulating layer in a vertical direction to form line trench structures exposing a portion of the upper surface of the lower patterns and the cut sidewalls of the cylindrical lower electrodes cut at one side; , And forming an insulating film in the line trench structures. The method of claim 26, Forming the line type insulating patterns Cutting one side of the cylindrical lower electrodes and the interlayer insulating layer in a vertical direction to form line trench structures exposing top surfaces and sidewalls of the cut regions of the cylindrical lower electrodes cut at one side thereof; And forming an insulating film in the line trench structures.

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