KR20060135191A - Double gate device manufacturing method - Google Patents

Abstract

The present invention provides a method for manufacturing a double gate device that can improve the device characteristics by suppressing the formation of the fringing field at the edge of the poly gate electrode. Providing a mask, forming a mask exposing a portion of the polysilicon layer on the polysilicon layer, and wherein the polysilicon layer concentration of an edge region of the polysilicon layer of the region exposed through the mask is And implanting a dopant into the polysilicon layer in a region exposed through the mask so as to be higher than the concentration of the polysilicon layer in the center.

Description

TECHNICAL FOR MANUFACTURING A DUAL GATE DEVICE

1 is a view for explaining the structure of a conventional poly gate electrode.

2 is an equivalent circuit diagram of FIG. 1.

3 is an experimental result of the dependence of the gate length and the total capacitance.

4 is a cross-sectional view illustrating a fringing field appearing in a poly gate electrode according to the prior art.

FIG. 5 is a conceptual view taken along the line II ′ of FIG. 4 to illustrate the boron doping profile in the poly depletion layer. FIG.

6A through 6D are cross-sectional views illustrating a method of manufacturing a double gate device according to an exemplary embodiment of the present invention.

7A-7C are conceptual views taken along the line II ′ of FIGS. 6A-6C to illustrate the boron profile inside the polysilicon layer.

8 is a conceptual view along the line II ′ shown in FIG. 6D to illustrate the boron profile inside the gate electrode.

<Explanation of symbols for the main parts of the drawings>

110: semiconductor substrate

120: gate oxide film

130: polysilicon layer

140: photoresist pattern

150: primary ion implantation process

160: secondary ion implantation process

170: tertiary ion implantation process

130a: P ⁺ poly gate electrode

G: gate area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a double gate device, and more particularly, to a method for manufacturing a dual poly gate device of a dynamic random access memory (DRAM) device.

In general, as the integration of semiconductor devices increases, the pitch of gates decreases during the processing of a complementary metal oxide semiconductor (CMOS) device using a silicon wafer. Accordingly, when the gate electrode and the gate oxide film are formed by using the existing material as it is through the conventional CMOS process, many problems occur. Recently, a change to the new material is urgently required.

First, look at the gate electrode from the perspective as follows.

In the CMOS device manufacturing process according to the prior art, each gate electrode of the NMOS device and the PMOS device has been formed of an n-type dopant doped polysilicon film. . As a result, the NMOS device has a surface channel characteristic, whereas the PMOS device has a buried channel characteristic. The PMOS device is very weak to short channel effects unlike NMOS devices having surface channel characteristics when the width of the gate electrode is narrowed to less than a half width of 100 nm due to the buried channel characteristics. .

Accordingly, in the fabrication process of a CMOS device having a narrow gate channel length in accordance with high integration of semiconductor devices, a double gate for forming a PMOS device with a p-type doped polysilicon film to realize a PMOS device with surface channel characteristics A dual gate structure has been proposed. This double gate structure solves the problem caused by the short channel effect.

However, various problems occur in the double gate structure, one of which is a threshold voltage shift and fluctuation due to boron penetration into the channel region. In addition, there is deterioration in device characteristics due to polysilicon depletion at the gate oxide film and the gate electrode interface. These problems are fundamentally due to the use of highly doped polysilicon material rather than metal as the gate electrode of the MOS structure. As such, a gate electrode formed using polysilicon is referred to herein as a poly gate electrode.

1 is a view for explaining the structure of a general poly gate electrode.

Referring to FIG. 1, a general poly gate electrode includes a gate oxide film 20 formed on a silicon substrate 10, a poly silicon film 30 formed on a gate oxide film 20, a gate oxide film 20, and a poly silicon. It is made of a poly depletion layer 25 formed between the films 30. Here, the gate voltage V _G is applied to the gate electrode, and the source voltage V _S is applied to the gate electrode.

The poly depletion layer 25 is formed when the dopant at the interface between the polysilicon film 30 and the gate oxide film 20 diffuses toward the gate oxide film 20, and is particularly well represented when manufacturing a PMOS device using boron. For example, since the boron has a greater diffusion to the oxide layer than other dopants, the depletion layer is well formed.

FIG. 2 is an equivalent circuit diagram of FIG. 1. Referring to FIG. 2, it can be seen that the poly depletion layer 25 of FIG. 1 functions as the first capacitor C _P and the gate oxide film 20 of FIG. 1 functions as the second capacitor C _acc . In addition, since the first and second capacitors C _P and C _acc are connected in series, the total capacitance C _inv (capacitance in an inversion state) may be expressed by Equation 1 below.

Accordingly, the charge amount Q _inv accumulated in the entire capacitor due to the voltage applied to the gate electrode and the channel may be expressed by Equation 2 below.

In addition, poly ball depletion layer can be expressed as the amount of charge (Q _acc) That is, the second capacitor is equation (3) to the amount of charge (Q _acc) of (C _acc) stored in (25, see FIG. 1). In the following, V _P refers to a drop voltage dropped by the first capacitor C _P.

As a result, the following Equation 4 can be obtained through Equations 2 and 3.

FIG. 3 recently reports on the dependence of gate length and parameter of equation (4) (CHChoi et al, Gate length dependent polysilicon depletion effects, vol 23, 224, IEEE, 2002). This is also an experimental result.

Referring to FIG. 3, it can be seen that as the gate length decreases, the total capacitance Q _inv decreases and V _P / (V _G −V _S ) increases. As shown in FIG. 4, as the gate length decreases, the dopant concentration at the poly gate electrode edge becomes inconsistent, thereby forming a fringing field (see 'F' region). Concatenate.

FIG. 5 is a conceptual diagram along the line II ′ of FIG. 4 to illustrate the boron doping profile in the poly depletion layer 25. Referring to FIG. 5, it can be seen that the boron concentration at the edge of the poly gate electrode is lower than the boron concentration at the center of the poly gate electrode. Thus, a fringing field is formed.

Here, referring to Equation 4, as the gate length decreases as described above, the total capacitance decreases, thereby increasing V _P. V _P is a drop voltage, and as the drop voltage increases, the threshold voltage changes, causing a problem of deterioration of device characteristics. In particular, when forming a PMOS device using boron, a fringing field is severely formed, and thus deterioration of device characteristics due to a decrease in gate length is increased.

Accordingly, the present invention has been made to solve the above problems of the prior art, to provide a method for manufacturing a double gate device that can improve the device characteristics by suppressing the formation of the fringing field at the edge of the poly gate electrode. The purpose is.

According to an aspect of the present invention, there is provided a semiconductor substrate on which a polysilicon layer is deposited, and forming a mask exposing a portion of the polysilicon layer on the polysilicon layer. And a dopant is applied to the polysilicon layer in the region exposed through the mask such that the concentration of the polysilicon layer in the edge region of the polysilicon layer in the region exposed through the mask is higher than the concentration of the polysilicon layer in the central portion. It provides a double gate device manufacturing method comprising the step of implanting.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween.

Example

6A through 6D are cross-sectional views illustrating a method of manufacturing a double gate device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 6A to 6D are the same elements having the same function.

First, as shown in FIG. 6A, an oxide process is performed to form a gate oxide film 120 on a semiconductor substrate 110. The oxidation process is performed by a wet oxidation method in which a silicon substrate is heated at a temperature of approximately 900 to 1000 ° C. in an oxidizing gas such as water vapor, or a dry oxidation method which is heated at a temperature of about 1200 ° C. using pure oxygen as an oxidizing gas. Conduct.

Subsequently, a polysilicon layer 130 is deposited on the gate oxide film 120. In this case, the polysilicon layer 130 is deposited by LPCVD (Low Pressure Chemical Vapor Deposition) method using SiH ₄ as undoped silicon.

Subsequently, after the photoresist (not shown) is coated on the polysilicon layer 130, the photoresist pattern 140 is formed by performing an exposure and development process using a photomask (not shown). In this case, the photoresist pattern 140 has a structure in which the gate region G in which the gate electrode is to be formed is opened.

Subsequently, a first ion implantation process 150 using the photoresist pattern 140 as an ion implantation mask is performed to dope boron in the polysilicon layer 130 of the gate region G. At this time, the primary ion implantation process 150 is performed in the vertical direction to uniformly doped boron to the entire polysilicon layer 130 of the gate region (G).

As such, when the boron is uniformly doped in the entire polysilicon layer 130 of the gate region G, the boron profile inside the polysilicon layer 130 is illustrated in FIG. 7A. FIG. 7A is a conceptual diagram illustrating the boron doping concentration distribution in the doped polysilicon layer 130 along the line II ′ of FIG. 6A.

Referring to FIG. 7A, after the primary ion implantation process in the vertical direction, the doping concentration distribution in the polysilicon layer of the doped region is uniform.

Subsequently, as illustrated in FIG. 6B, a second ion implantation process 160 using the photoresist pattern 140 as an ion implantation mask is performed to the right edge region of the polysilicon layer 130 of the gate region G. Doping boron. As a result, the boron doping concentration of the right edge region of the doped polysilicon layer 130 is increased.

Here, the secondary ion implantation process 160 determines the region to be doped by adjusting the inclination angle.

As described above, when the boron is doped in the right edge region of the polysilicon layer 130 of the gate region G, the boron profile inside the polysilicon layer 130 is illustrated in FIG. 7B. FIG. 7B is a conceptual view taken along the line II ′ of FIG. 6B to explain the boron doping concentration distribution in the doped polysilicon layer 130.

Referring to FIG. 7B, it can be seen that the boron doping concentration of the right edge region of the doped polysilicon layer 130 is increased after the secondary ion implantation process having the inclination angle.

Subsequently, as shown in FIG. 6C, a third ion implantation process 170 using the photoresist pattern 140 as an ion implantation mask is performed to form the left edge region of the polysilicon layer 130 of the gate region G. Doping boron. As a result, the boron doping concentration of the left edge region of the doped polysilicon layer 130 is increased.

Here, the tertiary ion implantation process 170 determines the region to be doped by adjusting the inclination angle.

As such, when the boron is doped in the left edge region of the polysilicon layer 130 of the gate region G, the boron profile inside the polysilicon layer 130 is illustrated in FIG. 7C. FIG. 7C is a conceptual view taken along the line II ′ of FIG. 6C to explain the boron doping concentration distribution in the doped polysilicon layer 130.

Referring to FIG. 7C, after the third ion implantation process having the inclination angle, boron doping concentration of the left edge region of the doped polysilicon layer 130 is increased.

Subsequently, as shown in FIG. 6D, a strip process is performed to remove the photoresist pattern 140 (see FIG. 6C).

Subsequently, a photoresist (not shown) is coated on the polysilicon layer 130, and then a photoresist pattern (not shown) is formed by performing an exposure and development process using a photomask (not shown). At this time, the photoresist pattern is formed to cover the gate region (G).

Subsequently, an etch process using a photoresist pattern as an etching mask is performed to etch the undoped polysilicon layer 130 (see FIG. 6C). As a result, the P ⁺ poly gate electrode 130a doped with boron is formed.

Subsequently, although not shown in the drawing, a conductive layer and a hard mask may be further formed on the P ⁺ poly gate electrode 130a. In this case, the conductive layer may be formed of any one selected from the group consisting of tungsten silicide (WSi _X , _X is 1 to 10), tungsten (W), and Mo (Molybdenum).

Next, although not shown in the figure, an oxidation process is performed to form an oxide film surrounding the P ⁺ poly gate electrode 130a.

In this way, the boron is out-diffused during the oxidation process for forming the oxide film, so that more boron escapes from the edge region than at the center of the P ⁺ poly gate electrode 130a.

However, since to the preferred embodiment of the present invention it is already higher than the boron doping concentration of the central portion of the P ⁺ poly gate electrode (130a) the boron doping concentration of the edge region P ⁺ poly gate electrode (130a) of the boron in the edge area It doesn't matter if you get away with this a lot.

Therefore, as shown in FIG. 8, the boron doping concentration in the P ⁺ poly gate electrode 130a becomes uniform. FIG. 8 is a conceptual view taken along the line II ′ of FIG. 6D.

That is, according to a preferred embodiment of the present invention, the doping concentration in the edge region of the gate electrode is increased in advance so that the doping concentration in the edge region of the gate electrode is higher than the doping concentration in the center portion of the gate electrode. When the dopant escapes from the edge region more than the center portion of the gate electrode, it does not become a problem. Therefore, the dopant doping concentration in the gate electrode becomes uniform, so that the formation of the fringing field can be suppressed, thereby improving device characteristics.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the doping concentration in the edge region of the gate electrode is increased in advance so that the doping concentration in the edge region of the gate electrode is higher than the doping concentration in the center portion of the gate electrode. When the dopant escapes from the edge region more than the center portion of the gate electrode, it does not become a problem. Therefore, the dopant doping concentration in the gate electrode becomes uniform, so that the formation of the fringing field can be suppressed, thereby improving device characteristics.

Claims (7)

Providing a semiconductor substrate having a polysilicon layer deposited thereon; Forming a mask on the polysilicon layer to expose a portion of the polysilicon layer; And Dopants are injected into the polysilicon layer exposed through the mask such that the concentration of the polysilicon layer in the edge region of the polysilicon layer exposed through the mask is higher than the concentration of the polysilicon layer in the center portion. step Double gate device manufacturing method comprising a. The method of claim 1, wherein injecting a dopant into the polysilicon layer, Implanting a dopant in the vertical direction to the polysilicon layer in the area exposed through the mask; And Implanting the dopant into the edge of the polysilicon layer in the area exposed through the mask to increase the dopant concentration at the edge of the polysilicon layer A double gate device manufacturing method consisting of. The method of claim 2, Injecting the dopant in the edge of the polysilicon layer, The doping region is determined by adjusting the inclination angle during the dopant injection method. The method of claim 2 or 3, Injecting the dopant to the edge of the polysilicon layer, Implanting the dopant into a region on the first side of the polysilicon layer in the region exposed through the mask; And Implanting the dopant into a second side region opposite to the first side of the polysilicon layer in the region exposed through the mask Double gate device manufacturing method comprising a. The method according to claim 1 or 2, And injecting the dopant into the polysilicon layer and then etching the polysilicon layer in a region where the dopant is not implanted. The method according to claim 1 or 2, The dopant is a double gate device manufacturing method using boron. The method according to claim 1 or 2, Wherein the polysilicon layer is a gate electrode material.

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