KR20060054511A - Direct charge injection type memory device and its manufacturing and operation method - Google Patents

Abstract

Disclosed are a direct charge injection type memory device and a method of manufacturing and operating the same. The present invention discloses spaced apart first and second channel layers, a conductive layer connecting them, a pad conductive layer connected to the first channel layer, a charge storage layer connected to the second channel layer, and the first channel. A first gate for controlling the on-off of the layer and a second gate for controlling the on-off of the second channel layer and relating to concentration of charge to the charge storage layer and release of charge from the charge storage layer. Provided are a memory device, and a method of manufacturing and operating the same.

Description

Memory device injecting charge directly and methods of manufacturing and operating the same}

1 to 3 are cross-sectional views of a direct charge injection type memory device according to the first to third embodiments of the present invention, respectively.

4 through 12 are cross-sectional views illustrating a method of manufacturing the memory device illustrated in FIG. 1 step by step.

13 to 17 are cross-sectional views related to a method of operating the memory device illustrated in FIG. 1.

FIG. 18 is a plan view of a 4-bit array consisting of the memory elements shown in FIG.

* Description of Signs of Major Parts of Drawings *

20, 60: lower electrode (substrate) 24, 40, 62: pad conductive layer

22, 42, 66: first channel layer (first phase transition layer)

28, 46, 70, 92: second channel layer (second phase transition layer)

26, 44, 64: conductive layer 30, 48, 68, 94: charge storage layer

32, 74: upper electrode 34, 76: interlayer insulating layer                 

54: first electrode 52: insulating layer

50: second electrode 72: intermediate electrode

34a, 34b, 34c: first to third insulating layers

80, 88: First and second conductive layers A1, A2: First and second regions

82, 90: photosensitive film pattern

80a and 80b: first and second patterns of the first conductive layer 80

84: beer hole 86: conductive plug

88a: second conductive layer pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a memory device in which a transistor is unnecessary by a charge direct injection type and a method of manufacturing and operating the same.

 The ideal memory device is capable of high integration and reliability, high-speed operation, low voltage drive, low power consumption, and long-term storage of stored data.

The memory devices introduced to date do not satisfy all the requirements of such an ideal memory device, but recently, the boundary between volatile memory devices and nonvolatile memory devices is blurred, and in many cases, they are approaching ideal memory devices.

A typical example is a SONOS memory device used as a flash memory. Since the Sonos memory device has a field effect transistor structure and a storage node at a gate, a separate node for data storage is not necessary. Therefore, the Sonos memory device has the advantage of higher directness and nonvolatileness than the conventional DRAM composed of transistors and capacitors.

However, in the case of a source memory device, in order to store data, electrons flowing in a channel between the source and the drain must be trapped in a storage node in the gate, which must pass through the tunneling layer. In addition, even when the stored data is erased, electrons emitted from the storage node must pass through the tunneling layer. Therefore, there is a limit in performing data write and erase operations at high speed. In addition, when the tunneling film deteriorates during the repetitive operation, data writing and erasing operations may occur at a voltage different from the predetermined voltage, which may lower the reliability of the operation.

The technical problem to be achieved by the present invention is to improve the above-described problems of the prior art, it is possible to ensure high-speed operation and high reliability with high integration, low voltage operation, can reduce the power consumption direct charge An implantable memory device is provided.

Another object of the present invention is to provide a method of manufacturing such a memory device.

Another object of the present invention is to provide a method of operating the memory device.

In order to achieve the above technical problem, the present invention provides spaced apart first and second channel layers, a conductive layer connecting them, a pad conductive layer connected to the first channel layer, and a charge storage connected to the second channel layer. A layer and a relationship between concentration of charge in the charge storage layer and release of charge from the charge storage layer controlling on and off of the first gate and the second channel layer controlling on and off of the first channel layer. It provides a memory device comprising a second gate.

The first and second gates and the pad conductive layer may be provided in parallel. Alternatively, the first and second gates may be vertically disposed, and the pad conductive layer and the second gate may be provided in parallel.

The first and second channel layers may be provided in parallel or vertically.

The first and second channel layers may be phase transition layers in which physical properties change from conductive to insulating or vice versa under an electric field of a predetermined intensity. In this case, the phase transition layer may be a vanadium oxide (VOx) layer or a nickel oxide (Ni0x) layer.

The charge storage layer may be any one of a metal layer and a polysilicon layer.

The second gate may be divided into a first portion that controls on and off of the second channel layer, and a second portion that is related to concentration of charges to the charge storage layer and release of charge from the charge storage layer. have. In this case, the first channel layer and the second channel layer may be vertical, and the charge storage layer and the second channel layer may be provided in parallel.                     

In order to achieve the above technical problem, the present invention is a step of forming a first gate, forming a first insulating layer on the first gate, the conductive first and second spaced apart on the first insulating layer Forming a pattern, forming a first channel layer on the first insulating layer between the first and second patterns, on the first insulating layer, the first and second patterns and the first channel Forming a second insulating layer covering the layer, forming a via hole in which the second pattern is exposed in the second insulating layer, filling the via hole with a conductive plug, and forming the conductive plug on the second insulating layer Forming a conductive layer pattern, a second channel layer, and a charge storage layer, each of which is in contact with each other, the conductive layer pattern on the second insulating layer, and the second channel layer; A third insulating layer covering the charge storage layer; And forming a second gate on the third insulating layer, and exposing a portion of the first pattern.

According to another aspect of the present invention, there is provided a method of forming a first gate having a predetermined thickness, forming a first insulating layer on the first gate, and a first channel layer on the first insulating layer. Forming a second insulating layer covering the conductive layer pattern and the first channel layer on the first insulating layer, and forming a second insulating layer on the first insulating layer. Forming the exposed via holes, filling the via holes with conductive plugs, and forming a second channel layer and a charge storage layer covering the exposed front surface of the conductive plugs on the second insulating layer, and being in contact with each other. Forming a third insulating layer covering the second channel layer and the charge storage layer on the second insulating layer, forming a second gate on the third insulating layer, and forming the conductive layer. Pattern work To provide a method of manufacturing a memory device comprising the step of exposing.

The present invention also provides a step of forming a groove having a predetermined depth in the first insulating layer, filling the groove with a conductive layer, and forming a first channel layer on a predetermined region of the conductive layer in order to achieve the above technical problem. And forming a first gate facing the first channel layer on the first insulating layer adjacent to the first channel layer, wherein the conductive layer, the first channel layer, and the first insulating layer are formed on the first insulating layer. Forming a second insulating layer covering a first gate, planarizing an upper surface of the second insulating layer to expose the first channel layer, and forming the first channel on different regions of the second insulating layer Forming a conductive layer pattern covering the exposed portion of the layer, and a second channel layer and a charge storage layer, each of which is in contact with each other, wherein the conductive layer pattern, the second channel layer, and the second insulating layer are formed on the second insulating layer. A third covering the charge storage layer The method comprising sequentially stacking the yeoncheung and a second gate, and provides a process for the production of a memory device comprising the steps of exposing a portion of the conductive layer.

According to another aspect of the present invention, there is provided a method of forming a first gate having a predetermined thickness, forming a first insulating layer on the first gate, and forming a conductive first layer on the first insulating layer. And forming a second pattern, forming a first channel layer on the first insulating layer between the first and second patterns, and forming the first and second patterns on the first insulating layer. Forming a second insulating layer covering the first channel layer, polishing the second insulating layer until the top surface of the second pattern is exposed, and the second insulating layer adjacent to the exposed second pattern Forming a second channel layer and a second gate on the layer to face the second channel layer, respectively, forming a third insulating layer on the second insulating layer to cover the second channel layer and the second gate; When the upper surface of the insulating layer is planarized to expose the second channel layer Forming a charge storage layer covering the exposed surface of the second channel layer on the third insulating layer, and forming a fourth insulating layer covering the charge storage layer on the third insulating layer. And forming an electrode layer on the fourth insulating layer.

In such manufacturing methods, at least one of the first and second channel layers may be formed as a phase change layer in which physical properties vary from conductive to insulating to vice versa under an electric field of a predetermined intensity. In this case, the phase transition layer may be formed of a vanadium oxide (VOx) layer or nickel oxide (NiOx).

In addition, the charge storage layer may be formed of any one of a metal layer and a polysilicon layer.

In order to achieve the above technical problem, the present invention provides a first and second channel layer, a conductive layer connecting them, a pad conductive layer connected to the first channel layer, and a charge storage connected to the second channel layer. Layer, a first gate that controls on and off of the first channel layer, and controls on and off of the second channel layer and concentrates charge on the charge storage layer and release of charge from the charge storage layer. CLAIMS What is claimed is: 1. A method of operating a memory device including an associated second gate, comprising: a first step of applying a predetermined write voltage to the first and second gates, respectively, to convert physical properties of the first and second channel layers to conductive; And a second step of maintaining a predetermined potential difference between the charge storage layer and the pad conductive layer to allow charge to flow into the charge storage layer.

In this operation method, after the second step, the third step of changing the physical property of the first channel layer to be insulating by adjusting the voltage applied to the first gate and the second voltage by adjusting the voltage applied to the second gate The method may further include a fourth step of changing the physical properties of the two channel layer to insulation.

In order to achieve the above technical problem, the present invention provides a first and second channel layer, a conductive layer connecting them, a pad conductive layer connected to the first channel layer, and a charge storage connected to the second channel layer. Layer, a first gate that controls on and off of the first channel layer, and controls on and off of the second channel layer and concentrates charge on the charge storage layer and release of charge from the charge storage layer. 1. A method of operating a memory device including a second gate, wherein the method comprises: a first step of applying a predetermined read voltage to the first and second gates, respectively, to change physical properties of the first and second channel layers to conductive; And maintaining a predetermined potential difference between the charge storage layer and the pad conductive layer so that the charge stored in the charge storage layer is discharged. It provides.

After the second step, the third step of changing the physical property of the first channel layer to insulating by adjusting the voltage applied to the first gate and the property of the second channel layer by adjusting the voltage applied to the second gate. It may further comprise a fourth step of changing to an insulating.

In addition, a refresh process may be further performed after the fourth step to restore the state of the charge storage layer to its original state.

With this invention, since the charges used for data recording, that is, the electrons do not suffer from tunneling, data can be recorded at high speed, and the recorded data can be erased at high speed. In addition, since the tunneling film is not used, there is no need to consider a problem due to deterioration of the tunneling film. In addition, since the charge is directly injected to the storage node without passing through the tunneling film, the operating voltage can be lowered and power consumption can be reduced than when passing through the tunneling film.

Hereinafter, a direct charge injection type memory device and a method of manufacturing and operating the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

First, the direct charge injection type memory device according to the first to third embodiments of the present invention will be described.

<First Embodiment>

Referring to FIG. 1, an interlayer insulating layer 34 and an upper electrode 32 are sequentially stacked on the lower electrode 20. The interlayer insulating layer 34 may be, for example, a silicon oxide layer. In the interlayer insulating layer 34 are first and second channel layers 22, 28, and a charge storage layer 30 in which charge, for example electrons, is stored, and the first and second channel layers 22, 28 are present. ) And a pad conductive layer 24 connected to a bit line (not shown) connected to an external sensing means. A portion of the top surface of the pad conductive layer 24 is exposed out of the interlayer insulating layer 34 for the bit line connection. In the interlayer insulating layer 34, the first channel layer 22 contacts one end of the pad conductive layer 24 to form a lower layer, and the second channel layer 22 contacts the charge storage layer 30 to form an upper layer. To form. The lower layer and the upper layer are vertically spaced apart. The first and second channel layers 22 and 28 are preferably provided on the same vertical line, but may not necessarily be located on the same vertical line. The lower electrode 20 and the upper electrode 32 may be metal electrodes or semiconductor electrodes doped with impurities such as polysilicon electrodes to have sufficient conductivity. In addition, the conductive layer 26 connecting the pad conductive layer 24 to the first and second channel layers 22 and 28 may be the same metal layer, for example, an aluminum layer, a copper layer, a silicide layer, or an alloy layer. The first and second channel layers 22 and 28 are material layers whose physical properties change from conductive to insulating or vice versa according to the voltage applied to the lower and upper electrodes 20 and 32, respectively (hereinafter referred to as phase transition layers). Is preferable. As a result, since the on and off of each of the first and second channel layers 22 and 28 are controlled by the lower and upper electrodes 20 and 32, the lower electrode 20 may control the first channel layer 22. With one gate, the upper electrode 32 can be seen as a second gate that controls the second channel layer 28. The upper electrode 32 extends above the charge storage layer 30 and is also involved in concentration of electrons to the charge storage layer 30 or emission of electrons concentrated in the charge storage layer 30. Preferably, the first and second channel layers 22 and 28 are all the same phase transition layer, for example, vanadium oxide film VOx, but may be different phase transition layers having the same voltage range required for phase transition within a given range. The charge storage layer 30 may include the pad conductive layer 24 and the first channel while voltages are applied to the lower and upper electrodes 20 and 32 such that both the first and second channel layers 22 and 28 are conductive. The material layer for storing electrons flowing through the layer 22, the conductive layer 26, and the second channel layer 28 may be a metal layer or a polysilicon layer. After the electrons are stored in the charge storage layer 30, the voltage applied to the lower electrode 20 is adjusted so that the first channel layer 22 is insulative, and thus the charge storage layer 30 is formed in the pad conductive layer 24. Since the electron flow path leading to) is blocked in the first channel layer 22, the electrons stored in the charge storage layer 30 maintain the initial stored state. In addition, even when no voltage is applied to the lower and upper electrodes 20 and 32, the first and second channel layers 22 and 28 have an off state, that is, an insulating property, and thus are stored in the charge storage layer 30. The former maintains its initial state. In other words, even if the power is removed, the state of the charge storage layer 30 is maintained as it is. In other words, when a predetermined bit data is written in the memory device shown in FIG. 1 when electrons are stored in the charge storage layer 30, the predetermined bit data written in the memory device is stored in the memory device. Even if the power supply to the power supply is cut off, it is not volatilized and remains as it is.

On the other hand, after the electrons are stored in the charge storage layer 30, when the voltage is applied to the lower and upper electrodes 20, 32 so that the first and second channel layers 22, 28 are on, that is, conductive. Since the entire electron flow path is conductive, electrons stored in the charge storage layer 30 flow along the path, and the flow of electrons is detected by sensing means connected to the conductive pad 24.

Second Embodiment

Referring to FIG. 2, the direct charge injection type memory device according to the second embodiment of the present invention is provided on the insulating layer 52 and the insulating layer 52 including a plurality of members together with the first electrode 54. And a second electrode 50. The insulating layer 52 includes the pad conductive layer 40, the first and second channel layers 42 and 46, the conductive layer 44 connecting the first and second channel layers 42 and 46, and the charge storage layer. (48). A portion of the upper surface of the pad conductive layer 40 is exposed outside the insulating layer 52. The insulating layer 52 may be, for example, a silicon oxide layer. In the insulating layer 52, the conductive layer 44, the second channel layer 46, and the charge storage layer 48 form one layer or one line corresponding to the pad conductive layer 40. The one layer consisting of the conductive layer 44, the second channel layer 46, and the charge storage layer 48 is spaced perpendicularly from the pad conductive layer 40 by a given distance and is the same as the pad conductive layer 40. It is preferably provided on a vertical line, but may not be on the vertical line. The first channel layer 42 is formed of a conductive layer 44, a second channel layer 46, and a charge storage layer 48 between the pad conductive layer 40 and the pad conductive layer 40. One end of 42 is connected vertically. In this way, an electron flow path is created between the pad conductive layer 40 and the charge storage layer 48 via the first channel layer 42, the conductive layer 44, and the second channel layer 46. The first electrode 54 is provided perpendicular to the first channel layer 42 in close proximity to the first channel layer 42. The first electrode 54 plays the same role as the lower electrode 20 of the memory device according to the first embodiment. In addition, the second electrode 50 plays the same role as the upper electrode 32 of the memory device according to the first embodiment. In addition, the first and second channel layers 42 and 46 are preferably the same as the first and second channel layers 22 and 28 of FIG. 1, respectively, according to the first embodiment. The charge storage layer 48 is also preferably the same as the charge storage layer 30 of the memory device shown in FIG.

Third Embodiment

Referring to FIG. 3, an interlayer insulating layer 76 including an intermediate electrode 72 is present on the lower electrode 60, and an upper electrode 74 is present on the interlayer insulating layer 76. The interlayer insulating layer 76 may include the first and second channel layers 66 and 70, the pad conductive layer 62, the charge storage layer 68, and the first and second channel layers 66, in addition to the intermediate electrode 72. And a conductive layer 64 connecting the 70. In the interlayer insulating layer 76, the conductive layer 64, the first channel layer 66, and the pad conductive layer 62 are provided above the lower electrode 60 and form one layer. A portion of the upper surface of the pad conductive layer 62 is exposed outside the interlayer insulating layer 76. The lower electrode 60 is used to change the physical properties of the first channel layer 66 from conductive to insulating or vice versa, and serves as a first gate to control on / off of the first channel layer 66. Therefore, the thickness of the interlayer insulating layer 76 between the first channel layer 66 and the lower electrode 60 is preferably thin for reliable control of the first channel layer 66. The first channel layer 66 is provided between the conductive layer 64 and the pad conductive layer 62 and is in contact with both. The charge storage layer 68 is vertically spaced apart from the one layer consisting of the conductive layer 64, the first channel layer 66, and the pad conductive layer 62, and is provided in parallel with the one layer. The second channel layer 70 is provided at a position where the two are vertically connected between the charge storage layer 68 and the conductive layer 64. The intermediate electrode 72 is provided close to the second channel layer 70 and changes the physical properties of the second channel layer 70 according to the degree of voltage applied from the outside. In other words, the intermediate electrode 72 serves as a second gate for controlling the on and off of the second channel layer 70. Preferably, the lower electrode 60, the intermediate electrode 72, and the upper electrode 74 are all the same metal electrode, but may be different metal electrodes, and the same as the lower and upper electrodes 20 and 32 of the first embodiment. It may be a doped semiconductor layer. The first and second channel layers 66 and 70 may be the same as the first and second channel layers 22 and 28 of FIG. 1. In addition, the charge storage layer 68 may be the same as the charge storage layer 30 of FIG. 1. The same applies to the pad conductive layer 62.

Next, a method of manufacturing the memory device of the present invention described above will be described.

Referring to FIG. 4, a first insulating layer 34a is formed on the substrate 20. The substrate 20 is a conductive substrate, for example, can be formed of a metal substrate. The substrate 20 is used as a lower electrode. The first conductive layer 80 is formed on the first insulating layer 34a. Subsequently, the photosensitive film pattern 82 is formed on the first conductive layer 80 to expose the spaced apart first and second regions A1 and A2 of the first conductive layer 80 by using a photographic and developing process. . The exposed first and second regions A1 and A2 of the first conductive layer 80 are etched using the photoresist pattern 82 as an etching mask. The etching is performed until the first insulating layer 34a is exposed. 5 shows the etching result. Referring to FIG. 5, it can be seen that the first conductive layer 80 is separated into a first pattern 80a and a second pattern 80b by the etching. After the etching, the photoresist pattern 82 is removed.

Next, referring to FIG. 6, a first phase change layer 22 is formed on the first insulating layer 34a between the first and second patterns 80a and 80b. The first phase transition layer 22 is preferably formed of a vanadium oxide (VOx) layer, but may be formed of another phase transition layer, for example, a nickel oxide layer. The first phase transition layer 22 may be formed at the same height as the first and second patterns 80a and 80b. Thereafter, a second insulating layer 34b is formed on the first insulating layer 34a to cover the first and second patterns 80a and 80b and the first phase transition layer 22. The second insulating layer 34b may be formed of a predetermined insulating layer, for example, a silicon oxide layer, together with the first insulating layer 34a. After forming the second insulating layer 34b, the via hole 84 exposing the second pattern 80b is formed in the second insulating layer 34b by using a photolithography and an etching process. Subsequently, as shown in FIG. 7, the via hole 84 is filled with the conductive plug 86. The conductive plug 86 may be formed of the same conductive material as the second pattern 80b, but may be formed of another conductive material. Subsequently, a second conductive layer 88 is formed on the second insulating layer 34b which contacts the conductive plug 86, preferably covering the exposed entire surface of the conductive plug 86. The second conductive layer 88 is preferably formed of the same conductive material as the first conductive layer (20 in FIG. 4), but may be formed of a doped semiconductor material layer, such as a doped silicon layer, to have sufficient conductivity. A photosensitive film pattern 90 defining a predetermined region of the second conductive layer 88 is formed on the second conductive layer 88. The photosensitive film pattern 90 is formed above the conductive plug 86. The exposed portion of the second conductive layer 88 is etched using the photoresist pattern 90 as an etch mask. As a result, as shown in FIG. 8, the second insulating layer 34b around the photosensitive film pattern 90 is exposed, and the agent covering the exposed entire surface of the conductive plug 86 on the second insulating layer 34b. 2 conductive layer patterns 88a are formed. After the etching, the photoresist pattern 90 is removed.

Next, referring to FIG. 9, the second phase change layer 92 and the charge storage layer 94 are formed on the second insulating layer 34b exposed by the etching for forming the second conductive layer pattern 88a. Form. The second phase change layer 92 may be formed of the same material as the first phase change layer 22, but may be formed of another phase change material layer. The second phase transition layer 92 may be formed at a position corresponding to the first phase transition layer 22 and in contact with the second conductive layer pattern 88a. The charge storage layer 94 may be formed of a metal layer or a polysilicon layer. The charge storage layer 94 may be formed in a line shape, but may be formed in various shapes such as other shapes such as squares, circles, and triangles. The charge storage layer 94 stores electrons via the second phase change layer 92. Accordingly, the charge storage layer 94 is formed at a position spaced apart from the second conductive layer pattern 88a and is in contact with the second phase change layer 94. Since a part of the first pattern 80a needs to be exposed in a subsequent etching process, the charge storage layer 94 is formed to have a length shorter than the first pattern 80a in consideration of this. The second phase transition layer 92 and the charge storage layer 94 may be formed by applying a conventional material layer stacking process, planarization process, and etching process. In this case, the second phase transition layer 92 and the charge storage layer 94 may be formed at the same height as the second conductive layer pattern 88a.

Next, referring to FIG. 10, a third insulating layer 34c covering the second conductive layer pattern 88a, the second phase change layer 92, and the charge storage layer 94 is formed on the second insulating layer 34b. It forms, and the whole surface is planarized. The planarization makes the thickness of the portion formed on the second conductive layer pattern 88a, the second phase change layer 92 and the charge storage layer 94 of the third insulating layer 34c as thin as possible. However, the second conductive layer pattern 88a, the second phase change layer 92, and the charge storage layer 94 are not exposed. The third conductive layer 32 is formed on the planarized third insulating layer 34c. The third conductive layer 32 is preferably formed of a metal layer, but may be formed of a doped semiconductor layer, such as a doped polysilicon layer, to obtain sufficient conductivity. The third conductive layer 32 is used as the upper electrode.

Next, as illustrated in FIG. 11, a photosensitive film pattern 96 is formed on the third conductive layer 32. The photoresist pattern 96 is formed as an etching mask for exposing only a part of the first pattern 80a. Accordingly, the photosensitive film pattern 96 may be formed on the third conductive layer 32 to cover the second conductive layer pattern 88a, the second phase change layer 92, and the charge storage layer 94.

Next, the exposed portion of the third conductive layer 32 and the formed third insulating layer 34c and the second insulating layer 34b are sequentially removed using the photoresist pattern 96 as an etching mask. As a result, as shown in FIG.

A portion of the first pattern 80a is exposed. The bit line is connected to the exposed portion of the first pattern 80a.

A method of manufacturing a memory device according to the second and third embodiments of the present invention is to form a first channel layer (42 in FIG. 2) or a second channel layer (70 in FIG. 3) and the intermediate electrode (54, 72) Except for the process, since it is not significantly different from the manufacturing method of the memory device according to the first embodiment described above, a detailed description of the manufacturing method of the memory device according to the second and third embodiments is omitted. In the memory device of the second embodiment or the memory device of the third embodiment, the first channel layer 42 or the second channel layer 70 is formed on the interlayer insulating layer 52 or 76 with the pad conductive layer 40 or the conductive layer 64. ) May be formed, and then fill the via hole with a phase change layer. The intermediate electrodes 54 and 72 may also be formed in the interlayer insulating layer 52 or 76 to a predetermined depth, and then fill the grooves with a conductive material.

Next, an operation method of the memory device of the present invention described above will be described.

Since the operating principles of the memory devices according to the first to third embodiments are the same, the operation method of the memory device according to the first embodiment will be described. Instead.

First, the basic operation of the memory device of the present invention will be described.

As shown in FIG. 13, when the first voltage V1 is applied to the lower electrode 20 and the second voltage V2 is applied to the upper electrode 32, the first and second voltages V1, When V2) is greater than or equal to a threshold voltage for changing the physical properties of the first and second channel layers 22 and 28 from insulating to conductive, the first conductive channel 22a is formed in the first channel layer 22, and the second The second conductive channel 28a is also formed in the channel layer 92. In this manner, when electrons are stored in the charge storage layer 94, the electrons pass through the second channel layer 92, the conductive layer 26, the first channel layer 22, and the pad conductive layer 24. Flowing to 24 is detected by sensing means (not shown) connected to the pad conductive layer. In the opposite case, electrons are stored in the charge storage layer 30 in the external source via the pad conductive layer 24, the first channel layer 22, the conductive layer 26 and the second channel layer 28.

However, when at least one of the first and second voltages V1 and V2, for example, the first voltage V1 is lower than the phase transition voltage of the first channel layer 22, for example, 0V, the charge storage layer 30 Since the current flow path connecting the pad conductive layer 24 is blocked at the first channel layer 22, electrons are discharged from the charge storage layer 30 to the outside or the electrons are stored in the charge storage layer 30. Everything you do is impossible. In other words, the charge storage layer 30 maintains the state immediately before the first channel layer 22 is blocked. In FIG. 13, reference numeral I denotes a flow of electrons emitted from the charge storage layer 30.

<Write>

Referring to Figure 14,

A predetermined write voltage, for example 5V, is applied to the lower electrode 20 and the upper electrode 32, respectively. The pad conductive layer 24 is kept at 0V. Under such voltage conditions, first and second conductive channels 22a and 28a are formed in the first and second channel layers 22 and 28, respectively, and are formed between the charge storage layer 30 and the pad conductive layer 24. A potential difference is formed so that electrons are stored in the charge storage layer 30 through the first channel layer 22, the conductive layer 26, and the second channel layer 28 in the pad conductive layer 24. Reference numeral I1 denotes the flow of electrons. When the electrons are stored in the charge storage layer 30 in this manner, it is assumed that bit data 1 is written in the memory element of the present invention.

In the state where electrons are stored in the charge storage layer 30, as shown in FIG. 15, when the voltage applied to the lower electrode 20 is maintained at 0 V, the physical properties of the first channel layer 22 are conductive to insulating. The first conductive channel 22a disappears in the first channel layer 22. In other words, the first channel layer 22 is entirely insulated. As a result, the flow of electrons I1 is blocked. Subsequently, when the voltage applied to the upper electrode 32 is also maintained at 0V, the electrons stored in the charge storage layer 30 are kept in the isolated state. In other words, the bit data 1 written in the memory element of the present invention is not volatilized even if the voltage applied first disappears, and remains as it was originally written.

<Read>

Referring to FIG. 16, a predetermined read voltage, eg, at the lower electrode 20, in which electrons are stored in the charge storage layer 30 of the memory device of the present invention, in which bit data 1 is written in the memory device, is described. For example, 5V is applied, and a predetermined read voltage, for example, -5V, is applied to the upper electrode 32. Then, a voltage of 0 V is applied to the pad conductive layer 24.

Under such voltage application conditions, first and second conductive channels 22a and 28a are formed in the first and second channel layers 22 and 28, respectively, and are formed between the charge storage layer 30 and the pad conductive layer 24. An electric potential difference in the opposite direction to that at the time of the recording is formed at. Accordingly, the electrons stored in the charge storage layer 30 are emitted to the outside via the second channel layer 28, the conductive layer 26, the first channel layer 22, and the pad conductive layer 24. Thereafter, when the voltage applied to the lower electrode 22 is maintained at 0 V, the charge storage layer 30 is kept empty. This state becomes the same as writing bit data 0 in the memory element of the present invention. Sensing means (not shown) connected to the pad conductive layer 24 recognizes the flow of electrons above the reference value flowing from the pad conductive layer 24. When the flow of electrons emitted from the charge storage layer 30 is recognized in this manner, it is assumed that bit data 1 is read from the memory device of the present invention. When the flow of electrons is not recognized, it is assumed that bit data 0 is read from the memory element of the present invention.

On the other hand, when bit data 1 is read from the memory device of the present invention, as can be seen from the comparison of FIGS. 16 and 17, the charge storage layer 30 is empty, and the bit data 0 is stored in the memory device. It will be as recorded. In other words, by reading the bit data 1, the bit data write state of the memory element of the present invention is changed, and in order to keep the write state of the memory element of the present invention in its original state and soon to be in a nonvolatile state, the bit data 1 After reading, the refresh process is performed according to the same method as that of writing the bit data 1 described with reference to FIG. 14.

 Figure 18 shows an array of memory elements of the present invention capable of writing and reading four bits of data.

In the voltage application state as shown in FIG. 18, the first and second channel layers 22 and 28 of the memory elements belonging to the first array G1 are turned on and the memory elements belonging to the second array G2. First and second channel layers 22, 28 in the off state. Accordingly, currents corresponding to bit data written in the memory elements belonging to the first array G1 flow through the first to fourth bit lines B1, B2, B3, and B4, and the first to fourth comparators ( It can be seen that data written in the memory elements belonging to the first array G1 through C1, C2, C3, and C4 are 1, 0, 1, and 1, respectively.

While many details have been set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those skilled in the art to which the present invention belongs,

The first and second channel layers 20 28 may be horizontally offset. In addition, the vertically stacked channel layer and other members may be provided on a horizontal plane. In addition, instead of the MIT (Metal Insulator Transition) material layer in which physical properties change to conductive or insulating properties according to the applied voltage, a material layer capable of blocking the flow of current according to magnetic properties may be used. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, in the memory element of the present invention, charges used for data writing, that is, electrons, do not suffer from tunneling. Therefore, data can be written or read at high speed, and data can be erased at high speed. In addition, since the tunneling film is not used, there is no need to consider a problem due to deterioration of the tunneling film. In addition, since charge is directly injected into the storage node without passing through the tunneling layer, the operating voltage can be lowered and power consumption can be reduced than when passing through the tunneling layer.

Claims (31)

A first channel layer; A second channel layer spaced apart from the first channel layer; A conductive layer connecting the first and second channel layers; A pad conductive layer connected to the first channel layer; A charge storage layer connected to the second channel layer; A first gate controlling on and off of the first channel layer; And And a second gate for controlling on and off of the second channel layer and relating to concentration of charge to the charge storage layer and release of charge from the charge storage layer. The memory device of claim 1, wherein the first and second gates and the pad conductive layer are provided in parallel. The memory device of claim 1, wherein the first and second gates are disposed vertically, and the pad conductive layer and the second gate are provided in parallel. The memory device of claim 1, wherein the first and second channel layers are provided in parallel. The memory device of claim 1, wherein the first and second channel layers are disposed vertically. 2. The memory device of claim 1, wherein the first and second channel layers are phase transition layers in which physical properties change from conductive to insulating or vice versa under an electric field of a predetermined intensity. 7. The memory device of claim 6, wherein the phase change layer is a vanadium oxide (VOx) layer or Ni0x. The memory device of claim 1, wherein the charge storage layer is any one of a metal layer and a polysilicon layer. 2. The method of claim 1, wherein the second gate comprises a first portion that controls on and off of the second channel layer, and wherein the second gate relates to concentration of charge in the charge storage layer and release of charge from the charge storage layer. A memory device, characterized in that divided into two parts. The memory device of claim 9, wherein the first channel layer and the second channel layer are perpendicular to each other, and the charge storage layer and the second channel layer are provided in parallel. Forming a first gate; Forming a first insulating layer on the first gate; Forming conductive first and second patterns spaced apart on the first insulating layer; Forming a first channel layer on the first insulating layer between the first and second patterns; Forming a second insulating layer covering the first and second patterns and the first channel layer on the first insulating layer; Forming a via hole in the second insulating layer to expose the second pattern; Filling the via hole with a conductive plug; Forming a conductive layer pattern covering the exposed surface of the conductive plug, a second channel layer, and a charge storage layer on the second insulating layer, wherein the conductive layer pattern is in contact with each other; Forming a third insulating layer on the second insulating layer to cover the conductive layer pattern, the second channel layer, and the charge storage layer; Forming a second gate on the third insulating layer; And And exposing a portion of the first pattern. 12. The method of claim 11, wherein at least one of the first and second channel layers is formed as a phase change layer in which physical properties vary from conductive to insulating or vice versa under an electric field of a predetermined intensity. The method of claim 11, wherein the charge storage layer is formed of any one of a metal layer and a polysilicon layer. The method of claim 12, wherein the phase transition layer is formed of a vanadium oxide (VOx) layer or nickel oxide (NiOx) deposition. Forming a first gate of a predetermined thickness; Forming a first insulating layer on the first gate; Forming a first channel layer and a conductive layer pattern on the first insulating layer to be in contact with each other; Forming a second insulating layer on the first insulating layer to cover the conductive layer pattern and the first channel layer; Forming a via hole in the second insulating layer to expose the first channel layer; Filling the via hole with a conductive plug; Forming a second channel layer and a charge storage layer on the second insulating layer, the second channel layer covering the exposed entire surface of the conductive plug and in contact with each other; Forming a third insulating layer on the second insulating layer to cover the second channel layer and the charge storage layer; Forming a second gate on the third insulating layer; And And exposing a portion of the conductive layer pattern. 16. The method of claim 15, wherein at least one of the first and second channel layers is formed as a phase change layer in which physical properties vary from conductive to insulating or vice versa under an electric field of a predetermined intensity. The method of claim 11, wherein the charge storage layer is formed of any one of a metal layer and a polysilicon layer. The method of claim 16, wherein the phase change layer is formed of a vanadium oxide (VOx) layer or nickel oxide (NiOx). Forming a groove having a predetermined depth in the first insulating layer; Filling the groove with a conductive layer; Forming a first channel layer on a predetermined region of the conductive layer, and forming a first gate facing the first channel layer on the first insulating layer adjacent to the first channel layer; Forming a second insulating layer on the first insulating layer to cover the conductive layer, the first channel layer, and the first gate; Planarizing an upper surface of the second insulating layer to expose the first channel layer; Forming a conductive layer pattern covering the exposed portions of the first channel layer, the second channel layer, and the charge storage layer on different regions of the second insulating layer, each of which is in contact with each other; Sequentially stacking a third insulating layer and a second gate covering the conductive layer pattern, the second channel layer, and the charge storage layer on the second insulating layer; And Exposing a portion of the conductive layer. 20. The method of claim 19, wherein at least one of the first and second channel layers is formed as a phase change layer in which physical properties vary from conductive to insulating or vice versa under an electric field of a predetermined intensity. 20. The method of claim 19, wherein the charge storage layer is formed of any one of a metal layer and a polysilicon layer. 20. The method of claim 19, wherein the phase transition layer is formed by a vanadium oxide (VOx) layer or nickel oxide (NiOx) deposition. Forming a first gate of a predetermined thickness; Forming a first insulating layer on the first gate; Forming conductive first and second patterns on the first insulating layer; Forming a first channel layer on the first insulating layer between the first and second patterns; Forming a second insulating layer covering the first and second patterns and the first channel layer on the first insulating layer; Polishing the second insulating layer until the top surface of the second pattern is exposed; Forming a second channel layer and a second gate on the exposed second pattern and the second insulating layer adjacent thereto; Forming a third insulating layer on the second insulating layer to cover the second channel layer and the second gate; Planarizing an upper surface of the third insulating layer to expose the second channel layer; Forming a charge storage layer on the third insulating layer to cover an exposed surface of the second channel layer; Forming a fourth insulating layer covering the charge storage layer on the third insulating layer; And Forming an electrode layer on the fourth insulating layer. 24. The method of claim 23, wherein at least one of the first and second channel layers is formed as a phase change layer in which physical properties vary from conductive to insulating or vice versa under an electric field of a predetermined intensity. 24. The method of claim 23, wherein the charge storage layer is formed of any one of a metal layer and a polysilicon layer. 24. The method of claim 23, wherein the phase transition layer is formed of a vanadium oxide (VOx) layer or nickel oxide (NiOx) deposition. Controlling on and off of the first and second channel layers, a conductive layer connecting them, a pad conductive layer connected to the first channel layer, a charge storage layer connected to the second channel layer, and the first channel layer. And a second gate to control the on and off of the second channel layer, the second gate being related to concentration of charge in the charge storage layer and release of charge from the charge storage layer. To A first step of applying a predetermined write voltage to the first and second gates, respectively, to change the physical properties of the first and second channel layers to conductive; And And maintaining a predetermined potential difference between the charge storage layer and the pad conductive layer such that charge flows into the charge storage layer. 28. The method of claim 27, further comprising: after the second step, adjusting the voltage applied to the first gate to change the physical properties of the first channel layer to insulation; And And adjusting a voltage applied to the second gate to change the physical properties of the second channel layer into insulating properties. Controlling on and off of the first and second channel layers, a conductive layer connecting them, a pad conductive layer connected to the first channel layer, a charge storage layer connected to the second channel layer, and the first channel layer. And a second gate to control the on and off of the second channel layer, the second gate being related to concentration of charge in the charge storage layer and release of charge from the charge storage layer. To A first step of applying a predetermined read voltage to the first and second gates to convert the physical properties of the first and second channel layers to conductive; And And maintaining a predetermined potential difference between the charge storage layer and the pad conductive layer to release charge stored in the charge storage layer. 30. The method of claim 29, further comprising: a third step of changing the physical property of the first channel layer to insulation by adjusting a voltage applied to the first gate after the second step; And And adjusting a voltage applied to the second gate to change the physical properties of the second channel layer into insulating properties. 31. The method of claim 30, wherein after the fourth step, a refresh process is performed to restore the state of the charge storage layer to its original state.

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