KR20030001912A - Method for manufacturing a flash memory cell - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory cell, wherein a drain region is formed to partially overlap with a floating gate to be programmed by injection of hot electrons, and a spacer and a nitride film are formed on both sidewalls of the gate electrode. The region is formed to further secure an effective channel length as much as the thickness of the spacer and the nitride film.

Description

Method for manufacturing a flash memory cell {Method for manufacturing a flash memory cell}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to a method of manufacturing a flash memory cell capable of effectively securing an effective channel length.

In general, as the semiconductor device is highly integrated, the width of the pattern is finely reduced, thereby causing various problems related to deterioration of the electrical characteristics of the device.

Among them, the decrease in the channel length due to the decrease in the width of the gate electrode causes many problems in the manufacture of the flash memory device. Then, the problem will be described through the manufacturing process of the conventional flash memory cell.

1A to 1C are cross-sectional views of devices for describing a method of manufacturing a conventional flash memory cell.

FIG. 1A is a cross-sectional view of a tunnel oxide film 2 and a first polysilicon layer 3 sequentially formed on a semiconductor substrate 1 on which an isolation layer is formed, and then patterned to form a floating gate 3. The floating gate 3 is patterned in the Y direction.

FIG. 1B sequentially forms the dielectric film 4, the second polysilicon layer 5, the tungsten silicide layer 6, and the insulating film 7 on the entire upper surface thereof, and then uses the Self Align Etch method. A control gate comprising a second polysilicon layer 5 and a tungsten silicide layer 6 by sequentially patterning the insulating film 7, the tungsten silicide layer 6, the second polysilicon layer 5, and the dielectric film 4. A sectional view of a state in which 6a is formed, wherein the control gate 6a is patterned in the X direction.

FIG. 1C is a cross-sectional view of a state in which impurity ions are implanted into the exposed semiconductor substrate 1 to form source and drain regions 8 and 9, and then heat-treated to improve the data storage capability by activating the implanted impurity ions.

However, as the device is highly integrated, the width of the gate electrode is reduced to 0.18 μm or less, and according to the conventional method described above, side diffusion of ions implanted into the source and drain regions 8 and 9 occurs during the heat treatment. Since the channel length is reduced, the electrical characteristics of the device are degraded, such as punch through during operation of the device.

Thus, a method of increasing the concentration of channel ions to prevent punch through or forming shallow source and drain regions 8 and 9 to secure a margin for reducing channel length has been proposed. The depth of the source and drain regions 8 and 9 is reduced because of the loss of the semiconductor substrate 1 by etching in the subsequent contact hole formation process for exposing 8 and 9, thereby resulting in junction leakage. Is generated and the reliability of the device is lowered.

Therefore, in the present invention, the drain region is partially overlapped with the floating gate to be programmed by the injection of hot electrons, and spacers and nitride films are formed on both sidewalls of the gate electrode, and then source regions are formed to match the thickness of the spacer and nitride film. It is an object of the present invention to provide a method of manufacturing a flash memory cell which can solve the above-mentioned disadvantages by further securing an effective channel length of.

A method of manufacturing a flash memory cell according to the present invention for achieving the above object comprises the steps of forming a gate electrode having a structure in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are sequentially stacked on a semiconductor substrate; Implanting impurity ions into the semiconductor substrate at one side to form a drain region, and then performing heat treatment, forming spacers on both side walls of the gate electrode, and sequentially forming a nitride film and an interlayer insulating film on the entire upper surface; Patterning the insulating film and the insulating film sequentially to form a contact hole to expose the semiconductor substrates on both sides of the gate electrode, implanting impurity ions into the semiconductor substrate exposed through the contact hole, and then performing heat treatment to complete formation of the drain and source regions. Characterized in that it comprises a step, according to the present invention Another method of manufacturing a flash memory cell includes forming a gate electrode having a structure in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are sequentially stacked on a semiconductor substrate, and implanting impurity ions into a semiconductor substrate on one side of the gate electrode. And forming heat treatment after forming the drain region, and forming spacers on both side walls of the gate electrode, and implanting impurity ions into the semiconductor substrate on the other side of the gate electrode to form and heat-process the source region. It is characterized by.

1A to 1C are cross-sectional views of elements for explaining a method of manufacturing a conventional flash memory cell.

2A to 2C are cross-sectional views of elements for explaining the first embodiment of the present invention.

3A to 3D are cross-sectional views of elements for explaining the second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1, 11 and 21: semiconductor substrate 2, 12 and 22: tunnel oxide film

3: first polysilicon layers 4, 14 and 24: dielectric film

5: second polysilicon layer 6, 16, and 26: tungsten silicide layer

6a, 16a, and 26a: control gate 7: insulating film

8, 32, and 33: source region 9, 18, and 28: drain region

13 and 23: floating gates 15 and 25: polysilicon layer

17 and 27: insulating film pattern 19 and 29: spacer

20: nitride films 40 and 50: contact hole

41 and 51: interlayer insulating film

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2C are cross-sectional views of devices for explaining the first embodiment of the present invention.

FIG. 2A illustrates a structure in which a tunnel oxide film 12, a floating gate 13, a dielectric film 14, a control gate 16a, and an insulating film pattern 17 are sequentially stacked on a semiconductor substrate 11 on which an isolation layer is formed. The control gate 16a is formed of the polysilicon layer 15 and the tungsten silicide layer 16 as a cross-sectional view of a state in which a gate electrode is formed.

FIG. 2B shows a state in which impurity ions are implanted into the semiconductor substrate 11 of one side of the gate electrode to form a drain region 18 and then heat treated, and spacers 19 formed of an insulating film are formed on both sidewalls of the gate electrode. It is a cross section.

In FIG. 2C, the nitride film 20 and the interlayer insulating film 41 are sequentially formed on the entire upper surface thereof, and the interlayer insulating film 41 and the insulating film 20 are sequentially formed to expose the semiconductor substrate 11 at both sides of the gate electrode. The contact hole 40 is formed by patterning, impurity ions are injected into the semiconductor substrate 11 exposed through the contact hole 40, and then heat-treated to form the drain and source regions 18 and 32. In this case, the source region 32 is formed long in the form of a line.

3A to 3D are cross-sectional views of devices for explaining the second embodiment of the present invention.

3A illustrates a structure in which a tunnel oxide film 22, a floating gate 23, a dielectric film 24, a control gate 26a, and an insulating film pattern 27 are sequentially stacked on a semiconductor substrate 21 on which an isolation layer is formed. As a cross-sectional view of a state in which a gate electrode is formed, the control gate 26a is formed of a polysilicon layer 25 and a tungsten silicide layer 26.

FIG. 3B illustrates a state in which impurity ions are implanted into the semiconductor substrate 21 at one side of the gate electrode to form a drain region 28 and then heat treated, and spacers 29 formed of an insulating film are formed on both sidewalls of the gate electrode. It is a cross section.

FIG. 3C is a cross-sectional view of a source region 33 formed by implanting impurity ions into the semiconductor substrate 21 of the other side of the gate electrode and then heat-processing, wherein the source region 33 is in a line form. Form long.

3D illustrates that the nitride film 30 and the interlayer insulating film 51 are sequentially formed on the entire upper surface thereof, and then the interlayer insulating film 51 and the nitride film are exposed so that the semiconductor substrate 21 of the drain and source regions 28 and 33 is exposed. A cross-sectional view of a state in which the contact holes 50 are formed by sequentially patterning the 30s, and then a plug is formed in the contact holes 50 so as to be connected to the upper layer.

Since the flash memory cell having the above structure is programmed as hot electrons generated in the channel are injected into the floating gate 13 or 23, the drain region 18 or 28 is changed to the floating gate 13 or 23. ) And some overlap.

Therefore, in the present invention, the drain region 18 or 28 is formed to partially overlap the floating gate 13 or 23, the spacers 19 or 29 are formed on both sidewalls of the gate electrode, and then the source region 32 or 33 is formed. As a result, the program characteristic is improved, and the effective channel length as much as the thickness of the spacer 19 or 29 and the nitride film 20 or 30 can be further ensured.

In addition, the present invention forms a source region so as not to overlap the floating gate so that the threshold voltage of the memory cell can be increased, thereby reducing the concentration of channel ions, thereby preventing junction breakdown from occurring. .

As described above, the present invention forms a drain region to partially overlap with the floating gate so that a program by hot electron injection is performed, and after forming spacers and nitride films on both side walls of the gate electrode, the source does not overlap with the floating gate. The region is formed so that the effective channel length as much as the thickness of the spacer and the nitride film is ensured, and the concentration of channel ions can be reduced.

Therefore, it is possible to form a shallow depth of the junction region to prevent junction leakage, and to maintain the threshold voltage at a low channel ion concentration as in the prior art to prevent the occurrence of junction failure. Therefore, using the present invention improves the reliability and yield of the device.

Claims (4)

Forming a gate electrode having a structure in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are sequentially stacked on a semiconductor substrate; Implanting impurity ions into the semiconductor substrate at one side of the gate electrode to form a drain region and then performing heat treatment; Forming spacers on both side walls of the gate electrode and sequentially forming a nitride film and an interlayer insulating film on the entire upper surface thereof; Patterning the interlayer insulating film and the insulating film sequentially to form contact holes to expose the semiconductor substrates at both sides of the gate electrode; And implanting impurity ions into the semiconductor substrate exposed through the contact hole, and then performing heat treatment to complete formation of a drain and a source region. The method of claim 1, And the control gate is made of polysilicon and tungsten silicide. Forming a gate electrode having a structure in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are sequentially stacked on a semiconductor substrate; Implanting impurity ions into the semiconductor substrate at one side of the gate electrode to form a drain region and then performing heat treatment; And forming spacers on both sidewalls of the gate electrode, and implanting impurity ions into the semiconductor substrate on the other side of the gate electrode to form a source region and heat treatment. . The method of claim 3, wherein And the control gate is made of polysilicon and tungsten silicide.