KR20010045183A - Method for manufacturing dual gate electrodes of CMOS device - Google Patents

Abstract

Disclosed is a method for fabricating a CMOS dual gate electrode of a semiconductor device capable of preventing dopant diffusion of a doped polysilicon film in an n + / p + dual gate electrode of a CMOS transistor to improve electrical characteristics of the semiconductor device. The present invention forms p-wells and n-wells adjacent to each other in a substrate on which a device isolation film is formed, sequentially deposits a gate insulating film and amorphous silicon on the entire surface of the substrate, and selectively adds n + impurities only to the amorphous silicon film in the p-well region. After implanting, injecting p + impurities only into the amorphous silicon film of the n-well region, and performing a cleaning process using H ₂ O ₂ and H ₂ SO ₄ to form a diffusion barrier layer on the amorphous silicon film to prevent the diffusion of impurities After the tungsten silicide film is deposited on the diffusion barrier, a rapid heat treatment is performed to crystallize the tungsten silicide, and a photo and etching process using a gate mask is performed to pattern the stacked metal silicide film, the diffusion barrier, and the doped polysilicon film. Thus, dual gate electrodes are formed on the p-well and n-well substrates, respectively.

Description

Method for manufacturing dual gate electrodes of CMOS device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a CMOS dual gate electrode of a semiconductor device capable of improving the electrical characteristics of a transistor by preventing impurity diffusion of an n + / p + dual gate.

In general, a CMOS transistor is doped with n-type impurities so as to exhibit conductivity in a polysilicon film as gate electrodes of NMOS and PMOS. As a result, the NMOS transistor operates in a surface channel mode in which a channel is formed near the substrate surface, and in the case of a PMOS transistor, a buried channel mode in which a channel is formed deeper than the substrate surface. Will work.

However, as the degree of integration of semiconductor devices increases, the gate length of MOS transistors also decreases. Recently, a device design has been made to have a gate length of about 0.2 μm or less for a 1 Giga-class dynamic random access memory (DRAM) device. The reduced channel length also shortens the effective channel length, so that the channel region is strongly influenced by the depletion layer charge, electric field, and potential distribution of the source / drain regions as well as the gate voltage. effect) will occur. This short-channel effect is accompanied by a drop in threshold voltage, a breakdown in source / drain breakdown voltage, and a drop in sub-threshold characteristics.

Therefore, in the case of a PMOS transistor having a gate doped with an n-type impurity, the characteristics of the PMOS transistor are degraded due to the short-channel effect. Therefore, the channel length must be longer than that of the NMOS transistor, and the threshold voltage is also increased. Had to be high.

In addition, in recent years, a structure change is required to a surface channel type PMOS transistor instead of a PMOS transistor having a buried channel in accordance with the shrinkage of semiconductor devices and low power supply operation specifications.

For the production of surface channel type PMOS transistors, p-type impurities are doped as conductive type impurities in polysilicon. That is, the gate electrodes of the surface channel NMOS and PMOS transistors each include polysilicon doped with n-type impurities and p-type impurities in the polysilicon film.

However, when the gate electrode is formed by stacking tungsten silicide on top of the doped polysilicon for low resistance of the gate electrode in the manufacturing process of the surface channel type PMOS transistor, the dopant in the polysilicon film is formed by the upper tungsten due to the subsequent thermal process. Diffusion occurs in the silicide film, resulting in non-uniform concentration of p-type impurities (eg, boron) in the polysilicon film. As a result, the threshold voltage of the surface channel PMOS transistor is reduced and the on / off characteristic is deteriorated, thereby degrading the operating margin and electrical characteristics of the transistor including the dual gate.

An object of the present invention is to solve the above problems of the prior art, by adding a diffusion barrier between the doped polysilicon film and the metal silicide film in the n + / p + dual gate structure of the CMOS transistor dopant of the doped polysilicon film The present invention provides a method for manufacturing a CMOS dual gate electrode of a semiconductor device that prevents diffusion and improves electrical characteristics of a semiconductor device by reducing Rs of a word line by applying a rapid thermal processing (RTP) process.

1 to 8 are cross-sectional views illustrating a manufacturing process of a CMOS transistor having a dual gate electrode according to the present invention.

Explanation of symbols on the main parts of the drawings

10: silicon substrate 11: p-well

12: n-well 14: device isolation film

16: gate insulating film 18: amorphous silicon film

18a: n + doped silicon film 18b: p + doped silicon film

18a ', 18b': doped polysilicon film 20,22: photoresist pattern

24: diffusion barrier film 26: tungsten silicide film

G: gate electrode 28: spacer

30a, 30b: source / drain regions

In order to achieve the above object, the present invention provides a method of manufacturing a dual gate electrode of a semiconductor CMOS transistor, comprising: forming an isolation layer on a semiconductor substrate, and forming p-wells and n-wells adjacent to each other in the substrate on which the isolation layer is formed; And depositing a gate insulating film on the entire surface of the substrate, depositing amorphous silicon on the gate insulating film, selectively implanting n + impurities only into the amorphous silicon film in the p-well region, and amorphous in the n-well region. Implanting p + impurities only into the silicon film, performing a cleaning process using H ₂ O ₂ and H ₂ SO ₄ on the resultant to form a diffusion barrier layer on the amorphous silicon layer to prevent diffusion of impurities; Laminating a metal silicide film on top, performing a rapid heat treatment process on the metal silicide film, and laminating the metal silicide film Film, a diffusion film, and a doped bit by patterning a polysilicon film and a step of respectively forming the dual-gate electrode over the substrate in the p- well and the n- well.

In the production method of the present invention, the ratio of H ₂ O ₂ to H ₂ SO ₄ is 4: 1 at the time of forming the diffusion barrier, and the film thickness is about 15 to 25 kPa.

In the production method of the present invention, the rapid heat treatment process is performed in an N ₂ atmosphere for 10 to 30 seconds at a temperature of 900 ~ 1100 ℃. Preferably, the rapid heat treatment process is a reaction temperature of 950 ℃, N ₂ in 3L atmosphere for 20 seconds.

In the production method of the present invention, the metal silicide film is tungsten silicide.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 to 8 are cross-sectional views illustrating a manufacturing process of a CMOS transistor having a dual gate electrode according to the present invention. Referring to this, a method of manufacturing a dual gate electrode having a metal polyside structure according to the present invention is as follows.

First, as shown in FIG. 1, an isolation layer 14 for defining an active region and an inactive region of a semiconductor device is formed on a p-type silicon substrate 10 as a semiconductor substrate. Then, p-wells 11 and n-wells 12 that are adjacent to each other are formed in the substrate on which the device isolation film 14 is formed. A gate insulating film 16 of about 30 to 50 kV is formed on the entire surface of the substrate 10. The insulating film 16 can be obtained by a wet oxidation process of about 800 ° C. and N ₂ O annealing. Here, the N ₂ O annealing step proceeds at a temperature of 900 ° C. for 30 minutes.

Next, as shown in FIG. 2, amorphous silicon 18 is deposited on the gate insulating layer 16. At this time, the deposition process of the amorphous silicon film 18 is deposited using a Si ₂ H ₆ to a thickness of 700 to 1000 Pa at a temperature of 480 to 550 ° C. under a pressure of 0.1 to 1.0 torr. Here, the thickness of the preferred amorphous silicon film 18 is 800 kPa.

As shown in FIG. 3, a photoresist pattern 20 is formed on the substrate to open only the amorphous silicon film of the p-well 11, and P31 is ion implanted as an n + impurity (see 18a). . At this time, the ion implantation step of P31 sets the energy intensity to 12 to 20 KeV and the dose amount to 1.0 to 6.0E15 / cm 2.

Then, the photoresist pattern 20 is removed. As shown in FIG. 4, a photoresist pattern 22 is formed on the substrate to open only an amorphous silicon film of the n-well 12 region, and B11 is ion implanted as a p + impurity (see 18b). At this time, in the ion implantation step of B11, the energy intensity is 4 to 6 KeV and the dose is 1.0 to 6.0E15 / cm 2.

Subsequently, as shown in FIG. 5, the cleaning process is performed using H ₂ O ₂ and H ₂ SO ₄ during the cleaning process performed before the metal polyside such as tungsten silicide is formed in the resultant. As a result, a diffusion barrier layer 24 is formed on the upper surfaces of the amorphous silicon layers 18a and 18b implanted with n + / p + dopants on the p-wells 11 and n-wells 12, respectively. . Here, at the time of formation of the diffusion barrier film 24, the ratio of H ₂ O ₂ to H ₂ SO ₄ is 4: 1, and the film thickness thereof is about 15 to 25 kPa.

Next, as shown in FIG. 6, tungsten silicide is deposited on the diffusion barrier 24 as a metal film 26 at about 800-1500 kV. At this time, the thickness of the preferable tungsten silicide film 26 is 1100 kPa.

Then, a rapid thermal process is performed to crystallize the tungsten silicide film 26 and doped polysilicon 18a 'and 18b' on the amorphous silicon films 18a and 18b. At this time, the rapid heat treatment process is carried out in N ₂ atmosphere for 10 to 30 seconds at a temperature of 900 ~ 1100 ℃, the preferred heat treatment process conditions is _{2 2} N ₂ in a temperature of 950 ℃ and 20 seconds. Then, activation of n + / p + impurities in the doped polysilicon films 18a 'and 18b' is increased by a rapid heat treatment process. In addition, although the diffusion prevention film between the tungsten silicide film and the doped polysilicon film serves as a dielectric material, the specific resistance of the doped polysilicon may deteriorate. Can be lowered.

Subsequently, as shown in FIG. 7, the tungsten silicide layer 26 ', the diffusion barrier layer 24', and the doped polysilicon layers 18a 'and 18b are sequentially stacked by performing a photolithography and an etching process using a gate mask. ') Is patterned to form dual gate electrodes G on the substrates of the p-well 11 and the n-well 12, respectively. In this case, the gate insulating layer 16 is also etched to be aligned with the dual gate electrode G.

Next, as shown in FIG. 8, a silicon nitride film is deposited on the entire surface of the substrate as an insulating material and etched by dry etching to form a spacer 28 on the sidewall of the dual gate electrode G. Referring to FIG.

In addition, a source in which n + / p + impurities are implanted into the substrate between the gate electrode G and the device isolation layer 14 of the p-well 11 and n-well 12 by performing normal source / drain ion implantation The / drain regions 30a and 30b are formed to complete the NMOS and PMOS transistors having the CMOS dual gate electrode of the tungsten polyside structure according to the present invention.

A semiconductor device having a dual gate electrode of a CMOS transistor according to the above manufacturing process is provided with a diffusion barrier layer formed by a cleaning process of NH ₄ OH + H ₂ O ₂ between a lower polysilicon and an upper tungsten silicide in the gate electrode, thereby providing a surface. Phosphorus (P) and boron (B), which are dopants in the n + / p + polysilicon film for the channel transistor, can be prevented from diffusing into the upper tungsten silicide film. Accordingly, the internal diffusion of the dopant in the gate electrode of the NMOS and PMOS transistors can be blocked to minimize the increase of the threshold voltage of the corresponding transistor, and the doping concentration of the polysilicon film can be increased to fundamentally eliminate the gate depletion.

In addition, the diffusion barrier in the gate electrode of the present invention blocks the path in which the fluorine-based ions diffused from the upper tungsten silicide diffuses to the gate insulating film / substrate in advance, thereby increasing the dopant concentration in the polysilicon film, in particular, the boron concentration (fluorine diffusion of boron). It is possible to maintain a constant to prevent the deterioration of the gate insulating film quality and to improve the time dependent dielectric breakdown (TDDB) characteristics.

As described above, the present invention prevents the dopant diffusion of the doped polysilicon film by adding an insulating diffusion preventing film between the doped polysilicon film and the metal silicide film in the surface channel type n + / p + dual gate structure of the CMOS transistor. Device characteristics such as reducing the threshold voltage and suppressing gate depletion can be improved.

In the present invention, the size of the PMOS transistor of the semiconductor device can be the same as that of the NMOS transistor, thereby increasing the total number of net dies, and the threshold voltages of the NMOS and PMOS transistors can be the same, while maintaining a low threshold voltage. Leakage characteristics can be secured and can be used for manufacturing low voltage semiconductor devices.

Claims (5)

In the method of manufacturing a dual gate electrode of a semiconductor CMOS transistor, Forming an isolation layer on the semiconductor substrate; Forming p-wells and n-wells adjacent to each other in the substrate on which the device isolation film is formed; Depositing a gate insulating film on the entire surface of the substrate; Depositing amorphous silicon on the gate insulating film; Selectively implanting n + impurities only into the amorphous silicon film of the p-well region and implanting p + impurities only into the amorphous silicon film of the n-well region; Performing a cleaning process using H ₂ O ₂ and H ₂ SO ₄ on the resultant to form a diffusion barrier layer on the amorphous silicon layer to prevent diffusion of impurities; Stacking a metal silicide layer on the diffusion barrier layer; Performing a rapid heat treatment process on the metal silicide film; And And patterning the stacked metal silicide layer, the diffusion barrier layer, and the doped polysilicon layer to form dual gate electrodes on the p-well and n-well substrates, respectively. Dual gate electrode manufacturing method. The method of claim 1, wherein the ratio of H ₂ O ₂ to H ₂ SO ₄ is 4: 1 and the film thickness is about 15 to 25 GPa when forming the diffusion barrier. Way. The method of claim 1, wherein the rapid heat treatment is performed in an N ₂ atmosphere at a temperature of 900 to 1100 ° C. for 10 to 30 seconds. 4. The method of claim 3, wherein the rapid heat treatment is performed at a reaction temperature of 950 ° C. and N ₂ at 3 L for 20 seconds. The method of claim 1, wherein the metal silicide layer is tungsten silicide.