KR20010017640A - Utopia interface unit having self loop-back test mode - Google Patents

Abstract

The present invention relates to a utopia interface device in which a circuit for a self loopback test is implemented. The present invention facilitates local loopback testing of the chip itself by adding a simple function when implementing a VLSI device using a utopia interface. It also saves time and costs for implementing a separate device (FPGA) for testing VLSI devices at the board level.

Description

UTOPIA INTERFACE UNIT HAVING SELF LOOP-BACK TEST MODE}

The present invention relates to a utopia interface device, and more particularly, to a utopia interface device having a circuit for a self loopback test and configured to facilitate a local loopback test of a chip itself.

The Utopia interface is a standard specification for the interface between the ATM layer and the physical layer in ATM Forum. This interface is used in nearly all commercial chips with ATM and physical layer capabilities.

1 illustrates a general utopia interface structure. As shown, a chip having an ATM layer utopia interface is referred to as "Chip A" 15, and a chip having a physical layer utopia interface is referred to as a "chip B" 16. In the interface, transmission (Tx) and reception (Rx) directions are determined based on the flow direction of data around the ATM layer. In other words, the direction in which data is transmitted from the ATM layer 11 to the physical layer 12 is set as transmission (Tx), and the direction in which the ATM layer 13 receives data from the physical layer 14 is determined as reception (Rx). . In addition, it is basically synchronized with the transmit clock TxCLK (s1) and the receive clock RxCLK (s7) provided by the ATM layer. The physical layer receives this clock and uses it to transmit and receive data. This is for the ATM layer to act as a master for accessing several different physical layers.

On the other hand, the Utopia interface has Level 1 and Level 2 specifications according to the number of physical layers attached to the ATM layer. The present technology can be used for both Levels 1 and 2. Utopia level 2 is a protocol for communicating in a multi-physical environment. The utopian level 2 basically accommodates the utopia level 1 but additionally includes an address signal.

In FIG. 1, the utopia transmission interface signal is a signal indicating that transmission data TxDATA (s2) indicating data transmitted from the ATM layer 11 to the physical layer 12 and that the transmission data TxDATA are valid (Valid). TxEnb *) (s4), a signal (TxSOC) (s3) indicating a cell start of the transmission data (TxDATA), and a signal (TxClav / TxFull *) (s5) (hereinafter referred to as a signal having information that a cell can be received from the physical layer). (TxClav), a clock (TxClk) transmitted from the ATM layer to the physical layer for data transmission and synchronization, an address needed for address falling when multiple physical layers are encountered at level 2. (TxAddr [4: 0] (s6). Also, the utopia reception interface signal is a clock signal RxClk (s7) transmitted from the ATM layer 13 to the physical layer 14, and the reception data received from the physical layer at the ATM layer. (RxDATA) (7: 0) (s8), cell start of the received data RxDATA The signal RxSOC (s9), the signal RxEnb * (s10) used as a read window of the reception data RxDATA and the start signal RxSOC, and the data to be transmitted in the physical layer. RxEmpty * RxClav (s11) (hereinafter referred to as "RxClav") to indicate the status of the address, address sent by the ATM layer to select one physical layer among several physical layers at level 2 (RxAddr [4] : 0]) (s12) signal Other details about the utopia interface are well known to those skilled in the art by a well-known standard, and further description thereof is omitted.

On the other hand, the utopia interface device of FIG. 1 is the first to loopback a chip A 15 (or chip B 16) having a Utopia interface of an AMT layer (or a physical layer) to a utopia loopback test. Function, and second, a loopback test by implementing a utopian interface of a relative layer (ATM is a physical and physical ATM layer) for interfacing outside the chip. In addition to the burden of implementing a separate additional logic when the loopback test is performed by inserting the inner loopback function, there is a disadvantage that the chip operation is not seen from the outside, and the second method, the external loopback test method, is selected. Barely, the system was burdened by the need for a separate circuit for testing.

Accordingly, an object of the present invention is to provide a utopia interface device that supports a loopback function of the chip itself by providing a simple internal logic and provides convenience of chip testing even when the system is implemented. .

In addition, another object of the present invention is to facilitate the local loopback test of the chip itself by adding a simple function when implementing a VLSI device using a utopia interface, and the implementation of the VLSI device implemented at the board level (board level) The test provides a utopia interface that saves time and costs for the tongue of a separate device (FPGA) for testing.

1 is a block diagram of a general utopia interface device;

Figure 2 is an embodiment circuit diagram for a self loopback test of the device using the utopia interface device according to the present invention.

* Description of the main symbols in the drawing

21: ATM layer utopia transmitter 22: physical layer receiver

23: ATM layer receiver 24: physical layer utopia receiver

25: Master chip 26: Slave chip

27: physical layer utopia transmitter 28: ATM layer utopia receiver

29: physical layer utopia transmitter 210: ATM layer utopia receiver

211: External clock source where TxCLK occurs

212: Receive clock RxCLK occurs External clock source

According to an aspect of the present invention, there is provided a Utopia interface apparatus comprising: an ATM layer utopia transmitter, an ATM layer receiver integrated with a physical layer utopia transmitter, and an ATM layer utopia receiver; and a master for determining an internal mode of the ATM layer receiver. Means for inputting a slave / slave selection signal, means for correspondingly connecting an access signal of the ATM layer utopia transmitter and an access signal of the ATM layer receiver, and a transmission clock transmitted from the ATM layer to the physical layer for data transmission and synchronization Utopia interface for implementing a self-loopback test of ATM layer chips, comprising a first external clock source for generating a second external clock source for generating a receive clock transferred from the ATM layer to the physical layer for data transmission and synchronization. It is characterized in that the device.

In addition, the utopia interface device according to the present invention for achieving the above object, the physical layer utopia receiver, the physical layer utopia transmitter and the ATM layer utopia receiver integrated together, the physical layer receiver and the internal mode of the physical layer receiver is determined Means for inputting a master / slave selection signal, means for correspondingly connecting an access signal of the physical layer utopia receiver and an access signal of the physical layer receiver, and a data transmitted from the ATM layer to the physical layer for data transmission and synchronization. A first external clock source for generating a transmission clock and a second external clock source for generating a reception clock transferred from the ATM layer to the physical layer for data transmission and synchronization, thereby implementing a self loopback test of the physical layer chip. It is characterized by a utopia interface device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do. In the drawings, the same reference numerals are used for the same components as in the prior art.

2 shows a circuit structure for a self loopback test of a device using a utopia interface according to the present invention.

Referring to the left configuration of Fig. 2, an ATM layer utopia transmitter 21, an ATM layer receiver 23 in which a physical layer utopia transmitter 29 and an ATM layer utopia receiver 210 are integrated together, and the ATM layer receiver ( Means for inputting a master / slave selection signal (s13) for determining the internal mode of 23), and means for correspondingly connecting a connection signal of said ATM layer utopia transmitter 21 and a connection signal of ATM layer receiver 23; And a first external clock source 211 generating a transmit clock TxCLK transmitted from the ATM layer to the physical layer for data transmission and synchronization, and a received clock RxCLK transferred from the ATM layer to the physical layer for data transmission and synchronization. A configuration of a utopia interface device having a second external clock source 211 to generate a loopback test of an ATM layer chip is disclosed.

2, the physical layer utopia receiver 24, the physical layer utopia transmitter 27 and the ATM layer utopia receiver 28 are directly connected together, and the physical layer receiver Means for inputting a master / slave selection signal (s14) for determining the internal mode of 22) and means for correspondingly connecting a connection signal of the physical layer utopia receiver 24 and a connection signal of the physical layer receiver 22; And a first external clock source 211 generating a transmit clock TxCLK transmitted from the ATM layer to the physical layer for data transmission and synchronization, and a received clock RxCLK transferred from the ATM layer to the physical layer for data transmission and synchronization. Disclosed is a utopia interface device having a second external clock source 211 to generate a loopback test of a physical layer chip.

In FIG. 2, a chip A 25 having an ATM layer function will first be described. The difference from the chip 15 of FIG. 1 described above is that the receiver 23 includes the functions of the physical layer _utopia_receiver 27 attached to the AMT layer_utopia_transmitter 21, and the master / slave selection ( Master / Slave select) signal s13 is added. Inserting this level of functionality in an ultra high density integrated circuit (VLSI) implementation is rarely a problem because of the relatively small number of gates. In addition, the chip with the ATM Adaptation layer (AAL) usually supports both ATM and physical layer interfaces. In other words, these chips have little additional logic. However, this loopback function is not supported.

The main features of the present invention are as follows. In the utopia interface, the transmit / receive clocks s1 and s7 are transmitted from the ATM layer to the physical layer as described above with reference to FIG. 1. However, in the present invention, all of these clocks are received by an external clock source, the Utopia TxCLK source 211 and the Utopia RxCLK source 212. The reason for this is that RxClK (s7) should support bi-directional clock with reverse clock direction during loopback test. This can be caused by a clock waveform that is not clean or can cause delays. In addition, having the clocks received externally also reduces the timing margin on the utopia interface. In fact, chips that support both ATM and physical layer functions are often implemented to receive clocks externally. In the utopia interface, except for the clock and the address, the number of output signals of the transmitter 11 and the number of input signals of the receiver 13 are the same, and the number of input signals of the transmitter 11 and the number of output signals of the receiver 13 are the same. Thus, in the test mode, the TxData [7: 0] signal of FIG. 2 is connected to the RxData [7: 0], the TxSOC signal is connected to the RxSOC signal as it is, and the TxEnb * (s15) signal is the RxClav (s16) having the correct data direction. Signal), and the TxClav (s17) signal can be connected to RxEnb * (s18). Then, in the normal state according to the master / slave select signal (s13), it performs the function of (210) operating in the master (ATM) mode, and in the loopback test mode, RxData [ 7: 0] signal is a TxData [7: 0] signal, RxSOC is TxSOC, RxEnb * is TxClav, and RxClav is TxEnb *, and the physical layer_utopia_transmitter of (29) may be performed. That is, this problem can be easily solved by external master / slave mode selection signal s13, external supply of a clock, mapping of each signal, and insertion of a physical layer_utopia function.

The chip B 26, which is a device that forms a physical layer, may be implemented like the device chip A 25, which functions as the ATM layer described above. That is, in the test mode, the TxData [7: 0] signal connected to Chip B is connected to RxData [7: 0], the TxSOC signal is connected to the RxSOC signal as it is, and the TxEnb * (s15) signal is the RxClav with the correct data direction. (s16), and the TxClav (s17) signal may be connected to the RxEnb * (s18). Then, in the normal state according to the Master / Slave select signal (s14), it performs the function of (27) operating in Slave (PHY) mode, and in the loopback test mode, the TxData [7: 0] signal is RxData [7 With the signal: 0], TxSOC is considered to be RxSOC, TxEnb * is RxClav, and TxClav is RxEnb *, and the function of the ATM layer_utopia_transmitter of (28) may be performed.

Although the foregoing has been described with respect to embodiments of the present invention, those skilled in the art will understand that various implementations are possible within the scope of the technical idea of the present invention.

As described above, the present invention is a circuit implementation method for a whole loopback test of a device using a utopia interface, and by adding a simple function when implementing a VLSI device using a utopia interface, a local loopback of the chip itself is performed. This facilitates loopback testing and saves time and cost for the implementation of a separate device (FPGA) for testing when testing this VLSI device implemented at the board level.

Claims (3)

In the utopia interface device for implementing a self loopback test of an ATM layer chip, ATM layer utopia transmitter; An ATM layer receiver in which a physical layer utopia transmitter and an ATM layer utopia receiver are integrated together; Means for inputting a master / three slave selection signal for determining an internal mode of the ATM layer receiver; Means for correspondingly connecting a connection signal of said ATM layer utopia transmitter and a connection signal of an ATM layer receiver; A first external clock source for generating a transmission clock transmitted from the ATM layer to the physical layer for data transmission and synchronization; And A second external clock source that generates a receive clock that is transferred from the AMT layer to the physical layer for data transmission and synchronization. Utopia interface device, characterized in that made. In the utopia interface device for implementing a self loopback test of a physical layer chip, A physical layer utopia receiver; A physical layer receiver in which a physical layer utopia transmitter and an ATM layer utopia receiver are integrated together; Means for inputting a master / slave selection signal for determining an internal mode of the physical layer receiver; Means for correspondingly connecting a connection signal of the physical layer utopia receiver and a connection signal of the physical layer receiver; A first external clock source for generating a transmission clock transmitted from the ATM layer to the physical layer for data transmission and synchronization; A second external clock source that generates a receive clock that is passed from the ATM layer to the physical layer for data transmission and synchronization. Utopia interface device, characterized in that made. In the utopia interface device for implementing its own loopback test, An ATM layer comprising an ATM layer utopia transmitter, an ATM layer receiver integrated with a physical layer utopia transmitter and an ATM layer utopia receiver, and means for inputting a master / slave selection signal for determining an internal mode of the ATM layer receiver chip; First means for correspondingly connecting a connection signal of said ATM layer utopia transmitter and a connection signal of an ATM layer receiver; A first external clock source for generating transmissions transmitted from the ATM layer to the physical layer for data transmission and synchronization; A second external clock source for generating a receive clock transmitted from the ATM layer to the physical layer for data transmission and synchronization; A physical layer comprising a physical layer utopia receiver, a physical layer receiver integrated with a physical layer utopia transmitter and an ATM layer utopia receiver, and means for inputting a master / slave selection signal for determining an internal mode of the physical layer receiver. chip; And Second means for correspondingly connecting a connection signal of the physical layer utopia receiver and a connection signal of the physical layer receiver; Utopia interface device made, including.